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Document:	DMZ32 24-line Asynchronous Multiplexer User Guide
Order Number:	EK-DMZ32-UG
Revision:	001
Pages:	122
Original Filename:

OCR Text

EK-DMZ32-UG-001

DMZ32
User Guide

Prepared by Educational Services

of
Digital Equipment Corporation

1st Edition, June 1984

The information in this document is subject to change without notice and should not be
construed as a commitment by Digital Equipment Corporation. Digital Equipment
Corporation assumes no responsibility for any errors that may appear in this document.

Printed in U.S.A.

This document was set on a DIGITAL DECset Integrated Publishing System.

The following are trademarks of Digital Equipment Corporation:

Bngflanm
DEC
DECmate

DECUS
DECwriter
DIBOL
MASSBUS

RSTS
RSX
UNIBUS

DECset

PDP

DECsystem-10

P/OS

VMS
VT

Professional

Work Processor

DECSYSTEM-20

Rainbow

VAX

CONTENTS

Page

PREFACE

W
—
N

RO RO BB

[ (S

e
el
e
e R e
e
e
e
v
[V

Lhbupbibbbbbbbbb
=

CHAPTER 1

CHAPTER 2
2.1

2.2
2.3

24
2.5

2.5.1
2.5.2
253
2.6
2.7

INTRODUCTION

INTRODUCGTION .....c.ceteeeecititeeeeeeeeiitaseeeesasaseasassesssssteeesssnssesessssssssntassssssssssnsas 1-1
e s seasnnns 1-1
DMZ32 GENERAL DESCRIPTION ......ooiiiiiiiieeeeeecteeeecreeeeceeeee
rce 1-3
e
UNIBUS Interface Module (M8398)......cccuriiiieeiieieereietcenccin
1-3
sssonsas
UNIBUS INEEITACE. ... . iiiiiiiieiiiiiieiiieiiieeeeeeereeeeierntererecenteeeeeeeeeessesssssess
1-3
ree
sesssnaneees
s
e
e ceeerecte
Shared RAM INerface .....ccoovvvevieeiiieeieieecccereeeesete
T1 INLerface Unit.....coooiiviiiiieiiiiiiiiiieeieeeeeeeereeerreeererrrer
e ee e e eees e sessresssssssns 1-3

Remote Distribution Panel (H3014).....oo oot 1-4
ettt e 1-4
POWET SUPPLY ...eeeierieeieeeeetee
s 1-4
Expansion Module...........ccccccoiiiiiiiiiiiiire
1-5
eeesaeesesesenesnnnns
ProcesSSOT MOAUIE.......oeunnneeeiecirececeeereeeeeeeeeseeeeeeers
1-6
ce
sssensassneens
s
rteesecsneeseeseneceese
DMZ32 SYSTEM OPERATION .....ootttieiieeeeeeeec
1-6
ssssnnssteseesssossssans
T1 OVERVIEW. ... oeeeeeieeieeeeeteeessesssseesessssarsseaasasasssssssaesssassesse
1-6
ssssnsnnsrns
eeaeeeesseensneeeesesassssnesess
DMZ32 SPECIFICATIONS ....oooeeiieieeeeeeeeteeeeeeesee
1-6
e
bn
e
e
snneseasr
ieeereee
s
essvcnt
ettt
ueiieeieeiee
DMZ32 Module (M8398).....
1-7
s
eerane
s
e
et
neciniesice
oiiiiiecieeeeeettce
Distribution Panel (H3014).........ooo
INSTALLATION

INTRODUCGCTION .....coceeeeeeeeceeiteeeeesisereessesssasssasesesesssssesesssssssasesonsnssesecssssssssssanas 2-1
ssssassnes 2-1
UNPACKING AND INSPECTION.......oottieieiitieetreeeiereeseeeeeseesssneess
s 2-2
reenneeeenteseeceeescsvsssssanese
...ttt
DEVICE ADDRESS ASSIGNMENTS
2-2
ssansassseses
e
ereeeeemeeeessenessess
......oooiioeeieeeeerci
ASSIGNMENT
DEVICE VECTOR
2-2
s
saaasnsee
s
seeeneec
e
iieeeeeeert
........ooo
INSTALLATION PROCEDURE
2-2
eaeas
s
e
crer
eeereereereec
et
.ccoeeeveieeeieciree
M8398 Module INStallation........
H3014 Distribution Panel Installation ..........cccooooieeiiereiiiemniiieiniinicinenneee 2-4
Cable INStAllatiON.........cccuveviieeeiiieieieeeeieicrearrrreereeteeeeeesaesennrereeeseeseseessssassssnses 2-13
e 2-15
DMZ32 INSTALLATION CHECKOUT .......ooooiirrreeeeetncrireceecseesaesnaae
2-23
e
ceerenciincereie
et
.....oooo
CHECKLIST
DMZ32 INSTALLATION
PROGRAMMING

INTRODUCGTION... ooetetteeieceeeeeseessesseeesisnrsraassesasessssaaeesasntesesssssssssstessssssssssnas 3-1
OV VICW ..o et eeeeeeeeeeeeeetaeee et e aeaaaresssesaressasssssssnssnnsnsssssnnssareatensnsenssasssssssssonses 3-1
s e st nne 3-2
s
.....eenvienieeeie ittt
DeEVICE REGISIETS
Octet Control and Status Register (OCTET.CSR).......ccccecvviiiiiininnniienens 3-2
Octet Line Parameter Register (LINE.PAR.REG)........cccooccevinnuiinininnnnnnnnnen. 3-2
Octet Receive Buffer (RX.BUF)/OCTET Receive

Silo Parameter (RSP.REG) .....ccvviiiiiieiittceeeeeee ettt s s 3-2
Octet Indirect Register (IND.REG).....cccccoooiiiiiniiniiniiiieirrneiecncnene 3-2
INITIAL OPERATION ....cooioteteiiirectieeeeeeeriereeeseessssssnnseesssasseessssssnssenessesssnssasssnnns 3-3
s snessne e s s ssaasssasans 3-3
PARAMETER INITIALIZATION.......ootiiiieieeeeeccireeeeeeiceie
TRANSMIT OPERATION .....oouttiiiiecirieeeecceveneeeeeeesmreeeeesesietesesasssssnnesessesssnssnns 3-4
iil

CONTENTS (Cont)

Page

RECEIVER OPERATION ..ot
e
o 3-4
DEVICE REGISTERS AND VECTOR ASSIGNMENTS ......coooeoieeeeeeeennn, 3-4

CONFIGURATION CONTROL AND STATUS REGISTER
(CONEFIG.CSR)...coteiitete
ettt
ettt e et e et e et eee e e e e e e oo 3-6
DIAGNOSTIC CONTROL AND STATUS REGISTER (DIAG.CSR)................ 3-9
Diagnostic Control and Status Register (DIAG.CSR<15:0>) — Write............. 3-9
Diagnostic Control and Status Register (DIAG.CSR<15:0>) — Read........... 3-10
OCTET CONTROL AND STATUS REGISTER (OCTET.CSR) READ/WRITE ......co i
e e e, 3-11
LINE PARAMETER REGISTER (LINE.PAR.REG<15:0>) READ/WRITE......ccooiiieee ettt et et e e s e e o 3-13
RECEIVE BUFFER REGISTER (RX.BUF<15:0>) READ ONLY ................... 3-15
RECEIVE SILO PARAMETER REGISTER (RSP.REG<15:0>) WRITE ONLY ..ot
ettt e ee e e e s e e e e e e, 3-17
INDIRECT REGISTERS.........ooeeeeee
e, 3-18
INDIRECT REGISTER (IND.REG[0]<15:0>) - WRITE ONLY .....coocovvvennn..n. 3-18
INDIRECT REGISTER (IND.REG[0]<15:0>) - READ ONLY ......coveevvvrenn. 3-19
INDIRECT REGISTER (IND.REGJ1]<15:0>) - READ/WRITE...................... 3-21
INDIRECT REGISTER (IND.REG[2]<15:0>) - READ/WRITE...................... 3-24
INDIRECT REGISTER (IND.REG[3]<15:0>) - READ/WRITE.........c........... 3-25

CHAPTER 4

SERVICE

4.1

INTRODUCGTION ..ottt
et e s e sereaa e 4-1
DMZ32 FIELD REPLACEABLE UNITS.........cooeiiiieeeeeeeee e 4-1
PREVENTIVE MAINTENANCE .......oooieeeeeeeeeeeeeee
e
s 4-1

4.2
4.3

4.4
4.5

SELF-TEST DIAGNOSTIC ..ottt
aeee e e e ea s 4-5
DIAGINOSTICS ...ttt
ettt et eee e et e e e eeeeneas 4-16

4.6

DIAGNOSTIC SUPERVISOR ..ottt 4-16

4.7

DMZ32 CSR ADDRESS AND VECTOR ADDRESS.........ccccoooivteeeeeeeennn. 4-16
MANUALLY CONTROLLED (HARDWARE) LOOPBACK METHODS....... 4-16

4.8
4.8.1

4.8.2
4.8.3
4.8.4
4.8.5
4.9
4.9.1

4.9.2

4.9.3
4.9.4
4.10
4.10.1

4.10.2
4.10.3

4.10.4
4.10.5

Local T1 Loopback (H3028) ......eeieiiieeieeeeeeeeeeee
e ee
e 4-17

Remote T1 Loopback (H3027).....cooomiieeeieeeeeeeeeeeeeeeee
e eeeeeeeeeeeeee e e eeeeanns 4-18
Single Line EIA Loopback (H3248)........c.oooveiiiiieieieieeeeeeeeeeeeeee
e, 4-19

Staggered Multiline Loopback (29-24929-00) .........c.coveoueemoeeeeeeeeeeeeeeeeeeennn. 4-20
Manual Analog Modem LoopbacK ........c..ccovveeiiieiiiiiieiciceeeeeeeeee
e 4-21
SOFTWARE LOOPBACK METHODS..........c.oooiiioeiieeeceeeeeeeeeeee e 4-22
Shared RAM Loopback..........oceeeiiiiiiiiiiiie
et 4-22
Local Trunk Loopback.........c.cocuiiuiieiiieeieeiieecececeeeeeeeeee
e
4-23
Internal Single-line or All Lines Loopback.............cccoooveeviviiceieniiiieee
. 4-24
Programmable Local Modem Loopback .............cccoeeveeviicvieiiiiiiiieeceenee. 4-25
DMZ32 LEVEL 3 (EVDAE) DIAGNOSTIC........cooviieiiieeeeee
e 4-26
EVDAE Hardware PrerequiSites ...........ccoooveeeeuieeniiiiiceie et 4-26
EVDAE Software Diagnostic Requirements ...............cccooeceevveeeveeeneeeree
e, 4-26
EVDAE DiagnostiC DeSCIIPtiON.........ccouuiievueieieiiiiieeciee ettt eaeeens 4-26
Loading, Attaching, and Running EVDAE.............c..cccoovviviiiiiiiieeeeeenn. 4-29
EVDAE Event Flags.......cocooooiiiiieeeeeee
e
4-31

CONTENTS (Cont)

B~
N
W

TR R R

et et ot e

ket

et e

AR ARBAERDRADDADAS

Page

e 4-31
DMZ32 LEVEL 2R (EVDAF) DIAGNOSTIC........ccoooiiiiiiiiiiiiiieeee
4-31
eeeiiinnesese
vuiiieiiiiiiiiiiiiniiinie
PrerequiSites......c.ccoe
Hardware
EVDAF
4-31
iiinieiennninnnen.
............ccccovviiiemiii
Requir€ments
Diagnostic
Software
EVDAF
e 4-32
EVDAF Diagnostic DesCription.........cccccoveereiiviiiiiiiiieiinineniiensneseie
4-32
.
..
EVDAF
Running
and
Attaching,
Loading,
4-35
ttt
..o
INDICATORS.
PANEL
FRONT
H3014
et s 4-35
ettt eeeeee
Power Indicator (PWR) .....ooviiiiiiiieiee
et 4-35
Sync Indicator (SYNC) ....c.coviiiiiiiiiiiiie
e 4-35
Trunk Quality Indicator (TRNK QLTY) cc.oooiiiiiiiiiii
H3014 REMOVAL/REPLACEMENT PROCEDURES..........cccooiiiiin 4-36
H3014 Power Supply Assembly Removal/Replacement (29-24799-00)........ 4-37
H3014 Fan Assembly Removal/Replacement (29-24800-00).............coc.o.e.. 4-39
H3014 Expansion Module Removal/Replacement (29-24798-00) ................. 4-41
H3014 Processor Module Removal/Replacement (29-24797-00) .................. 4-42
H3014 Chassis/Backplane Replacement ...........cccovuiiiiimiiniiiiniiiineiciiieee 4-45

APPENDIX A

FLOATING DEVICE ADDRESSES AND VECTORS

FLOATING DEVICE ADDRESSES ........ottt A-1
FLOATING VECTOR ADDRESSES ...ttt A-3

APPENDIX B

T1 CABLE SPECIFICATIONS

B.1

B.2
B.3

esaeassaasessssae e s srnaneesbaanns B-1
e e ete et e st e e s sete e e s tt
.t
eeeee et
INTRODUCGCTION ..
s sasaeesseannee s sbeannnas B-1
ttt
e et e eeieeeceiee
CABLE CONFIGURATION ...
T1 CONDUCTOR CHARACTERISTICS ...t B-4

FIGURES
Title

Page

DMZ32 Component Parts.........ccccceeeveeuieeeieeieeieceeceiceeetee
e sveestee st eeeseseee e e nee s 1-2

£ N

tor

W N-=O

&Ahkhhhwwyuuuwuuwwuuu
PERPRERRPRPRRRL
OooUrhbhDL~
AN
DN et ot ok et ek et et \D OO0~

DMZ32 Functional Block DIagram ............cc.oooeeoiiiiiiiiiiiieeeieieeeeeeeeeeeeeeveeesssesanans 1-3

4-10
4-11

4-12
4-13
4-14
4-15
4-16

DMZ32 UNIBUS Interface Module (M8398) .......uoeiemeieeeeieeeeeeeeeeeeeeeeeeeseeeeeerseennes 2-3
Typical H9642-FC/FD Shielded Cabinet Before H3014 Installation....................... 2-5
Typical H9642-FC/FD FCC Shielded Cabinet After H3014 Installation................ 2-7
H3014 Shipping Bracket POSItion ..............ccccoevveiiviiiiiiiiiieieeeeeeeeeeeeeeee
e senee
eeee
s 2-8
Typical H9652-MF (VAX-11/780) FCC Shielded Cabinet Before
H3014 InStallation ..........ccceeeiiieeiiiieceeeeeeeeeeee
e et
s e ane 2-10
Typical H9652-MF (VAX-11/780) FCC Shielded Cabinet After
H3014 Installation......................ettt
et et e e e st e e e e e e s nnae s e aeennaesrnnns 2-11
H3014 Shipping Bracket POSItION ...........cc.coouiviiiiiieiieicneeeeeceeeeeeeeeeeesveeeeseeeeens 2-12
BC22N-10 to BC18L-15 CONNECLION.........ccvievrieeeeeeieieieeeeeeceeeeeeeteeeeeseeseeeeresaeen 2-14
H3028 Loopback Connector Installed on M8398............c..coouvmiveiireieeeeeeeeeeenenn, 2-15
BC22N-10 Cable Between M8398 and I/O Bulkhead...........coccoevvvveveeveeeeeeennnnn. 2-16
H3027 Loopback Connector Installed on I/O Bulkhead..............c.ccceeueeueeenennn.... 2-17
H3027 Loopback Connected to Remote End of T1 Cable........ccoceveeeeevevneannenn. 2-18
T1 Connector Between I/O and H3014 ..........c.ooomiioiiieieeeeeeeeeeeeeeeee
e eeeee e 2-19
29-24929-00 Installed on H3014 Distribution Panel............c.ocooeeeviroveeeieeeennnnn. 2-20
DMZ32 Installation OVEIVIEW .........cc.cccueeiieieeeeereiieceieceeeceeceeeereeaeeseee
e seeesaeseeaan 2-22
DMZ32 Word Allocation of Device Control/Status Registers..............ccceeveeneenn.... 3-5
DMZ32 Register Bit Map OVETVIEW..........couvieeiiieeiiiieieieeeeereeeeeeeeeeeeeeeseeeeeessseens 3-6
Configuration Control and Status Register (CONFIG.CSR) Bit Map...................... 3-7
Diagnostic Control and Status Register DIAG.CSR <15:0> Bit Map - Write........ 3-9
Diagnostic Control and Status Register DIAG.CSR <15:0> Bit Map - Read...... 3-10
Octet Control and Status Register (OCTET.CSR) Bit Map.......cccccoevveveeveveeenne. 3-11
Line Parameter Register (LINE.PAR.REG. <15:0>) .....cccceeeveiveimeeeeceeeeeereennnn. 3-13
Receive Buffer Register (RX.BUF) Bit Map — Read Only ..........cccovveuemenennne... 3-15
Receive Silo Parameter Register (RSP.REG) Bit Map - Write Only.................... 3-17
Indirect Register (IND.REG [0] <15:0>) Bit Map — Write Only .............c........... 3-18
Indirect Register IND.REG [0] <15:0>) Bit Map —Read Only ............................ 3-19
Indirect Register (IND.REG [1] <15:0>) Bit Map — Read/Write.........cccou.e....... 3-21
Indirect Register (IND.REG [2] <15:0>) Bit Map - Read/Write......................... 3-24
Indirect Register (IND.REG [3] <15:0>) Bit Map - Read/Write......................... 3-25
Processor Module Test POINES ..........c.ccoueiiieiiereceiceceeeeeee
et
e 4-2
Expansion Module Test POINLS.........c..cccoeuriieoiinieieceeceeeceeeeeeeeestee
eeeeeeeeeeaes 4-3
Power Supply Assembly Test POINtS.........ccceeveeeieeiecieiieeieeceece et 4-4
MB398 LEDS ..ottt
ettt et aecere ettt et s e st st et e nesseeees 4-5
H3028 Loopback CONNECLOT .........cceeeuvieeieeetieeeeeceeeceeeeeee
et e
eeseeeeaeesaaas 4-17
H3027 Loopback CONNECLOT .......cccuveuvieieiiieeceeeeeeeeeeneece
et tee e eeeeses aeneees 4-18
H3248 Turnaround CONNECLOT ............ccuvieeiivrieeeeeiee
e
eeeeeeeetse
res e eese s 4-19
29-24929-00 Staggered Loopback COonnector..........coocvveveeeeeeeeeeeeseeeeeeeereereeereeeareens 4-20
Manual Analog Modem Loopback.............ooieeeieveiniiiiiiiiiie
et ee e eeeeeeesnens 4-21
Shared RAM Loopback Test..........ieeceeuiieiiieeieeceeeeeeeeeeeeee
eeeeeeeeeesevesaeseens 4-22
Local Trunk Loopback TeSt.......c.cceeueieuieieeiieierieeeeeece
ettt e seeeeeeeaeeseens 4-23
Single Line Loopback TeSt......ccoueeiuiiuviiiiieeeeeeeeee
et
eee et e e eee e e ae 4-24
Analog Modem Loopback Test.........cccecveiuerieieeeneiieeeeeeee
et
neneas 4-25
Loading, Attaching, and Running EVDAE ..............ccoccuoomiieieeeeeeeeeeeeeveee
e 4-29
Loading, Attaching, and Running EVDAF ...........cccooovviiiiiiiiiiieeeeeeeeeeereeeeenen 4-33
H3014 LED INICAtOrS ....c...oocveeeuiiiieeieiieceeceeeeeece
et satesateeeesses st e ee e e e 4-35

FIGURES (Cont)
Figure No.

4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
A-1

Title

Page

1/4 Turn Lock Fasteners ..........ccccoeeveeveerieeneeeceneceiiininiiiiesiesnseseessnessesssesssanns 4-37
H3014 Power Supply LOCAtion .........ccoeeerieeieeinieirniiiiniiiirciieciecesinesessseesseeseseeas 4-38
e ente e 4-39
H3014 Fan Assembly LOCAtion..........ccceeevuereeiceniieiiiiiiiiiiiieceiterccicesine
e 4-40
Fan Mounting Bracket ASSembly........cc.cocevvuiniiviiniiiiiniiieereeeee
H3014 Expansion Module Location.........c..cccouviuiiniiiiinniiniiceecrenee
e 4-4]
Processor Module Clock Jumper and Dip SwitCh ..........cccoovvviiirinniinnniinnniinnnnee. 4-43
Processor Module Master/Slave JUMPET .........coocveiiieriicerriccnniicinieccneciceieeeeens 4-44
Processor/Expansion Module Input Power ............ccccoovvniiiniinniinnniiniinienernnen, 4-45
Chassis/Backplane Securing Screws Location .........ccccooeenienieniininninneninccaneen. 4-46
UNIBUS Address Map .......oooeceieeiiiiriireietieesierreeesistsssesteesssessssasessssssssssessssssssssnss A-1

TABLES
Table No.
1-1
2-1
3-1
3-2
3-3
34
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
4-1
4-2
4-3
4-4
A-1
A-2
B-1
B-2
B-3

Title

Page

V.24 /RS-232 Pin ASSIZNMENLS ......ccocoeiieriireeiireeecneeeeeerntessssesteesiesssessssesernsesssasenss 1-5
iceete 2-1
et
DMZ32 Option Packing List .......cc.ccoceviiviiiiiinniiiiicciect
Configuration Control and Status Register Functions..........ccccocoeeieiiniiniicninnnnnne. 3-8
Diagnostic Control and Status Register DIAG.CSR <15:0> — Write...................... 39
Diagnostic Control and Status Register DIAG.CSR <15:0>.......ccccoocieiiiininnnnnn. 3-10
Octet Control and Status Register FUnctions ..........ccccccoveeriiciiiiiiiiiniiinnninniiniennenn, 3-11
Line Parameter Register FUnCtions...........cccooeceiiiiinniiinniiinniniieecie
e 3-13
Receive Buffer Register FUNCLIONS.........cocceeeeireiienceiiiiiiriiiinciecnecciccree
e 3-16
Receive Silo Parameter Register Functions..........c.ccccovvvviiiiniiiiiiiniiiinnenncniineenn. 3-17
Indirect Register 0 FUNCLIONS ........ccceeiverreenreccnienititiciniceiiee
et
een 3-18
Indirect Register 0 Functions — Read Only........cccccovviiniiniiinniiniiiiiicieenee, 3-20
Indirect Register 1 Functions — Read/Write......cc.ccocoviiniinuininininiiniinieicecinnnen, 3-21
Indirect Register 2 Functions — Read/WTite........cccoooveiiiiiininniiniciiieieeeeeeen, 3-24
Indirect Register 3 Functions — Read/Write.........cccovvvinvrninieiiininniiiieiecieenee .. 3-25
M8398 Coded LED Display........ccccoveeririiiieiiniieniiciiiiineeciintie
e nrineeesereesessneesaeeas 4-6
EVDAE DiagnostiC SUMMATY ........cccceeceireruiiiinieiieciiiiieneisiesieesessesseessasesnenns 4-26
EVDAF DiagnostiC SUMMATY .......ccccceevieivirierniiiisiieniieiniirinneestesentsesssssssesessssssasees 4-32
H3014 Front Panel INndiCators..........ccceeeeeereioenneniniiineitrcinntennenesecesnneessssn
e esannes 4-36
Floating CSR Address ASSIZNIMENLS .........c.cccueerereerennesreeseesssenesseeessesemsasessaessssensses A-2
Floating Interrupt Vector Device ASSIZNMENt .........coovveiviiiiiiiiniiiiniiinienieeeeneeeieeens A-3
BC18L-xx Component PArts .........ccccceeveirieeiiiciiniiiniitiiiecrieree
sttt seree e B-1
DIGITAL Cable Option Designations............ccccceeeviririeininiiiiinneeeeneninrinneesuessiensens B-3
T1 Cable SChemMALIC ......ceveueeeeiiecteeece ettt e sa e e e saes B-5

vii

PREFACE

The DMZ32 User Guide is a standalone document that describes typical 24-line asynchronous multiplexer
use, features and capabilities, installation, programming, service, and troubleshooting procedures, based on
a module replacement philosophy. T-carrier techniques are covered in Appendix A, while floating device
addresses and vectors are covered in Appendix B.
Additional information about the DMZ32 24-line asynchronous multiplexer can be found in the following:
®

DMZ32 Technical Manual (EK-DMZ32-TM),

Communications Options Minireference Manual (EK-CMIVI-RM), and

DMZ32 Print Set (MP00997-01).

The postage-paid Reader’s Comments form at the end of this document requests your critical evaluation to
assist us in preparing future documentation.

viil

CHAPTER 1
INTRODUCTION

1.1

INTRODUCTION

This chapter contains a brief introduction to the DMZ32. The term DMZ32, as used throughout this
manual, denotes the 24-line asynchronous multiplexer.
1.2

DMZ32 GENERAL DESCRIPTION

The DMZ32 is a 24-line asynchronous multiplexer consisting of a single hex height module and a
distribution panel. The DMZ32 has a maximum line speed of 19.2K bits/s.
Features of the DMZ32 include:

Split baud rate and modem control on all lines,

Transmit and receive character silos,

DMA capability on transmit,

Programmable silo alarm time-out period for the receive silo, and

Improved connectivity.

These features result in increased system throughput. An added feature is the improved connectivity of the
DMZ32. The connection between the VAX UNIBUS interface module (M8398) and the remote distribution panel (H3014) is accomplished by two cables (BC22N-10 and BC18L-15).
The remote distribution panel (H3014) of the DMZ32 can be mounted up to 1524 m (5000 ft) away from
the UNIBUS interface module (M8398) with additional cable. (See Appendix B.) The H3014 is an active
distribution panel that requires external power. Located on the distribution panel are 24 RS-232-C male
DB25 connectors which allow connection to 24 different lines.

The DMZ32 plugs into a Small Peripheral Controller (SPC) slot and runs under the VMS operating
system (Version 4.0 or later). (Refer to Figure 1-1 for the component parts of the DMZ32 and Figure 1-2
for the DMZ32 functional block diagram.)

1-1

nfl!

rn__n__n

(M8398)

| B
[{

[ o]

(BC22N-10)

(BC18L-15)

TRNK

PWR

SYNC

OQLTY

LINEO

LNE4

IS ;

LINEO

LINE

OCTET 2

(H3014)

H3028

MKV84-0470

Figure 1-1

DMZ32 Component Parts

1-2

POWER

SUPPLY

INTERFACE | INTERFACE

SHARED

<
<

INTEREACE

CONTROL

:vigt;

RAM

MODEM

UNIBUS

—

0 rereace

= 2

[]

LINK

EIA

LINES

21
22

ASYNC

RECEIVERS

DEMUX

EIA

DRIVERS/

M8398

CABLE

H3014
MKV84-0471

Figure 1-2

1.2.1

DMZ32 Functional Block Diagram

UNIBUS Interface Module (M8398)

The first interface component of the DMZ32 asynchronous multiplexer is the UNIBUS Interface Module
(UIM). The UIM is mounted on a single hex height board and is divided into the following logical sections:
e
e
e

UNIBUS Interface (UBI),
Shared RAM Interface (SR), and
TI1 Interface Unit (TIU).

1.2.1.1 UNIBUS Interface — The UNIBUS Interface (UBI) is the section of logic that handles all
UNIBUS interfacing. This section passes data between the VAX UNIBUS and the shared Random
Access Memory (RAM) interface.

1.2.1.2 Shared RAM Interface — The Shared RAM interface (SR) is an area of shared access, a means
of passing data from one asynchronous process to another. The Shared RAM interface allows access to the
T1 interface unit from the UNIBUS Interface and to the UNIBUS interface from the T1 interface.

1.2.1.3 T1 Interface Unit — The T1 Interface Unit (TIU) is the time division multiplexer and the T1
carrier interface. It controls all data going on and off the high speed (1.544M bits/s) T1 trunk.

1-3

1.2.2 Remote Distribution Panel (H3014)
The second component of the DMZ32 asynchronous multiplexer is the remote distribution panel (H3014).
The H3014 is an active distribution panel that is powered from its own independent power supply. The
H3014 is responsible for coordinating all data transfers between any of 24 asynchronous lines and the T1

trunk. The configuration of the H3014 depends on the option purchased; therefore, it may also be
responsible for passing modem signals if the appropriate option is installed. The distribution panel decodes

the incoming T1 formatted serial data. In the reverse direction, it places outgoing asynchronous terminal
data and modem control signals into the T1 serial bit stream, using bipolar encoding techniques.
The H3014 consists of the following major components:
e

Power supply,

Expansion module , and

Processor module.

1.2.2.1
Power Supply - The power supply provides the operating voltages necessary for the electronic
circuitry in the distribution panel. The voltages provided by the power supply are:

®
e
e

+5Vdc@ 10 A,
+12Vdc@ 2.5 A, and
—12Vdc@ 2.5 A.

1.2.2.2 Expansion Module - The expansion module provides drivers/receivers for six of the modem
control signals. The modem control signals supported by the expansion module are:
Data Signaling Rate Select,
Request To Send,
Data Set Ready,

Clear To Send,
RS-449 Local Loopback, and

RS-449 Test Mode.

(Refer to Table 1-1 for pin assignment and signal descriptions.)

1-4

Table 1-1

V.24/RS-232 Pin Assignments

Description

CCITT

EIA

Origin

Protective Ground
Transmitted Data
Received Data
Request To Send (RTS)
Clear to Send(CTS)
Data Set Ready (DSR)
Signal Ground
Carrier Detect (CD)
RS-449 Local Loopback (LL)
Data Terminal Ready (DTR)
Ring Indicator (RI)
Data Signaling Rate
Selector (DSRS)
RS-449 Test Mode (TM)

1
2
3
4
5
6
7
8
18
20
22
23
25

101
103
104
105
106
107
102
109
108.2
125
111
-

AA
BA
BB
CA
CB
CC
AB
CF
CD
CE
CH
-

DTE
DCE
DTE
DCE
DCE
DCE
DTE
DTE
DCE
DTE
DCE

1.2.2.3

Processor Module — The processor module contains the microprocessor that controls the H3014

operation, status indicators (Pwr, Sync, and Trnk QIlty), drivers/receivers for data signals, and modem
control signals. The modem control drivers/receivers contained on the processor module are:
e
e
e

Data Terminal Ready,
Carrier Detect, and
Ring Indicator.

1-5

1.3 DMZ32 SYSTEM OPERATION
The DMZ32 can transmit data to and receive data from 24 different lines. During the transmission of

data, the transmit line is enabled by setting the line enable bit in the specific line control (LINE CTRL)
register. A line must be enabled before transmission of data can take place. A disabled line is held in the
ON (or marking) state, except in special maintenance situations. Transmission of data is handled using two
different techniques, Program Mode and DMA Mode. Although both of these techniques use silos, the
program mode uses standard I/O and the DMA mode uses NPR/DMA to load the transmit silos.
For reception of data, the receiver is enabled by setting the line enable bit in the appropriate LINE CTRL
register. A line must be enabled in order to receive data. Each octet (8-line group) shares a 128-character
receive silo (total of three receive silos). There is no NPR/DMA mode in the receiving mode of the
DMZ32.

1.4 T1 OVERVIEW
The DMZ32 uses a T1 transmission technique by way of two twisted pair cables to provide optimal
channel utilization for transfer of data between the UIM and the distribution panel.
T1 or “T-Carrier” is a telecommunication industry term taken from the Bell System’s carrier system. This
transmission techique is based on Pulse Coded Modulation (PCM) and Time Division Multiplexing (TDM)

techniques. Using these techniques, 24 independent data channels are encoded into 8 bits and are
subsequently placed into a 1.544M bits/s serial bit stream. This bit stream is then converted into a specific
format using a bipolar or Alternate Mark Inversion (AMI) technique, and is transmitted down the T1 link.
At the receive end of the T1 link, the clock is reconstructed from this serial bit stream and is used to

synchronize the demultiplexing and distribution of the data to the appropriate line.
1.5 DMZ32 SPECIFICATIONS
The specifications for the two major components of the DMZ32 (M8398 module and H3014 distribution

panel) are divided into the following:
Physical specifications,
Electrical specifications,
Environmental specifications, and
UNIBUS conductor specifications (M8398 only).
1.5.1

DMZ32 Module (M8398)

Physical Specifications

Single hex height module
Electrical Specifications
DC Voltage

+5V@90A
+15V@0.1 A

Data Baud Rates
(Half or Full Duplex)

50, 75, 110, 134.5, 150, 300, 600,
1200, 1800, 2000, 2400, 4800, 9600, and 19200

1-6

Environmental Specifications
Temperatures

Operating

10 to 40°C (50 to 104°F)

Non-operating

—40 to 66°C (—40 to 151°F)

Relative Humidity

Operating

10 to 90% with a maximum wet bulb of 28°C (82°F)
Maximum dewpoint of 2°C (36°F), noncondensing

Non-operating

5 to 95% noncondensing

UNIBUS Specifications
UNIBUS Loads

6.2 ac unit loads

1.5 dc unit loads

1.5.2

Addresses (Octal)

760440 — 763740 (typical)

Vector (Octal)

300 (typical)

Interrupt Levels

BR
5

Distribution Panel (H3014)

Physical Specifications

Height

13.3 cm (5.25 in)

Width

48.2 cm (19 in)

Depth

43.18 cm (17 in)

Mounting

Standard 48.2 cm (19 in)

Weight

8.1 kg (18 lbs) maximum

Electrical Specifications

AC Line Voltage

90-130 Vac or 180-255 Vac

Line Frequency

47-63 Hz

Input Current

1.5 A @ 120 Vac
.8 A @ 220-240 Vac

Grounding

Frame Ground

The chassis frame is electrically bonded to earth ground
by means of the primary circuit connector

Logic Ground

This is signal reference ground

EIA Ground

This is a noncurrent carrying ground used as a reference
for all Electronic Industries Association (EIA) receiver
inputs

Environmental Specifications
Temperatures

Class B

10 to 40°C (50 to 104°F)

(Non air-conditioned)
Relative Humidity
Class B
(Non air-conditioned)

Heat Dissipation

10 to 90% with a maximum wet bulb of
28°C (82°F)

Maximum dewpoint of 2°C (36°F), noncondensing
454 Btu per hour

1-8

CHAPTER 2
INSTALLATION

2.1

INTRODUCTION

This chapter contains procedures for unpacking, installing, and checking the DMZ32. A checklist, which
can be used to verify the installation process, is included.
2.2

UNPACKING AND INSPECTION

The DMZ32 is packaged according to commercial packing practices. When unpacking a DMZ32 option,
carefully remove all packing materials making sure not to damage the contents, and check the contents
against the shipping list. Table 2-1 lists the contents of each DMZ32 option. Inspect all items carefully.
Pay close attention to the module to check for cracks, loose components, and breaks in the etched paths.
Table 2-1

DMZ32 Option Packing List
Contents

Option

Part Number

DMZ32-M

M8398
BC22N-10

One UNIBUS hex module
One internal cable and 2 X 4 bulkhead insert

BC18L-15

H3028
H3027
EK-DMZ32-UG

One external cable
One local T1 loopback
One remote T1 loopback
One user guide

CK-DMZ32-AY

H3014-CA

Remote distribution panel (120 V /240 V) with

CK-DMZ32-DY

H3014-AA

DMZ32-AP

DMZ32-DP

DMZ32-N

modem control
Shipping bracket
120 V power cord
240 V power cord

Remote distribution panel (120 V/240 V) no

modem control
Shipping bracket
Picture frame
120 V power cord
240 V power cord

DMZ32-M (system integrated)
CK-DMZ32-AY

DMZ32-M (system integrated)

CK-DMZ32-DY

Remote distribution panel (H3014) expansion
module for modem control

2.3 DEVICE ADDRESS ASSIGNMENTS
The DMZ32’s device addresses are selected from the floating device address space of the UNIBUS
input/output (I/O) page. (Refer to Appendix A.) Switchpack E-53 on the DMZ32 selects the
first
DMZ32 CSR address.

When there are no floating devices before the DMZ32, the first floating address space is 760440 (FFE120
hex). The second and third floating address spaces for the DMZ32 are 760500 (FFE140 hex) and
760540
(FFE160 hex), respectively. When operating under VMS (Version 4.0 or later), the actual address(es)
can
be determined by using the SYSGEN utility. Refer to the VAX/VMS Guide to Writing a Device
Driver
(AA-H499B-TE) for the procedure to determine CSR address assignments.
2.4 DEVICE VECTOR ASSIGNMENT
The DMZ32 interrupt vectors are controlled by the VMS operating system. During autoconfiguration,

the
operating system loads the value of the base vector into the DMZ32. The other DMZ32 vectors
are
calculated from the base vector. (Refer to Appendix A for floating vector addresses.)

2.5 INSTALLATION PROCEDURE
The installation of the DMZ32 is broken down into the following procedures:
e
®

UNIBUS interface module (M8398) installation,
Remote distribution panel (H3014) installation, and
(Cable installation.

The required installation tools are:
VAX cabinet key (usually a 7/64 Allen wrench),

Phillips screwdriver,
7/16 hex driver, and
Flatblade screwdriver.

2.5.1
MB8398 Module Installation
To install the M8398, perform the following steps in the sequence given, ensuring that no steps are
or overlooked. Figure 2-1 shows the location of the switchpacks.

skipped

Set switches 2 through 9 on switchpack E-63 to the correct priority level.

Set switches 1 through 8 on switchpack E-53 to the proper UNIBUS address.

Set switch 9 on switchpack E-53 to the ON position.

Set switch 10 on switchpack E-53 to the ON positon. (Refer to Figure 2-1 for switch settings.)

Power down the system in which the M8398 is being installed.

WARNING
Before performing this procedure, the system on
which the DMZ32 is to be installed must be com-

pletely powered down and the power cord disconnected from the power source. Personal injury may

result if this procedure is ignored.

SWITCH SETTINGS OFF TO REDUCE POWER CONSUMPTION
(THIS SWITCHPACK IS NOT USED IN DMZ32 APPLICATION.}
.

mmOo

—

SWITCHPACK EiOT"

aafs]sfs

M8398 LED'S

SELF-TEST

(SEE SECTION 4.4)

PUSHBUTTON
L

]

W1 — IN (ENABLES

]

MSB LSB

]

{UNIBUS INT.}

W2 - OUT (NO
FUNCTIONALITY)

]

SWITCHPACK E53

SWITCHPACK E63

Zala]tinj0®]sisls

s’

Fle

9 10

910

"l
alalalulalt

[¢]

NOT

|'— SELF TEST
- DMA SELF TEST
ON
FAILS — JUMPS TO

JUNIBUS ADDRESS

USED

SPECIFIC ERROR

DEVICE

PRIORITY | SW#
5
6

2
ON

OFF

3
OFF
ON

a4
OFF
ON

7
[
5
OFF | OFF | ON
ON

8
ON

LOCATION
DO DATA PATH
TESTING (NORMAL

]
ON

OPERATION)

OFF | OFF | OFF

OFF

— DMA SELF TEST
FAIL

SELF TEST LOOPS
SKIP DATA PATH

NOTES

L- SELF TEST

1. FOR SWITCHPACK E53,

TESTING

ON — PERFORM DMA
SELF TEST (NORMAL
OPERATION)

EB3. AND E101, “ON" IS
A LOGIC “0 AND “OFF"
IS A LOGIC 1",

FACTORY SETTING FOR
JUMPERS W1 AND W2 ARE:
W1=IN

OFF — DISABLE DMA
SELF TEST
GO TO DATA TEST

W2=0UT

ADDRESS }_fl]’
RANGE

—

760440
760500
760540
| 76060(
760640
760700
760740
761000

SW#

ON
ON
ON
ON
ON
ON
ON
ON

ON
ON
ON
ON
ON
Of
ON
ON

ON
ON
ON
ON
ON
ON
ON
OFF|

OFF | ON
ON
OFF
OFF | ON
OFF | ON
OFF | ON
OFF | OFF
OFF | OFF | ON
ON
OFF | OFF | ON
OFF
OFF | OFF | OFF | ON
OFF | OFF | OFF | OFF
ON
ON
ON
ON

MKVB4-0309

Figure 2-1

DMZ32 UNIBUS Interface Module (M8398)

Remove the Non-Processor Grant (NPG) wire (CA1-CBl) from the Small Peripheral
Controller (SPC) backplane slot where the M8398 module is to be installed.

Perform resistance checks on the backplane to ensure that no short circuits exist.

Install the M8398 module into the prepared SPC slot of the DD11-DK backplane.

Power up the system and verify that the +5.00 Vdc supplied to the M8398 measures

Vdc.
10.

When the M8398 module installation is complete, proceed to the DMZ32

Off List (Section 2.7) for the remaining steps to be performed.
2.5.2

+5.00

Installation Check-

H3014 Distribution Panel Installation

H9642-FC/FD (UNIBUS Expansion Cabinet)

NOTE
Because of mounting limitations, the distribution
panel can only be mounted in H9642-FC/FD model

cabinets. Refer to Figure 2-2 for the rear view of a
model H9642-FC/FD.

Remove the rear door assembly of the VAX cabinet using the 7/64 Allen wrench.

Remove the FCC shield gasket panel assembly (Figure 2-2) by removing the following:
a.

Two (2) 7/16 hex head screws are located on the top right side and top left side
of the
gasket panel assembly. These secure the FCC shield gasket panel to the vertical mounting

rails of the cabinet.

Nine (9) Phillips screws located under the gasket panel assembly. (These screws secure
the
FCC shield gasket panel to the FCC bulkhead frame).

NOTE
The FCC bulkhead frames must be removed from
below the FCC shield gasket panel assembly down to

the location where the H3014 is to be mounted.
These bulkhead frames must be removed starting
from the top frame to the bottom frame. (See Figure

2-2))

Remove the nine (9) Phillips screws (Figure 2-2) that secure the FCC bulkhead frames.

Remove the six (6) mounting Phillips screws (Figure 2-2) that secure the FCC bulkhead frames
to the vertical mounting rails of the cabinet.

2-4

7/16 HEX HEAD

SCREWS

(2 PLACES)

FCC SHIELD
\

MOUNTING scaewsj

(6 PLACES)

)

GASKET PANEL
ASSEMBLY

\ SMALL PHILIPS
SCREWS

(9 PLACES)

I/O PANEL
(TYPICAL)

FCC BULKHEAD

FRAME

POWER

CONTROLLER

MKV84-0472

Figure 2-2

Typical H9642-FC/FD Shielded Cabinet Before H3014 Installation

Repeat Steps 3 and 4 until all required FCC bulkhead frames are
removed, then proceed to
Step 6.

NOTE
The distribution panel can be mounted to the cabinet

only in the location shown in Figure 2-3.

Position the distribution panel and secure it to the cabinet vertical mounting
rails using the six
(6) Phillips mounting screws (Figure 2-3).
After the distribution panel is mounted, secure the bottom of the distribut
ion panel to the FCC
bulkhead frame beneath it using the nine (9) Phillips screws that were
removed from the FCC
bulkhead frame.

NOTE
If the H3014 is received in a cabinet, remove the

shipping bracket (Figure 2-4).

Install the FCC shield gasket panel assembly by reversing the procedure

in Step 2.

When the distribution panel installation is complete, proceed to the DMZ32
Installation CheckList (Section 2.7) for the remaining steps in the installation of the DMZ32.

2-6

H3014

MOUNTING /

SCREWS
(6 PLACES)

877D

POWER CONTROL

2X4 1/0

PANEL (TYPICAL)

MKV84-0474

Figure 2-3

Typical H9642-FC/FD FCC Shielded Cabinet After
H3014 Installation

H9642-FC/FD CABINET

FRONT

SIDE

H3014 SHIPPING

BRACKET

REMOTE DISTRIBUTION
PANEL (H3014)

‘ FRONT

SIDE

(SIDE VIEW)
MKV84-0473

Figure 2-4 - H3014 Shipping Bracket Position

H9652-MF (UNIBUS Expansion Cabinet)
NOTE

If the H9652-MF cabinet uses two (2) BA11 boxes,
the distribution panel can not be mounted in the
cabinet due to power limitations.

Remove the rear door assembly of the VAX cabinet using the 7/64 Allen wrench.

Remove the FCC shield gasket panel assembly (Figure 2-5) by removing the following parts.
a.

Two (2) 7/16 hex head screws are located on the top right side and top left side of the
gasket panel assembly. These secure the FCC shield gasket panel to the vertical mounting
rails of the cabinet.

Nine (9) Phillips screws are located under the gasket panel assembly. These screws secure

the FCC shield gasket panel to the FCC bulkhead frame.

Remove the nine (9) small Phillips screws (Figure 2-5) that secure the FCC bulkhead frame to
the top of the cabinet frame.

Remove the six (6) mounting Phillips screws (Figure 2-5) that secure the top FCC bulkhead
frame to the cabinet vertical mounting rails.

Repeat Steps 3 and 4 until all required FCC bulkhead frames are removed. When completed,

proceed to Step 6.

NOTE

The distribution panel can be mounted only in the
top two FCC bulkhead frame locations.

Position the distribution panel and secure it to the cabinet vertical mounting rails using the six

(6) Phillips mounting screws (Figure 2-6).

After the distribution panel is mounted, secure the bottom of the distribution panel to the FCC
bulkhead frame beneath it using the nine (9) Phillips screws that were removed in Step 3.
NOTE

If the H3014 is received in a cabinet, remove the
shipping bracket (Figure 2-7).

If you are mounting two distribution panels, repeat Step 7. When completed, proceed to Step 9.
Install the FCC shield gasket panel assembly by reversing the procedure in Step 2.
10.

When the distribution panel installation is complete, proceed to the DMZ32 Installation CheckOff List (Section 2.7) for the remaining steps in the installation of the DMZ32.

PHILLIPS

FCC BULKHEAD
FRAME

(9 PLACES)

MOUNTING /

KRR

%%RLR%%1I0KL0L9L0E%R%0R%
KS

(6 PLACES)

SCREWS

SERIRIKKY

MKVv84-0475

Figure 2-5

Typical H9652-MF (VAX-11/780) FCC Shielded Cabinet Before H3014 Installation

2-10

caa
]

EITY

oo
Gy

&
@D

oo
=D

o
&

\NAS\/‘“A

(6 PLACES)

KERRK
S

SCREWS

SKRRAGIRSKS

MOUNTING

Emn

RSRSIS

CAUTION

IF TWO BA11 BOXES
ARE BEING USED BY THE

VAX-11/780. THE H3014

DISTRIBUTION PANEL(S)

MAY NOT BE MOUNTED
IN THE CABINET BECAUSE
OF POWER LIMITATIONS.

MKV84-0477

Figure 2-6

Typical H9652-MF (VAX-11/780) FCC Shielded Cabinet After H3014 Installation

2-11

H9652-MF CABINET

FRONT

SIDE

H3014 SHIPPING
BRACKETS

|
I

!"l
‘

REMOTE DISTRIBUTION
PANEL(S) (H3014)

/
=

- 1:

| 1

I
I
|

71
|
— 1

(BATIKBOX)

L ___
_1
I
1
-

FRONT

SIDE

L—— POWER CONTROLLER

(SIDE VIEW)

Figure 2-7

H3014 Shipping Bracket Position

2-12

MKV84-0476

Non-FCC Compliant Cabinet
1.

Remove the rear door assembly of the VAX cabinet using the 7/64 Allen wrench.

Position the distribution panel where it is to be mounted, and secure it to the cabinet vertical
mounting rails using the six (6) Phillips mounting screws.

If you are mounting two distribution panels, repeat Step 2 and proceed to Step 4.

When the distribution panel installation is complete, proceed to the DMZ32 Installation CheckOff List (Section 2.7) for the remaining steps in the installation of the DMZ32.

2.5.3

Cable Installation
NOTE

In an FCC cabinet, before the BC22N-10 is connect-

ed, it should be attached to the 2 X 4 I/O panel that
is shipped with the cable. If installing in a non-FCC
cabinet, discard the 2 X 4 1/0 panel. (Refer to Figure 2-8.)

Remove a blank 2 X 4 1/0 panel from the FCC bulkhead frame where the new 2 X 4 1/O panel
(supplied with the cable) is to be located. Remove the two screws that secure the panel to the
FCC bulkhead.

Feed the cable end of the BC22N-10 cable through the opening where the new I/O panel is to
be secured.

Secure the new 2 X 4 1/O panel that is connected to the BC22N-10 cable to the FCC bulkhead
frame where the blank panel was removed.

Connect the 10-pin BergTM connector of the BC22N-10 cable to J1 of the M8398 module,
located in the BA11-K box. Be sure that the “This Side Up” label is visible.

Connect one end of the BC18L-15 cable to the external side of the new I/O panel.

Connect the loose end of the BC18L-15 cable to the T1 connector on the distribution panel.

Berg is a trademark of Berg Electronics, Inc.

2-13

2X4 1/0 PANEL

BC22N-10
:

‘

;

MODULE _ "“MIIII
M8398

[Fhe_

PANEL T1

DISTRIBUTION

INTERNAL TO CABINET <«

BC18L-15

"JI

THREADED SPACERS

’

— EXTERNAL TO CABINET

CONNECTOR

MKV84-0478

Figure 2-8

BC22N-10 to BC18L-15 Connection

2-14

2.6

DMZ32 INSTALLATION CHECKOUT

The following procedure is used to check out the installation of the DMZ32.
1.

Remove the BC22N-10 cable from J1 of the M8398 module.

Install the local T1 loopback (H3028) connector into J1 of the M8398 module (Figure 2-9).
Power up the VAX system and execute diagnostic EVDAE for two passes with event flag 3 set.

(Refer to Chapter 4 for details on how to execute EVDAE).
If a failure occurs, check the following:

Seating of the M8398 module in the DD11-DK backplane,

ROM seating on the M8398 module, and

Seating of the H3028 loopback connector in J1.

IF THE FAULT IS NOT CORRECTED, REFER TO CHAPTER 4 FOR CORRECTIVE
ACTION.

H3028 @
N

m8398

————————

)

A
4

MKV84-0479

Figure 2-9

H3028 Loopback Connector Installed on M8398

2-15

After two successful passes, remove the H3028 loopback connecto
r from the M8398 module
and connect the BC22N-10 cable between M8398 module J1 and the
2 X 4 I/O panel insert.
(Refer to Figure 2-10.)

P
e

BA11-K — ]

BOX

_—~

BC22N-10

—

FRONT

g:BI .
NET

I/O BULKHEAD

| [ L7 PaneL
/

"'y

MKV84-0480

Figure 2-10

BC22N-10 Cable Between M8398 and I/O Bulkhead

2-16

Install the H3027 loopback connector (Figure 2-11) to the 1/O panel side of the I/0 panel
connector (outside the cabinet), and execute diagnostic EVDAE, setting event flag 3 for two
passes without errors.

If a failure occurs, check the T1 cable for proper seating at both ends.

IF THE FAULT IS NOT CORRECTED, REFER TO CHAPTER 4 FOR CORRECTIVE
ACTION.

If the H3014 is installed in a remote location, it is the customer’s responsibility to supply and
install the remote T1 cable. (Refer to Appendix B for T1 cable information.)

2X4 /0 PANEL
(TYPICAL)

LOOPBACK CONNECTOR

) -

I/0 PANEL

- -~

INSERT

NOTE

THE LOCATION OF THIS I/O PANEL
INSERT CONNECTOR WILL VARY
WITH EACH UNIT. THIS IS
ONLY A TYPICAL
REPRESENTATION.
MKV84-0481

Figure 2-11

H3027 Loopback Connector Installed on 1/0O Bulkhead
2-17

Remove the H3027 loopback connector from the 1/O bulkhead. Connect the remote
T1 cable
or BC18L-15 to the 2 X 4 I/O panel. (refer to Figure 2-12).
Install the H3027 loopback connector (Figure 2-12) to the opposite end of the remote
T1 cable
or BC18L-15, and execute EVDAE diagnostic for two passes with event flag
3 set.

NOTE
This loopback test can only be performed if the T1
cable length is 762 m (2500 ft) or less in length.

REMOTE CABLE

(REFER TO APPENDIX B)

2X4 /0 PANEL

MKV84-0484

Figure 2-12

H3027 Loopback Connected to Remote End of T1 Cable

2-18

After two successful passes of EVDAE, stop the diagnostic and remove the H3027 loopback
connector. Connect the remote T1 cable or BC18L-15 to the T1 input connector on the H3014
(Figure 2-13).

ey Pl Pl I

|: (

VAR

BC18L-15

CONNECTOR

[

|
|
|

2X4 1/0 PANEL

7~
L/

Figure 2-13

MKV84-0482

T1 Connector Between 1/0 and H3014

2-19

Install the six (6) 29-24929-00 staggered loopback connectors, which
are supplied in the CD kit
(Figure 2-14).

29-24929-00 LOOPBACK CONNECTOR

P@o::::::]cj

[06.....:........)01

O
HANDLE N

follecseassol
foleenen)o]

(REAR VIEW)

(FRONT VIEW)

el Lol

ol |

o] |

29-24929-00

MKV84-0483

Figure 2-14

29-24929-00 Installed on H3014 Distribution Panel

2-20

10.

Execute EVDAE diagnostic for two passes with event flag 6 set.
If a failure occurs, check the following:

TI cable for proper seating,

H3014 modules for proper seating, and

H3014 power supply voltages.

IF THE FAULT IS NOT CORRECTED, REFER TO CHAPTER 4 FOR CORRECTIVE
ACTION.

CAUTION

To check the H3014 boards for proper seating, refer
to Chapter 4 for the procedures when removing the
Field Replaceable Units (FRUs) of the H3014 and
checking power supply voltages.

11.

On successful completion of EVDAE, remove the 29-24929-00 loopback connectors from the

12.

Execute the DMZ32 on-line diagnostic EVDAF with internal loopback set (loop type equals

H3014 distribution panel.

four). Refer to Chapter 4 for details.

If a failure occurs, perform the following:
e

Check for proper module seating,

Verify proper UNIBUS placement, and

Check voltages.

IF THE FAULT IS NOT CORRECTED, REFER TO CHAPTER 4 FOR CORRECTIVE
ACTION.

13.

14.

User Exerciser Test Progra
After the DMZ32 has passed the EVDAF diagnostic, execute the
configuration.

(UETP). If a failure occurs during UETP, check the system

After the DMZ32 has passed UETP, return the system to the normal configuration and initiate
customer acceptance.

NOTE

Refer to Figure 2-15 for the DMZ32 installation
overview to see how all component parts tie together.

2-21

H3014 DISTRIBUTION PANEL

H3028

| Jooo HE=EY

HEEE

BEEP Rl

)4 m8398
J1

BC22 E/F OR

M8398

CONNECTOR

UNIBUS INTERFACE MODULE

rnn

EQUIVALENT

29-2429-00
LOOPBACK

CONNECTOR

CABLE AND

(REAR

H3027

PANEL

JIEM_VIEW)

TEST
-

o
(FRONT

H3248

TEST

’

[lo]

I Al

lol

1o [ el

ol [ 1] [ lo] | o
llo] | lo] | Je

I
I

'
I

/: /L'
|

-]
-

EQUIVALENT}
BC18L-15

T1 CABLE

REAR CABINET
AREA
e

H9642-FC/FD

o H9652-MF
MKV84-0485

Figure 2-15

DMZ32 Installation Overview

2-22

[

2.7

DMZ32 INSTALLATION CHECKLIST

PHASE 1 - Preinstallation Considerations

System Requirements (Section 1.5)

a. M8398 Module (Section 1.5.1)
UNIBUS Loading
Power Requirements

Interrupt Priority Level

DMZ32 Device Addrcss Determination
b. H3014 Distribution Panel (Section 1.5.2)
Power Requirements

PHASE II - M8398 Installation

Unpack DMZ32 option and verify that all
components were shipped (Section 2.2 and
Table 2-1)

E-63 set for proper priority level
(Section 2.5.1 and Figure 2-1)

E-53 S1 through S8 set to UNIBUS address,

refer to Appendix A for UNIBUS address

(Figure 2-1)

E-53 S9 set to “ON” (Figure 2-1)

E-53 S10 set to “ON” (Figure 2-1)

NPG wire (CA1 —CB1) removed

Backplane resistance checks complete

8.
9.

With power ON, verify selected SPC backplane
voltages

Install M8398 module into selected SPC slot
of the backplane

2-23

PHASE III - H3014 Installation
1.

Unpack H3014 distribution panel and verify
that all components were shipped

Install H3014 into proper cabinet

Connect power cable to switched output of
power controller (Section 2.5.2)

If the H3014 is received in a cabinet, remove
the shipping bracket

PHASE IV - Cable Installation
1.

Connect the 2 X 4 I/O panel supplied with
the DMZ32 to the BC22N-10 cable

Remove blank 1/0 panel from the FCC Bulkhead

Frame to make space for the new I/O panel
supplied with the DMZ32

Connect BC22N-10 cable to the M8398 module
Connect BC18L-15 cable between the BC22N-10

2 X 4 1/0 panel and the H3014 distribution
panel

PHASE V - DMZ32 System Checkout
1.

Run EVDAE with H3028 connected to J1 of the
M8398 module (Section 2.6)

hat

Connect M8398 module to the BC22N-10 cable
I/O panel (Figure 2-10)
Run EVDAE with the H3027 connected to the
BC22N-10 cable (Section 2.6)
When power is applied to the H3014, the
front panel LEDs display a normal indication
(Refer to Table 4-4)

Run EVDAE with BC18L-15 connected to the I/0
panel with an H3027 turnaround connected to

the open end of the cable. [If a remote
cable, connect the H3027 to the far end of
the T1 cable ONLY if the cable is 762 m
(2500 ft) or less in length]

224

Disconnect the H3027 from the T1 cable and
connect the T1 cable to the H3014 T1
connector. Then place six (6) 29-24929-00
staggered turnaround connectors on the H3014
distribution panel and run EVDAE. EVDAE runs
successfully under all conditions
(Section 2.6)

EVDAF runs successfully under all conditions
(Section 2.6)

Remove all loopback connectors, and turn
the system over to the customer

2-25

CHAPTER 3
PROGRAMMING

3.1

INTRODUCTION

This chapter describes the different registers that control the operation of the DMZ32. Each register is
listed and the different bits of each register are defined.
Opverview

3.1.1

The DMZ32 asynchronous multiplexer contains three (3) octets of eight (8) transmit and eight (8) receive
lines, each making a total of 24 lines available for data. These 24 lines may be programmed to operate at
one of 14 baud rates from 50 bits/s to 19,200 bits/s. All 24 lines have the capability of operating with
different receive and transmit baud rates. All lines have modem control and each receive and transmit line
can be independently enabled or disabled. There is a separate receive and transmit interrupt vector for
each of the 3 octets. These vectors may be enabled or disabled independently. Separate TX READY and
RX DATA AVAILABLE bits exist for each octet to allow for non-interrupt driven device operation.
These octets can be operated independently. For example, each octet can be reset without affecting any of
the other octets.

In the DMZ32, receive characters with their respective line numbers and status information are stored in a
128-character silo. Each octet has its own RX silo. An interrupt may be generated for the following
reasons:

The RX silo contains 64 characters, or

The RX silo has been nonempty for more than a programmed time interval since the last time
the RX silo was read.

The DMZ32 may be programmed to echo all received characters.

Each transmit line has its own 32-character TX silo. All characters to be transmitted must first be loaded
into the respective TX silo. The TX silo may be loaded in one of two ways. The first method (programmed
mode) is to use CPU move instructions to load one or two characters at a time into the proper indirect
address register. The second method (DMA mode) is by means of Direct Memory Access (DMA) transfers
from main memory. Once a DMA transfer has been initiated, characters are automatically put into the
TX silo every time the TX silo count drops below eight characters. This cycle continues until the DMA

byte count is zero. When the last character to be transmitted is fetched from the TX silo, an interrupt will
be generated if requested. If desired, each TX silo may be flushed, resulting in emptying the TX silo and
zeroing any remaining DMA byte count. If the TX interrupt enable bit is HIGH, an interrupt is generated.
Each transmit line may be operated in an automatic XON/XOFF mode. The line’s receiver must be
enabled for this mode to operate. When enabled, a received XOFF character causes the respective
transmit line to be disabled. In a similar manner, receiving an XON character causes the transmit line to
be enabled. In both cases, the XON or XOFF character is stored in the octet’s RX silo so that the
operating system is aware that transmissions have been either enabled or disabled. This mode of operation
allows for long RX silo timeouts as the time-critical XOFF instantly disables the transmitter.

3-1

3.1.2 Device Registers
The UNIBUS to DMZ32 interface uses three (3) groups of four (4)
device registers, one for each octet. The four device registers are:
®

Octet Control and Status Register (OCTET.CSR),

Octet Line Parameter Register (LINE.PAR.REG),

Octet Receive Buffer (RX.BUF)/OCTET Receive Silo Parameter (RSP.REG), and

Octet Indirect Registers (IND.REG).

3.1.3 Octet Control and Status Register (OCTET.CSR)
The OCTET.CSR is used for the following:
To select one of four indirect registers,
To select a register line number,

To initiate a Master Reset,
To enable/disable receive and transmit interrupts,

To indicate when data is in the RX silo,
To indicate when a TX silo is empty, and

To indicate a NXM error.
3.1.4 Octet Line Parameter Register (LINE.PAR.REG)
The LINE.PAR.REG is used to specify the following:
The bits per character,
The number of stop bits per frame,
The receive and transmit baud rates, and
The parity enable/disable and sense.

3.1.5 Octet Receive Buffer (RX.BUF)/OCTET Receive Silo Parameter (RSP.REG)
The RSP.REG is used to read the following:
®
®

The received character, and
The status byte associated with the received character.

The RSP.REG is used to write the RX silo alarm timeout value.
3.1.6 Octet Indirect Register (IND.REG)
The IND.REG is used as a window to one of four registers (IND.REG 0, IND.REG 1, IND.REG
2, or
IND.REG 3). The following can be performed by the appropriate registers:
e

IND.REG O
-

Write to the TX silo
Read the TX silo count

Read the RX modem signals

IND.REG 1

—
—

-~
—~
-

—
—
e

IND.REG 2

—
e

Specify the lower 16 bits of a DMA buffer address

IND.REG 3

—
3.2

Enable a pre-empt character
Set the TX modem signals
Enable the maintenance control functions
Enable the reporting of an RX modem signal change
Flush the TX silo
Break the TX line
Enable the receiver and/or transmitter
Enable auto XON/XOFF

Specify the upper two bits of a DMA buffer address
Specify the DMA transfer byte count

INITIAL OPERATION

Before the DMZ32 can be prepared for loading line parameters, the system itself must be checked for
proper operation. A selfdiagnostic routine within the DMZ32 is run to verify proper operation. This selfdiagnostic is run under the following conditions:
On powerup,

After UNIBUS Initialization (INIT),
M8398 pushbutton switch, and
AAO0O to the diagnostic register.

3.3

PARAMETER INITIALIZATION

After an INIT or a Master Reset has occurred within the DMZ32, the transmit and receive buffers are
empty and all lines are disabled. Before operation can begin, the operating system must load the line
parameter register (LINE.PAR.REG<15:0>) with the desired parameters for specific lines before enabling these lines. (The line parameter registers must be loaded even if all parameters are zero.)
The line number whose parameters are to be loaded is contained in the lower order byte of the Line
Parameter Register, LINE.SELECT <2:0>. After the program optionally sets the appropriate interrupt
enable bits in the Control and Status Register (CSR<15:0>), the program is ready to enable the desired
transmit and receive lines.

TX modem control signals coming from the DMZ32 can be set or cleared at any time after an INIT or a
Master Reset. The TX modem signals are cleared only after an INIT and are not affected by a Master
Reset.

RX modem control signals going to the DMZ32 are loaded into the respective device register every time
there is a change on one or more of the signal lines. An INIT or a Master Reset also causes a device
register update.

3-3

3.4 TRANSMIT OPERATION
Before the transmission of data can occur, a line must be enabled. The enabling of a transmit line is
performed by setting the appropriate bit in the IND.REG 1 register. If the appropriate bit is not set, the
line is disabled and held in the marking state (providing the line is not programmed for auto echo or
remote loopback).
TX.RDY is asserted whenever a transmit silo becomes empty due to a character being tranmsitted from

the silo or a silo flush.

If TX.LE. is active when TX.RDY becomes set, then an interrupt to the transmit vector is posted. The
program should read OCTET.CSR<15:0> in order to determine the cause of the interrupt. If TX.RDY is
set, then OCTET.CSR<2:0> will contain the line number where the silo is empty. OCTET.CSR<13> is
set if the transmission has been stopped due to an aborted DMA transfer. The act of reading
OCTET.CSR<15:0> clears TX.RDY. This is important because TX.RDY has to be cleared before the
DMZ32 can assert TX.RDY for another line.
To minimize the possibility of interrupt overload from occurring, the program should attempt to keep silos
full at all times. If the program decides to fill a specific silo, it may inspect the transmit silo count register

to determine how many characters have been transmitted from the silo while it is being filled. The silo
count indicates how many full positions there are in the silo. Because of this, a silo count of zero indicates
an empty silo, and a silo count of 32 indicates a full silo. The transmit silo count registers may be examined
at any time and any particular line’s silo may be loaded or flushed. These operations may be performed
whether the respective transmit line is enabled or not. If a line is disabled while its silo is being emptied,
transmission stops after the current character has been transmitted. However, if the silo has been loaded,
the silo contents will remain and upon enabling the line, transmission from the silo will resume as normal.
3.5 RECEIVER OPERATION
The receive lines in the DMZ32 are enabled by setting appropriate bits in IND.REG 1. A line must be
enabled in order to receive data. All lines in each octet share a 128-character receive silo. There is no
DMA mode for the receiver.
3.6 DEVICE REGISTERS AND VECTOR ASSIGNMENTS
A block of 16 words has been assigned to the registers that control the DMZ32. This block includes the
base CSRs and four line registers for each octet. The base address is selected in the floating CSR range by

means of DIP switches on the DMZ32 module. (Refer to Appendix A for the floating device addresses and
vectors.)
The floating CSRs for the DMZ32 are in a contiguous block of 14 words. (Refer to Figure 3-1.) Eight

switches on the DMZ32 determine bits <12:5> of the starting address. The registers contained in this
block can be addressed only by word except the registers that are used to access a line’s transmit silo.
Access by word means that the instruction operating on the register causes a data out (DATO) rather than
a data out byte (DATOB) UNIBUS cycle. The DMZ32 pays no attention to the least significant UNIBUS
address bit on registers that are word access only. Because of this, the register block must be located on a
20-hex address boundary. The 16 words are allocated to the devices as shown in Figure 3-1.

CONFIGURATION CONTROL AND STATUS
CONFIG. CSR
DIAGNOSTIC CONTROL AND STATUS
DIAG.CSR

7760444
8

OCTET CONTROL AND STATUS
LINE PARAMETER

RECEIVER BUFFER/RECEIVE SILO PARAMETER
RX.BUF/RSP.REG

INDIRECT REGISTERS

IND.REG[O].[1].[2].[3]

OCTET CONTROL AND STATUS
LINE PARAMETER

OCTET O BASE +0

OCTET

OCTET O BASE +4

OCTET O BASE +6

OCTET 1 BASE +0

OCTET 1 BASE +2

LINE.PAR.REG

RECEIVER BUFFER/RECEIVE SILO PARAMETER
RX.BUF/RSP.REG

INDIRECT REGISTERS

IND.REG [0].[1].[21.[3]
7760464
8

DMZ32 BASE +2

OCTET O BASE +2

LINE.PAR.REG

7760454

DMZ32 BASE +0

OCTET CONTROL AND STATUS
LINE PARAMETER

OCTET 1 BASE +4

OCTET 1 BASE +6

N5
g

7760440
8

OCTET 2 BASE +0

OCTET 2 BASE +2

LINE.PAR.REG

RECEIVER BUFFER/RECEIVE SILO PARAMETER
RX.BUF/RSP.REG

INDIRECT REGISTERS
IND.REG[0].[1].[2).[3]

OCTET

OCTET 2 BASE +4

OCTET 2 BASE +6
MKV84-0486

Figure 3-1

DMZ32 Word Allocation of Device Control/Status Registers

3-5

3.7 CONFIGURATION CONTROL AND STATUS REGISTER (CONFIG.CSR)
The configuration control and status register has an address that establishes the rest of the remaining
addresses for the DMZ32. Refer to Appendix A for the floating device addresses and vectors. This register
is used by the VAX/VMS operating system at the time the system is being automatically configured.
The autoconfiguration routine scans each bit of the CONFIG.CSR register to determine what type drivers

should be loaded.
Refer to Figure 3-2 for a bit map overview of the DMZ32 registers.

CONFIG. CSR

INTERFACE TYPE

VECTOR BASE ADDRESS

DIAG. CSR

NUMBER OF OCTETS

DIAGNOSTIC COMMAND

L[]
l

TRANSMIT

OCTET-CS R ( R EAD/WR 'TE)

NOT USED

og8

RECEIVE

BIT

READY

INDIRECT REG.

RESET

AVAILABLE

UNUSED 8IT

MASTER

DATA

ENABLE

TRANSMITTER

UNUSED

INTERRUPT

LINE NUMBER

RECEIVE

INDIRECT

INTERRUPT

REG. NUMBER

ENABLE
TRANSMIT

DMA ERROR

LTRANSMIT BAUD RATE

RECEIVE BAUD RATE l

LENGTH

LINE.PAR.REG (READ/WRITE)
STOP CODE

CHARACTER

] LINE SELECT ]

PARITY
ENABLE

EVEN/ODD

PARITY

[
RX.BUF (READ ONLY)

DATA

FRAMING

DATA SET

VALID

ERROR

CHANGE

OVERRUN

PARITY

ERROR

RSP.REG (WRITE ONLY)

{

TRANSMIT CHARACTER

RECEIVE CHARACTER

RESERVED BITS

IND.REG O (WRITE ONLY)

NUMBER

RECEIVE LINE

RECEIVER SILO ALARM TIMEOUT

]

TRANSMIT CHARACTER

MKV84-0487

Figure 3-2

DMZ32 Register Bit Map Overview (Sheet 1 of 2)

3-6

[

USED BITS

TRANSMIT SILO COUNT

]

INDICATOR | SEND

DATASET

CARRIER

READY

DETECT

RECEIVE

UNUSED

12
13

UNUSED
BITS

TERMINAL |

BIT

REQUEST
TOSEND

READY

DATA
SIGNAL

RATE

UNUSED | DATA

PREEMPT

IND.REG 1 (READ/WRITE)

]

MAINTENANCE | FLUSH

TRANSMIT |

CONTROL

USER
TRANSMIT

siLo

DATASET
CHANGE

BREAK

ENABLE

RECEVE | TRANSMIT

ENABLE | ENABLE
TRANSMIT
AUTO

XON/XOFF

SELECT

IND.REG 2 (READ/WRITE)

TRANSMIT BUFFER ADDRESS
14

TRANSMITI

DMA CHARACTER COUNT

BUFFER

ADDRESS

IND.REG 3 (READ/WRITE)

]

MKV84-0488

DMZ32 Register Bit Map Overview (Sheet 2 of 2)

Figure 3-2

There are six interrupt vectors used by the M8398 contiguous to the first vector. There are no switches on
the M8398 module that have control over the interrupt vectors because the interrupt vectors are under
software control. Refer to Figure 3-3 for the CONFIG.CSR bit map.

Refer to Table 3-1 for the bit map of the configuration control and status register

(CONFIG.CSR<15:0>).

This register may be accessed with a Read Modify Write (RMW) cycle.

15
INTERFACE TYPE

VECTOR BASE ADDRESS

NUMBER OF OCTETS

NOTE

BITS <1:0> OF THE UNIBUS VECTOR
ADDRESS ARE ALWAYS ZERO; THEREFORE
ONLY THE TOP EIGHT BITS <9:2> OF THE
UNIBUS VECTOR ARE EVER LOADED INTO
CONFIG.CSR <7:0>.
MKV84-0491

Figure 3-3

Configuration Control and Status Register (CONFIG.CSR) Bit Map

3-7

Table 3-1

Configuration Control and Status Register Functions

Bits

Title

Function

<7:0>

Vector

The CONFIG.CSR<7:0> is read/write and is loaded at autoconfiguration with the vector address of vector [0}<9:2>. The six floating interrupt vector addresses are:
o

Vector [0]<9:2> Receive vector for FIRST octet,

Vector [1]<9:2> Transmit vector for FIRST octet,

Vector [2]<9:2> Receive vector for SECOND octet,

Vector [3]<9:2> Transmit vector for SECOND octet,

Vector [4]<9:2> Receive vector for THIRD octet, and

Vector [5]<9:2> Transmit vector for THIRD octet.

NOTE
There are no switches on the DMZ32 for interrupt

vectors. The six vector locations are loaded by the
operating system at autoconfiguration time. The

other vectors are assumed to be contiguous as shown
below.
®

®
®
®
®

Vector [0]<9:2> = 320
Vector [1]<9:2> = 324
Vector [2]<9:2> = 330
Vector [3]<9:2> = 334
Vector [4]<9:2> = 340
Vector [5]<9:2> = 344

These bits are cleared upon receipt of INIT.D executing the microdiagnostic.
<11:8>

Number

CONFIG.CSR<11:8> is always read as a binary value
of three.

When a binary three (11) is present in CONFIG.CSR<9:8>, a 24line unit (three eight-line groups or octets) is to be configured.
<15:12>

Interface

CONFIG.CSR<15:12> is always read as zero and controls
the

loading of drivers. Because only asynchronous lines are available,
only asynchronous drivers are loaded.

3.8 DIAGNOSTIC CONTROL AND STATUS REGISTER (DIAG.CSR)
The diagnostic control and status register has an address of Device Base + 2.

The diagnostic control and status register (DIAG.CSR) is the UNIBUS window into the DMZ32. The
DIAG.CSR can be regarded as a device used by the host processor in controlling trunk loopback functions,
monitoring test status, requesting/reporting microcode revision numbers, and starting on-board
diagnostics.

3.8.1

Diagnostic Control and Status Register (DIAG.CSR<15:0>) — Write

The bit map for the DIAG.CSR<15:0> — Write — can be seen in Figure 3-4. The DMZ32 uses only the
upper byte (<15:8>) of this register for commands. This is for DMF32 conformity. (Refer to Table 3-2
for the functions performed.)

This register may NOT be accessed with an RMW cycle; it can be accessed by word only.
00

NOT USED

DIAGNOSTIC COMMAND

MKV84-0490

Figure 3-4 Diagnostic Control and Status Register DIAG.CSR<15:0> Bit Map — Write
Table 3-2 Diagnostic Control and Status Register DIAG.CSR<15:0> - Write
Bits
<15:8>

Hex

Decimal

Octal

Function/Test Description

170

252

Start self-test

125

Halt UBI microcode

Read UBI microcode version number

Read TIU microcode version number

Read RDP microcode version number

Set local trunk loopback

Clear local trunk loopback

Set ALL lines loopback (EIA)

Clear ALL lines loopback (EIA)

Read T1 status register

3-9

3.8.2 Diagnostic Control and Status Register DIAG.CSR<15:
0>
— Read
The bit map for the DIAG.CSR<15:0> — Read
- is shownin Figure 3-5. (Refer to Table 3-3 for the
functions performed.)

This register may NOT be accessed with an RMW cycle, it can be

accessed by word only.

00
STATUS OR ERROR RETURNED

VALID

MKV84-0489

REG
ERROR/

STATUS

Figure 3-5

Diagnostic Control and Status Register DIAG.CSR<15:0> Bit

Table 3-3

Map - Read

Diagnostic Control and Status Register DIAG.CSR<15:0>

Bits

Hex

<15>

(Valid Data Flag)

Decimal

Octal

Function/Test Description
This bit is used to indicate if the content of the

diagnostic register is valid. If it is not set, the
microcodeis still executing the self-test.
<14>

(Status or Error Flag)

This bit indicates if the content of the diagnostic

0 = Status
1 = Error
<13:0>

(Status or Error Return)

NOTE
Refer to Table 4-1 for details.

3-10

3.9 OCTET CONTROL AND STATUS REGISTER (OCTET.CSR) - READ/WRITE
The octet control and status register (OCTET.CSR<15:0>) has an address of Octet Base + 0. The bit map
for the OCTET.CSR<15:0> is shown in Figure 3-6. (Refer to Table 3-4 for the bit functions performed
by this register.)

This register may NOT be accessed with an RMW cycle.
15

TRANSMIT LINE
NUMBER

TRANSMIT
INTERRUPT

ENABLE

RECEIVE
DATA

UNUSED
BIT

AVAILABLE

RECEIVE

UNUSED

TRANSMITTER

INTERRUPT

BIT

READY

INDIRECT REG.
LINE NUMBER

MASTER
RESET
INDIRECT

REG. NUMBER

ENABLE

TRANSMIT

QMA ERROR
MKV84-0494

Figure 3-6

Octet Control and Status Register (OCTET.CSR) Bit Map

Table 3-4

Octet Control and Status Register Functions

Bits

Title

Function

<15>

Transmitter
Ready

This bit is set when an enabled line (pointed to by OCTET.CSR
<10:8>) has loaded the last character from the silo into the

respective line holding register.

This read/write bit is cleared by a Master Reset, INIT, or the
act of reading this register.

<14>

Transmit
Interrupt

When set, this bit allows interrupt requests to be made to the
transmit vector when TX.RDY is set.

Enable

A Master Reset or INIT clears this read/write bit.

<13>

Transmit
DMZ.NXM
Error

This bit is used only when the respective line is in DMA mode.
This bit is set for the indicated line if the DMZ32 UNIBUS
controller either did not receive a SSYN at least 32 microseconds
after issuing a MSYN, or the controller could not become bus
master for at least 32 microseconds after having asserted BUS
NPR. OCTET.CSR <2:0> points to the line in error.

This read only bit is cleared when the program reads this register
by Master Reset, or an INIT.

3-11

Table 3-4

Bits

Title

<12>

Not Used

<ll>

Not Used

<10:8>

Octet Control and Status Register Functions (Cont)

Function

Transmit

When TX.RDY is set, the Transmit Line contain

s the number of

Line
Number

the line whose silo has become empty. These bits are read
only,
and are cleared by a Master Reset, INIT, or the act of
reading

this register.
<7>

Receive

This read only bit is set whenever data is availab

le in the receive

Data
Available

silo and is automatically cleared when the receive silo is empty.

Receive Data Available (RX.DATA.AVAIL) is cleared
by a
Master Reset or INIT.
<6>

Receive

When this read/write bit is set, interrupt requests can be
made to
the receive vector under the following conditions:

Interrupt
Enable

Receive Data Available has been set for longer than the

timeout period, and
°

64 characters have entered the receive silo.

This read/write bit is cleared by a Master Reset or INIT.
<5>

Master

When this read/write bit is set, a Master Reset is initiated

. This

Reset

bit remains set while resetting is taking place and is cleared after

Master Reset has occurred. This bit remains set after a
self-test
failure. The program should not access device registers of
the
octet being reset (other than this one) while reset is occurrin
g.
Writing to this register while a Master Reset is taking place
has
no effect. Master Reset takes up to 500 microseconds.
NOTE
Performing the Master Reset function affects only

one octet. Each octet must be individually reset.

<4:3>

Indirect

These read/write bits point to one of four (4) indirect registers

These bits are automatically cleared by Master Reset or INIT.,
These read/write bits point to one of eight (8) indirect

groups. This register is accessed through location Octet Base +

These bits are automatically cleared by Master Reset or INIT.

3-12

3.10 LINE PARAMETER REGISTER (LINE.PAR.REG<15:0>) - READ/WRITE

The line parameter register has an address of Octet Base + 2. The bit map for the line parameter register is
shown in Figure 3-7. Refer to Table 3-5 for individual bit functions.

This register may be accessed with a RMW cycle.
NOTE

The line parameter register should ALWAYS be
loaded with the parameter for the particular line
before the line is enabled (even if the parameters are
all zeros).

Bits <2:0> are used to specify the line number when
writing only. When reading, OCTET.CSR <2:0>
selects the line number.

E;Sgfi‘:TER

TRANSMIT BAUD RATE | RECEIVE BAUD RATE

LINE SELECT

PARITY

STOP CODE

ENABLE

EVEN/ODD
PARITY
MKV84-0493

Figure 3-7

Line Parameter Register (LINE.PAR.REG.<15:0>)

Table 3-5

Line Parameter Register Functions

Bits

Title

Function

<l15:12>

Transmit

When a line is selected, these bits specify one of the following 14

Baud Rate

transmit baud rates:
Bits <15:12>

Baud

Rate

0000
0001
0010
0011
0100
0101
0110
0111
1000

50
75
110
134.5
150
300
600
1200
1800

Baud
Baud
Baud
Baud
Baud
Baud
Baud
Baud
Baud

3-13

Table 3-5

Bits

<11:8>

Title

Function

Receive

Baud Rate

Line Parameter Register Functions (Cont)

1001

2000

1010

2400

1100

Baud

4800

1110

Baud

9600

Baud

1111

19200

Baud

Split baud rate capability is supported.

When a line is selected, the receive baud rate specifies the selected receiver’s baud rate.
Bits <15:12>
0000

<7>

Stop Code

Baud

Rate

0001
0010
0011
0100

Baud

150

0101
0110

Baud
Baud
Baud
Baud

300
600

Baud

110
134.5

Baud

0111

1200

1000

Baud

1800

1001

Baud

2000

1010

Baud

2400

1100

Baud

4800

1110

Baud

9600

1111

Baud

19200

Baud

This bit specifies the number of stop bits for the selected line as
follows:

Logic 0 = 1 stop bit
Logic 1 = 2 stop bits
<6>

Even/Odd

Parity

When parity enable is set, even/odd parity specifies which parity

is being used as follows:

Logic 0 = odd character parity
Logic 1 = even character parity
<5>

<4:3>

Parity

When set, this bit causes a parity bit to be generated on trans-

Enable

mission. The parity bit is checked and stripped on reception of
the selected line.

Character

These two bits specify the character length (not counting start,
stop, and parity bits, if enabled) for the selected line as follows:

3-14

Table 3-5

Function

Title

Bits

Line Parameter Register Functions (Cont)

00 = 5 bits per character
01 = 6 bits per character
10 = 7 bits per character
11 = 8 bits per character

These bits contain the binary number of the line whose parameters are to be written. Selection of a particular line for reading is

Line Select

<2:0>

done by way of OCTET.CSR<2:0>.
*

3.11

RECEIVE BUFFER REGISTER (RX.BUF<15:0>) READ ONLY

The receive buffer register has an address of Octet Base + 4. Refer to Figure 3-8 for the bit map of the
receive buffer register and Table 3-6 for the functions of each bit contained in this register.
It is through the receive buffer register that the program accesses the receive silo. Every time this register
is read, data words in the silo shift down by one position. Successive read cycles access successive silo
entries. This receive silo not only contains receive characters and associated status information, but also
contains data set change information. Master Reset or INIT flushes the silo.
This register may NOT be accessed by an RMW cycle.

RECEIVE LINE

RECEIVE CHARACTER

NUMBER

DATA

FRAMING

DATA SET

VALID

ERROR

CHANGE

OVERRUN

PARITY

ERROR

MKV84-0492

Figure 3-8

Receive Buffer Register (RX.BUF) Bit Map - Read Only

3-15

Table 3-6

Bits

Title

<15>

Data

Valid

Receive Buffer Register Functions

Function
When this bit is set, the remaining bits are valid. This bit is set

when data is loaded into the receive buffer register. This bit

remains set as long as there is data in the buffer.

This bit is cleared by Master Reset, INIT, or when the receive
buffer becomes empty.
<14>

<13>

<12>

Overrun

clear. This bit is set if one or more previous characters were lost
on the line due to the silo being full.

Framing

This bit is useful only if Data Set Change (RX.BUF<11>) is

Error

clear. This bit is set if the line on which the character was
received was in the spacing (0) state at the time the first stop bit
was sampled.

Parity

This bit is useful only if the Data Set Change (RX.BUF<11>) is

Error

<l1>

Data

Set
Change
<10:8>

Receive

Line
Number
<7:0>

This bit is useful only if Data Set Change (RX.BUF<11>) is

Error

Receive

Character

clear. If parity error has been enabled for the line on which the
character is received, and the character is received incorrectly,
this bit will be set.

When this bit is set, RX.BUF<7:0> is zero, and RX.BUF<10:8>

contains the line number of the modem line that has changed.
These bits contain the binary number of the line on which a

character was received and a data set change experienced.

These bits contain the received character only if RX.BUF<11> is

clear. If parity is enabled, the parity bit is stripped off. Charac-

ters less than eight bits in length are right justified with the high
order bits set to zero.

If RX.BUF<11> is set, then RX.BUF<7:0> will be zero and the
program should read the RX.MODEM signal.

3-16

3.12 RECEIVE SILO PARAMETER REGISTER (RSP.REG<15:0>) - WRITE ONLY
The receive silo parameter register has an address of Octet Base + 4. This register-is write only and is
accessed by word. The receive silo parameter register contains the receive silo alarm timeout. Refer to
Figure 3-9 for the bit map and Table 3-7 for the bit description of the receive silo parameter register.
This register may NOT be accessed by an RMW cycle.
15

RESERVED BITS

00
RECEIVER SILO ALARM TIMEOUT
MKV84-0496

Figure 3-9

Receive Silo Parameter Register (RSP.REG) Bit Map — Write Only
Table 3-7

Bits

Title

<15:8>

<7.0>

Receive Silo Parameter Register Functions

Function
Reserved Bits

Receive

Silo
Alarm
Timeout

These bits specify the silo alarm timeout period. An interrupt is

generated if data has been sitting in the silo for a time equal to
or longer than the timeout period. Every time the receive silo is
read, a Master Reset occurs or an INIT occurs, restarting the
internal timer.

The timeout period can range from 0 to approximately 255 milliseconds. Loading a value of zero into this register causes an infinite timeout.

The following shows the progression of how these eight bits specify the silo alarm rate:

00000000 =

Infinite timeout

00000001 =

Approximately one (1) millisecond
timeout

00000010 =

00000011 =

Approximately two (2) milliseconds
timeout

Approximately three (3) milliseconds
timeout

11111111

Maximum timeout, approximately 255
milliseconds.

Approximately one (1) millisecond is added for each bit increment. This timer is based on microcode loops
and is not very accurate. The receive silo alarm timeout is set to a value of 1 after a Master Reset or INIT.

3-17

3.13 INDIRECT REGISTERS
There are 32 indirect registers associated with each octet of the DMZ32. Only the generic indirect

registers are covered in this chapter. The generic indirect registers covered are IND.REG 0, IND.REG 1,
IND.REG 2, and IND.REG 3.

The indirect registers are addressed by the five-bit address in the octet control and status register <4:0>.
The lower three bits of the address OCTET.CSR <2:0> indicate the line number being referenced, and the
upper two bits OCTET.CSR<4:3> select which indirect register of that line is being accessed.

3.14 INDIRECT REGISTER (IND.REG[0]<15:0>) - WRITE ONLY
The indirect register [0] has an address of Octet Base + 6. This write only register should be written to only
while in the Programmed mode of operation. In the DMA mode of operation, writing to this register still
loads characters into the TX silo. This is permissible but results in the mixing of the two data streams.

Writing to this register enters one or two characters into the 32-character transmit silo for the selected line.
If the write to this register is a WORD; for example, UNIBUS DATO, then two characters are loaded into
the silo. The character in the lower byte is loaded into the silo first. If the write to this register is a BYTE;

for example UNIBUS DATOB, then only the lower byte is loaded into the silo, and the high order
character is ignored.
Refer to Figure 3-10 for the bit map and Table 3-8 for the bit description of the indirect register 0 — Write
Only.

This register may NOT be accessed by an RMW cycle.

08
TRANSMIT CHARACTER

00
TRANSMIT CHARACTER

MKVv84-0497

Figure 3-10

Indirect Register (IND.REG[0]<15:0>) Bit Map — Write Only

Table 3-8

Bits
<15:0>

Title

Function

Transmit

This register is reserved for data that is being transmitted.

Character

Indirect Register 0 Functions

Buffer

3-18

3.15

INDIRECT REGISTER (IND.REG[0]<15:0>) - READ ONLY

The indirect register [0] has an address of Octet Base + 6. Refer to Figure 3-11 for the bit map and Table
3-9 for the bit description of the indirect register 0 — Read Only.
This register may NOT be accessed by an RMW cycle.

USED BITS

RING

CLEAR TO

USER

INDICATOR

SEND

RECEIVE

DATA SET

CARRIER

READY

DETECT

00
TRANSMIT SILO COUNT

UNUSED

MKV84-0495

Figure 3-11 Indirect Register (IND.REG[0}<15:0>) Bit Map —Read Only

3-19

Table 3-9

Bits
<15:8>

<15>

Title

Function

Receive

This byte contains the receive modem status for the selected line.

Modem
Status

All modem signals represented in this register come from the
Data Communications Equipment (DCE). The MODEM.RX
byte is updated after a Master Reset or INIT but not flagged in
the RX silo. If the receive silo is full and data set change enable
(IND.REG[1]<5>) is set, a data set change will be flagged only
after the silo becomes nonfull. In this way, data set changes are
not lost when the RX silo is full.

Data

This bit reflects the state of the Data Set line (RS-232-C circuit

Set
Ready

<14>

Indirect Register 0 Functions — Read Only

Ring
Indicator

CC) coming from the modem connected to the selected line.

This bit reflects the state of the Ring Indicator line (RS-232-C
circuit CE) coming from the modem connected to the selected

line.
<13>

Carrier

Detect

This bit reflects the state of the Received Line Signal Detector

line (RS-232-C circuit CF) coming from the modem connected to

the selected line.
<l12>

Clear
To
Send

<l1>

<10>

This bit reflects the state of the Clear To Send line (RS-232-C
circuit CB) coming from the modem connected to the selected
line.

Not Used

User

Receive

This bit is connected to pin 25 of the RS-232-C connector on the

distribution panel. This bit may be used for whatever purpose the

user desires.

<9:8>

<7.0>

Not Used

Transmit

Silo
Count

These bits contain the number of entries in the 32-character

transmit silo for a selected line. They are cleared after Master

Reset or INIT.

3-20

3.16 INDIRECT REGISTER (IND.REG[1]<15:0>) -READ/WRITE
The indirect register [1] has an address of Octet Base + 6. This read/write register is cleared by a Master
Reset or INIT. This register must be loaded with the appropriate information prior to using a line after
Master Reset.

Refer to Figure 3-12 for the bit map and Table 3-10 for the bit map description of the indirect register 1 Read/Write.
This register may be accessed by an RMW cycle.

UNUSED
BITS

PREEMPT

UNUSED

DATA

MAINTENANCE

FLUSH

RECEIVE

TRANSMIT

BIT

TERMINAL

CONTROL

TRANSMIT

ENABLE

READY

SILO
BREAK

REQUEST

DATA

USER

DATA SET

TO SEND

SIGNAL

TRANSMIT

CHANGE

AUTO

ENABLE

XON/XOFF

RATE

TRANSMIT

SELECT

Figure 3-12

MKV84-0500

Indirect Register (IND.REG[1]<15:0>) Bit Map — Read/Write

Table 3-10

Indirect Register 1 Functions — Read/Write

Bits

Title

Function

<15:8>

Modem
Transmit

These read/write bytes represent the transmit modem signals for
the selected line.

These bits are cleared by an INIT but not by a Master Reset.
The modem signal lines always follow these bits.
<15>

Pre-empt

This bit is set by the program to pre-empt silo output. The user
may then load the transmit character indirect register. The low
byte that is loaded by the user will then be the next character to
be transmitted. This allows the program to interrupt Programmed
or DMA transmission to send a character (presumably an XON
or XOFF) and then continue the Programmed or DMA transmission. When this process is performed, take note that there is no
loss of characters or data. The pre-empt character is simply
inserted into the effective transmit output stream of data. When
indirect register O is loaded, this bit is automatically cleared. This
bit is cleared by Master Reset or INIT.

<14:13>

Not Used

3-21

Table 3-10

Bits

<12>

Title

Request To

Send

<l1>

<10>

Data

Rate
Select

Data

Terminal

<8>

Function

This bit controls the Request to Send line (EIA RS-232-C circuit

CA) that is connected to the modem. When this bit is set, the
Request To Send line is in the ON condition. When this bit is
clear, the Request To Send line is in the OFF condition.

Not Used

Signal

<9>

Indirect Register 1 Functions — Read/Write (Cont)

This bit controls the Data Signal Rate Select line (EIA RS-232-C

circuit CH) that is connected to the modem. When this bit is set,

the Data Signal Rate Select line is in the ON condition. When

this bit is clear, the Data Signal Rate Select line is in the OFF
condition.

This bit controls the Data Terminal line (EIA RS-232-C circuit

CD) that is connected to the modem. When this bit is set, the

Ready

Data Terminal Ready line is in the ON condition. When this bit
is clear, the Data Terminal Ready line is in the OFF condition.

User

This line is connected to pin 18 of the line’s 25-pin RS-232-C

Transmit

connector on the distribution panel. This pin is an EIA RS-232-C

unassigned pin. This line and the pin associated with it may be

used for whatever purpose the user desires.
<7:0>

Line

Control

These read/write bits are cleared by a Master Reset or INIT.

These bits must be loaded with the appropriate information prior
to using a line after a Master Reset has been generated.

<7:6>

Maintenance

Control
Function

These maintenance bits have the following meanings:

Normal Operation

Automatic Echo Mode

In this mode of operation, data is put into the received silo
and automatically retransmitted (regardless of the state of

TX.ENA) at the same baud rate as the transmitter.
RX.ENA must be set for this mode to work. Normal
transmitter operation is not inhibited in this mode.
10

Internal Line Loopback

In this mode of operation, the specific line’s output is internally connected to the line’s input (within the distribution

panel). Received data is looped back. All modem signals
are looped back when operating in this mode.

3-22

Table 3-10
Bits

Title

Indirect Register 1 Functions — Read/Write (Cont)
Function
11

Shared RAM Loopback

In this mode of operation, the specific line’s output is internally connected to the line’s input. All data and modem
signals are looped back at the UBI - TIU interface (shared
RAM).

<5>

<4>

<3>

Data

When set, this bit enables the multiplexer to search for a transi-

Enable

receive silo will have the Data Set Change bit set.

Set
Change

tion in the modem receive signals for the selected line. When
such a transition is found, the result is that the entry into the

Flush
X
Silo

The setting of this bit causes the transmit silo for the selected
line to be flushed and DMA terminated. Disabling the transmitter does not cause the silo to be flushed. Disabling the transmitter

Break

When this bit is set, the EIA Data line transmits spaces after the

simply inhibits character transmission. After the silo has been
flushed, this bit is automatically cleared and TX.RDY is set.
current character has finished being serialized. Transmission
resumes after the break is cleared.

<2>

Receive
Enable

When this bit is set, the receiver for the selected line is enabled.
When this bit is clear, the receiver for the selected line is disabled. If receive enable is set to zero while a character is being
assembled, the character is lost.

<1l>

<0>

Tx
Auto
XON/XOFF

When this bit is set, the receipt of an XOFF causes the transmit
enable bit to be reset. The receipt of an XON causes the bit to
be set. The XON/XOFF character is put into the RX silo if the

Transmit
Enable

When this bit is set, the transmitter for the selected line is enabled. When this bit is clear, the transmitter for the selected line

receiver is enabled.

is disabled. If transmit enable is cleared while a character is
being transmitted, the disabling of the transmitter occurs after
the complete character has been transmitted. Reception of an

XON or XOFF character sets or resets this bit if IND.REG [1]
<2> is set.

3-23

3.17 INDIRECT REGISTER (IND.REG|2]<15:0>) -READ/WRITE
The indirect register [2] has an address of Octet Base + 6. This read/write

register is not cleared by a
Master Reset or INIT. After a read or write to the buffer address register,
OCTET.CSR<4:3> is
automatically incremented to point to the respective line’s DMA character
count register.

The buffer address register is meaningful only if the respective line is in the DMA

mode of operation. This
register should be loaded with the lower 16 bits of the DMA buffer address for the
respective line. Writing
to this register while the DMA character count is nonzero will have unpredicta
ble results.
Refer to the Figure 3-13 for the bit map of the indirect register (IND.REG{2])
and to Table 3-11 for the
function of the bits contained in this register.
If a DMA error is encountered, the line will be taken out of DMA mode. The
register will contain the
address that caused the error.
This register may be accessed by an RMW cycle.

TRANSMIT BUFFER ADDRESS

MKV84-0499

Figure 3-13

Indirect Register (IND.REG[2]<15:0>) Bit Map - Read/Write

Table 3-11

Indirect Register 2 Functions — Read/Write

Bits

Title

<15:0>

Transmit

Buffer
Address

Function
The lower 16 bits of the DMA buffer

address

3-24

3.18 INDIRECT REGISTER (IND.REG[3]<15:0>) -READ/WRITE

DMA
The indirect register [3] has an address of Octet Base + 6. This read/write register contains the
a
initiates
registers
these
to
Writing
character count and the upper two bits of the transmit buffer address.
3Table
to
and
{3])
(IND.REG]
DMA transfer. Refer to the Figure 3-14 for the bit map of indirect register
12 for the function of the bits contained in this register.

The DMA character count is cleared by a Master Reset or INIT. The two address bits are not cleared. Ifthea
DMA error is encountered, the DMA character count will be set to zero. Bits <15:14> will contain
UNIBUS address bit <17:16>, which caused the error.
This register may be accessed by an RMW cycle.

TRANSMIT

DMA CHARACTER COUNT

BUFFER

|_ADDRESS
MKV84-0498

Figure 3-14 Indirect Register (IND.REG[3]<15:0>) Bit Map — Read/Write
Table 3-12

Indirect Register 3 Functions - Read/Write

Bits

Title

Function

<15:14>

Transmit

These bits contain the UNIBUS

Buffer

address bits <17:16>.

Address

<13:0>

DMA

Character

These bits contain the respective line’s
14-bit character count.

Count

NOTE

As characters are fetched by means of DMA cycles,
the DMA character count is decremented. Writing
to this register while the DMA character count is
nonzero will have unpredictable results.

3-25

CHAPTER 4
SERVICE

INTRODUCTION

This chapter describes Field Replaceable Units (FRUs), preventive maintenance, self-test diagnostics,
4.1

H3014 front panel indicators, and removal/replacement procedures.
4.2

DMZ32 FIELD REPLACEABLE UNITS

and system diagnostics aid
The DMZ32 is designed for ease of maintainability. Internal microdiagnostics
as follows:
in isolating the fault to a specific FRU. The FRUs of the DMZ32 are
e

UNIBUS interface module (M8398),

H3014 processor module (29-24797-00),

H3014 expansion module (29-24798-00),

H3014 power supply assembly (29-24799-00),

H3014 fan (29-24800-00),

H3014 chassis with I/O panel (29-24796-00),

3.0 m (10 ft) internal cable (BC22N-10), and

4.6 m (15 ft) external cable (BCI18L-15).

For the removal/replacement procedures for each of the FRUs, refer to Section 4.13.
4.3

PREVENTIVE MAINTENANCE

There is no scheduled preventive maintenance performed on the DMZ32. However, when system preventive maintenance is performed, check the following:
e

The voltages on the DD11-DK backplane,

The voltages on the processor module of the H3014 distribution panel,

The voltages on the expansion module of the H3014 distribution panel, and

The H3014 disribution panel fan operation.

4-1

DD11-DK Voltage Test Points

+5 V (CA2)
+15 V (CU1)

H3014 Voltage Test Points
Processor Module (Second Module) — Figure 4-1
TP14 (BLACK)
TP13 (RED)
TP12 (BLUE)
TP11 (WHITE)

= Ground
= 45V

= +12V
= —12V

TP11 (WHITE) = —12V

TP12 (BLUE) = +12V
TP13 (RED) = +5V

/TPM (BLACK) = GND
7 XA

me—
1

[ EXPANSION

“P2

]

! PROCESSOR |

@
A

SRERERE RN

llllllllllllllllllllll]1lll

—

llllllllllllllllllllllllTll

llllIl[IIllllllIllllllll[ll

[
MKV84-0501

Figure 4-1

Processor Module Test Points

4-2

Expansion Module (Top Module) - Figure 4-2
TP14 (BLACK)
TP13 (RED)
TP12 (BLUE)
TP11 (WHITE)

= Ground
=45V
= +12V
= -12V

TP11 (WHITE) =—12 V
TP12 (BLUE) =+12 V
TP13 (RED) =+5 V
/ TP14 (BLACK) = GND

121

1©]

A e
A\

]

[ EXPANSION

! PROCESSOR |
o |

,
]

B
|

llll]llllll
P SEERERENERUEN| lllI1llllllll]llllllllllllllllllllllllllIllllll'llllllllllllllllllllll

—

MKV84-05622

Figure 4-2

Expansion Module Test Points

4-3

Power Supply Assembly - Figure 4-3
TBI1-1
TBI1-2 } TB1-3

TB1-4

TB1-5

Input Line Voltage
:

Not Used
—12V

TB1-6

+12V

TB1-7

Chassis Ground

TB1-8

45V

(O]

m'n'

mTalsn

AAAL

EXPANSION

]

AR Aanlll

PROCESSOR

250 mA/250 Vv

3A/250 V

2A/250 V

SPARE

2A/250 V
MKV84-0502

Figure 4-3

Power Supply Assembly Test Points

4-4

4.4

SELF-TEST DIAGNOSTIC

The self-test diagnostic for the DMZ32 is an on-board Read Only Memory (ROM) based microdiagnostic.
The self-test diagnostic is executed during the following:
Power-up,

When the self-test pushbutton is pressed,
At UNIBUS initialization, and

When writing AA0O (HEX) to the diagnostic register.

The results of the ROM based microdiagnostics can be seen by reading the eight (3) Light-Emitting
Diodes (LEDs) that are mounted on the M8398 module. Refer to Figure 4-4 for the proper orientation of
how the LEDs are numbered. Refer to Table 4-1 for the LED coded display, the function tested when a
display is seen, and the field replaceable unit that is faulty for each display.

in a
When the self-test diagnostic is finished, and everything has passed the self-test, the LEDs cycle
the LSB
rotating pattern that repeats over and over. The pattern repeats from the MSB (LED 7) through
(LED 0).

When all the microdiagnostics are successfully passed, the LEDs display a walking ones (1s) pattern. This
is indicated by LEDs 7 through O flashing sequentially over a two (2) second time period. When
completed, a binary number is displayed indicating the peak, 24-line receive character rate since the last
peak character rate number was displayed. The binary number is displayed for approximately two seconds.
After the two seconds, the first binary number is followed by a second binary number that displays the
peak 24-line transmit character rate. This display also lasts for approximately two seconds. In both cases,
the binary number displayed can be translated to peak characters per second by dividing by 2 and
multiplying by 1000. For example, a binary number of 16 (00010000) translates to 8000 characters per
second. The TX peak character rate number is then followed by the walking ones pattern again.

MKV84-0503

Figure 4-4

M8398 LEDs

4-5

Table 4-1

M8398 LEDs
7(6(514[3]|2]1

MB8398 Coded LED Display

Function Tested
FRU

Diagnostic LEDs

Description

Hex | Decimal | Octal

Illegal Code

M8398 | Q Register Condition
Code

M8398 | Working Registers 0-7

)

M8398 | Working Registers 8-18

MB8398 | MSB of “A” & “B” Address | 04

MB8398 | Subroutine calls (4

of Working Register

Levels)
o0

MB8398 | Set Negative Bit

MB8398 | Set Carry Bit

MB8398 | Clear N Bit, C Bit

)

M8398

| 09

M8398 | Rotate Left, Rotate Right

M8398 | Mask Function

ole

M8398 | Negate Function

M8398 | Decrement Function

OD | 13

eloje

M8398 | OR Function

ole|®

- Not Used
-

)

- Not Used -

M8398 | Shared RAM (Addressing)

MB8398 | Shared RAM (Data)

| XOR Function, AUX Z Bit

WR & Q Register

|o®

MKV84-0654

Table 4-1

M8398 Coded LED Display (Cont)

Diagnostic LEDs

Function Tested

M8398 LEDs

615/4]3]2]1|0]

FRU

Hex | Decimal | Octal

Description

M8398 | LS Addressing (1K Sections) | 15

|o]e

M8398 | LS Addressing (.256K Blocks) | 16

|o|o|eo]|

M8398 | LS Addressing (Direct

o | M8398 | LS Data Indirect LO

o|
o|

eo|

EA PADRL1:>

COMF<24:25>

Space) COMJ<23:16>

M8398 | LS Addressing (Process

o|o]

Space) PROC<2:0>

ole

Octet 0

ole]

|o®

M8398 | LS Data Indirect HI

e|eo|

|o|e]|

M8398 | LS Data Indirect LO

oje|o®

M8398 | LS Data Indirect HI

oleje

e | M8398 | LS Data Indirect LO

M8398 | LS Data Indirect HI

ole|o|e|e | M8398 | LS Data Indirect LO

M8398 | LS Data Indirect HI

o | M8398 | Starting DMA Tests

M8398 | Slave Sync Time-Out

Octet 0
Octet 1

Octet 1

Octet 2

ele|o|e

Octet 2

Maintenance Space

°
°

During DMA DATO

o |eo| M8398 | Data Compare Error On
DMA DATO

MKV84-0655

4-7

Table 4-1

MB8398 Coded LED Display (Cont)

M8398 LEDs

Function Tested

716|5|4{3]2|1]0]

FRU

M8398

Description

Hex | Decimal | Octal

Slave Sync Time-Out

- Reserved -

Starting TIU Self-Test

On DMA DATI
°

e | M8398 | Data Compare Error On

DMA DATI

ole

M8398 | Failed To Become Master

On DATO or DATI

)

ejele

Diagnostic LEDs

(o]

|o®

M8398 | TIU 2901

2A | 42

(o]

|o]®|

M8398

| TIU 2901

|ole

M8398 | TIU Shared RAM

| 44

|o|o|

MB398

2D | 45

|o]o]e

MB8398 | TIU Micro-Sequencer

MB398

M8398 |

e | M8398 | TIU 2901

|of

®®|e

| TIU Micro-Sequencer

ole

MB8398 | TIU Local Store

ole

® | M8398 | TIU Local Store

| TIU T1 Interface

o | M8398 | TIU T1 Interface

ole

olo

ole|

|e@

ele|

|o|

M8398

|o]|

M8398

| TIU A23 Channel

M8B8398

| TI1 Link Synchronization

Failure

ole|

|ole

- Reserved
-

ole|

|o]o]e

- Reserved -

- Reserved
-

olele

MKV84-0656

Table 4-1

M8398 Coded LED Display (Cont)

Diagnostic LEDs

M8398 LEDs

Function Tested

6{514(3(211]0| FRU

Description

Hex | Decimal | Octal

- Reserved -

ele e

olele

- Reserved -

eole|o

ole

- Reserved -

ojo|o|o]0

- Reserved -

ololo|ojo|e

- Reserved -

eololole

eoloj|o]e®

)

MS8398

Internal Local T1 Data

100

)

o | M8398

Internal Local T1 Data

101

Path [Octet 0, Line 0]

Path {Octet O, Line 1]

MS8398

Internal Local T1 Data

102

e|e| M8398

Internal Local T1 Data

103

Path [Octet 0, Line 2]

Path [Octet O, Line 3]

M8398

Internal Local T1 Data

104

e | M8398

Internal Local T1 Data

105

ole

M8398

Internal Local T1 Data

106

eje|®| M8398

Internal Local T1 Data

107

Path [Octet 0, Line 4]

Path [Octet 0, Line 5]

Path [Octet 0, Line 6]

Path [Octet O, Line 7]

]

M8398

Internal Local T1 Data

110

e | M8398

Internal Local T1 Data

111

Path [Octet 1, Line 0]

Path [Octet 1, Line 1]

MKV84-0657

Table 4-1

M8398 LEDs

Function Tested

716|5141312{1|0|

MB8398 Coded LED Display (Cont)

FRU

Description

Hex | Decimal | Octal

Internal Local T1 Data

112

M8398 | Internal Local T1 Data

113

MS8398 | Internal Local T1 Data

114

o | M8398 | Internal Local T1 Data

| 77

115

116

M8398 | Internal Local T1 Data

117

M8398 | Internal Local T1 Data

120

e | M8398 | Internal Local T1 Data

121

MS8398 | Internal Local T1 Data

122

M8398 | Internal Local T1 Data

123

M8398

124

| 85

125

126

127

130

[

M8398 |

Path [Octet 1, Line 2]
)

o|e|

Path [Octet 1, Line 3]

ole

Path [Octet 1, Line 4]

ole

Path [Octet 1, Line 5]

olole

M8398 |

Internal Local T1 Data

Path [Octet 1, Line 6]
°

o|le|o|e|

Path [Octet 1, Line 7]

Path [Octet 2, Line 0]

Path [Octet 2, Line 1]

Path [Octet 2, Line 2]

o|eo|

Path [Octet 2, Line 3]

[

| Internal Local T1 Data

Path [Octet 2, Line 4]
e

|[of

lo|

[®|M8398

| Internal Local T1 Data

Path [Octet 2, Line 5]
°

M8398

Internal Local T1 Data

Path [Octet 2, Line 6]
°

e|e|e|

M8398

| Internal Local T1 Data

Path [Octet 2, Line 7]
°

ole

Diagnostic LEDs

M8398 | Manual T1 Connector Data

Path [Octet O, Line 0]

MKV84-0658

4-10

Table 4-1

M8398 Coded LED Display (Cont)

Diagnostic LEDs

Function Tested

M8398 LEDs

6/5(4]312{110]

FRU

Description

Hex | Decimal | Octal

o | M8398 | Manual T1 Connector Data

131

MS8398 | Manual T1 Connector Data

132

o|e|

M8398 | Manual T1 Connector Data

133

eojole

M8398 | Manual T1 Connector Data

134

eolole

o | M8398 | Manual T1 Connector Data

5D | 93

135

|o|o|0]|e

MS8398 | Manual T1 Connector Data

S5E

136

(o|o|o|o]|®]

M8398 | Manual T1 Connector Data

137

el|®

M8398 | Manual T1 Connector Data

140

e | M8398 | Manual T1 Connector Data

141

oi®

)

ole

°®

Path [Octet 0, Line 1]

Path [Octet 0, Line 2}

Path [Octet 0, Line 3]

Path [Octet 0, Line 4]

Path [Octet 0, Line 5]

Path [Octet O, Line 6]

Path [Octet O, Line 7]

Path [Octet 1, Line 0]

Path [Octet 1, Line 1]

ole

M8398 | Manual T1 Connector Data

142

el®

e|{e®| M8398 | Manual T1 Connector Data

143

Path [Octet 1, Line 2}

Path [Octet 1, Line 3]

ele

)

M8398 | Manual T1 Connector Data

100

144

ole®

o | M8398 | Manual T1 Connector Data

101

145

MS8398 | Manual T1 Connector Data

102

146

ofo

ole|e| M8398 | Manual T1 Connector Data

103

147

Path [Octet 1, Line 4]

Path [Octet 1, Line 5]

Path [Octet 1, Line 6]

Path [Octet 1, Line 7]

MKV84-0659

4-11

Table 4-1

MS8398 LEDs

M8398 Coded LED Display (Cont)

Function Tested

6(5}41312]1{0]

FRU

eole

MS8398 | Manual T1 Connector Data

Description

e | M8398

105

151

106

152

| Manual T1 Connector Data

107

153

| Manual T1 Connector Data

108

154

| Manual T1 Connector Data

109

155

| ManuaT1
l Connector Data

110

156

| Manual T1 Connector Data

111

157

- NOT USED -

112

160

- NOT USED
-

113

161

| Manual T1 Connector Data

M8398 | Manual T1 Connector Data

Path [Octet 2, Line 2]

ole

e e | M8398

Path [Octet 2, Line 3]

olo

MB8398

150

Path [Octet 2, Line 1]
olo

Hex | Decimal | Octal

104

Path [Octet 2, Line 0]

ole

Diagnostic LEDs

Path [Octet 2, Line 4]
o0

® | M8398

Path [Octet 2, Line 5]

ole

ele|o

M8398

Path [Octet 2, Line 6]

ejeele®|

MB398

Path [Octet 2, Line 7]

eole
ole

ole|e

- NOT USED -

114

162

eole|e

-NOT USED -

115

163

- NOT USED -

116

164

- NOT USED -

117

165

olole

°®

eleje

°®

ole

- NOT USED -

118

166

ole|e

- NOT USED -

119

167

-NOT USED -

120

170

- NOT USED
-

121

171

- NOT USED -

122

172

eolole

|o@

eolelole

olele

olole

MKV84-0661

4-12

Table 4-1

M8398 Coded LED Display (Cont)

Diagnostic LEDs

Function Tested

M8398 LEDs

Description

Hex | Decimal | Octal

- NOT USED
-

7B | 123

173

oleolojole

- NOT USED

7C | 124

174

elejo|o]|e

- NOT USED-

D | 125

175

oleojo|o|0]0

- NOT USED

TE | 126

176

H3014 Self-Test Failure

TF | 127

1717

615]413(2]1
olo(o|o|

FRU

olo|o|o |00

H3014
Processor

H3014

Internal EIA Data Path

[Octet O, Line O]

128

200

H3014

Internal EIA Data Path

129

201

()

H3014

Internal EIA Data Path

[Octet O, Line 2]

130

202

H3014
Processor|

Internal EIA Data Path
[Octet O, Line 3]

131

203

H3014
Processor|

Internal EIA Data Path
[Octet O, Line 4]

132

204

H3014
Processor|

Internal EIA Data Path
[Octet O, Line 5}

133

205

H3014

Processor | [Octet O, Line 6}

Internal EIA Data Path

134

206

ole

Internal EIA Data Path
H3014
Processor | [Octet O, Line 7]

135

207

Processor|
Processor|

Processor|

[Octet O, Line 1]

H3014

Processor | [Octet 1, Line 0]

136

210

]

Internal EIA Data Path
H3014
Processor | [Octet 1, Line 1]

137

211

Internal EIA Data Path
H3014
Processor | [Octet 1, Line 2]

8A | 138

212

Internal EIA Data Path

MKV84-0660

4-13

Table 4-1

M8398 LEDs

6(51413(2]1

M8398 Coded LED Display (Cont)

Function Tested

FRU

Description

139

213

H3014

140

214

Internal EIA Data Path

8D | 141

215

Internal EIA Data Path

| 142

216

Internal EIA Data Path

| 143

217

Internal EIA Data Path

144

220

Internal EIA Data Path
Processor | [Octet 2, Line 1]

145

221

H3014

Internal EIA Data Path

146

222

Internal EIA Data Path

147

223

148

224

H3014

Internal EIA Data Path

Processor | [Octet 1, Line 5]
olole

H3014

Processor | [Octet 1, Line 6]
elele

H3014

Processor | [Octet 1, Line 7]
o

H3014

Processor | [Octet 2, Line 0]
°

H3014

)

Processor | [Octet 2, Line 2]
°

H3014

Processor | [Octet 2, Line 3]
°

Hex | Decimal | Octal

H3014
Internal EIA Data Path
Processor | [Octet 1, Line 3]

Processor | [Octet 1, Line 4]
o

Diagnostic LEDs

H3014

Internal EIA Data Path

Processor | [Octet 2, Line 4]
o

H3014
Internal EIA Data Path
Processor | [Octet 2, Line 5]

149

225

)

H3014

150

226

151

227

Internal EIA Data Path

Processor | [Octet 2, Line 6]
o

|oje

H3014

Internal EIA Data Path

Processor | [Octet 2, Line 7]

MKV84-0662

4-14

Table 4-1

M8398 LEDS
6|5|41312]1|0{ FRU
ole

M8398 Coded LED Display (Cont)

Diagnostic LEDs

Function Tested
Description
— Illegal Codes —

Hex | Decimal

Octal

UBI or TIU Failure

152

230

[

[}

[]

(through)

[]

[)

255

371

olo|ojolo]e|e

— Illegal Codes —

UBI or TIU Failure

MKV84-0715

4-15

4.5 DIAGNOSTICS
This section describes the use of DMZ32 diagnostics. The DMZ32 is supported

by both Level 3 and Level
2R diagnostics. The Level 3 diagnostic is a standalone diagnostic that runs under
the Diagnostic Supervisor
using direct I/O. EVDAE is the only Level 3 diagnostic. The purpose
of EVDAE is to verify the
functionality of the DMZ32.
Various loopback methods are used to isolate the fault to a specific
component of the DMZ32. The
different loopback methods used during the running of the EVDAE are either
software controlled or
manually inserted.

The Level 2R diagnostic enables Field Service to fault isolate to the option level while
running under VMS.
The Level 2R diagnostic, run under the Diagnostic Supervisor, uses the QIO interface
of the VMS device
driver. EVDAF is the only Level 2R diagnostic.
4.6 DIAGNOSTIC SUPERVISOR
Both Level 3 and Level 2R diagnostics run under the Diagnostic Supervisor
. Loading and using the
Diagnostic Supervisor are described in both the V.AX-11 /730 Diagnostic System
Overview Manual (EXDS730-UG) and the VAX Diagnostic System User’s Guide (EK-VX11D-UG)
4.7 DMZ32 CSR ADDRESS AND VECTOR ADDRESS
The DMZ32 CSR address (760440) is used only as an example address in
the following diagnostic
procedures. The actual address depends on the switch setting of E-53 on
the M8398 module. The vector is
software controlled. (Refer to Appendix A for floating device addresses
and vectors.)
4.8 MANUALLY CONTROLLED (HARDWARE) LOOPBACK METHOD
S
There are five manually controlled loopback methods that are used in running
the DMZ32 diagnostics.
These loopbacks require that a turnaround device be placed on the line(s) or
that the local modem be
manually put in a loopback mode of operation. The manually controlled loopback
methods used with the
DMZ32 are as follows:

Local T1 loopback (H3028),
Remote T1 loopback (H3027),
Single line EIA loopback (H3248),

Staggered multiline loopback (29-24929-00), and
Manual analog modem loopback.

4-16

4.8.1
Local T1 Loopback (H3028)
The local T1 loopback test is conducted by Field Service personnel using the H3028 turnaround connector
(Figure 4-5). The H3028 turnaround connector is inserted at J1 on the M8398 module. When the H3028
is inserted in J1 of the M8398 module, the T1 circuitry up to and including the analog I/O of the M8398
module is checked for proper operation.
This loopback is supported by EVDAE with event flag 3 set.

J1 PIN NUMBER

SIGNAL NAME

= 0oOoONOOOPWN—

DATA IN A (+) ——
DATA
IN B (—)

SIGNAL GROUND
UNUSED
UNUSED
UNUSED
UNUSED

UNUSED

DATA OUT A (+) —

DATA OUT B (—) ——

|§

BC22N-10

BC18L-15

29-2429-00

B = LOOPBACK
B = VERIFIED GOOD
MKV84-0504

Figure 4-5

H3028 Loopback Connector

4-17

4.8.2 Remote T1 Loopback (H3027)
The remote T1 loopback test is conducted by Field Service personnel using the H3027 turnaround
connector (Figure 4-6). The H3027 turnaround connector is inserted at either the 1/O bulkhead or at the
distribution panel end of the interconnecting cable between the M8398 module and the distribution
panel.
When inserted into the I/O panel insert connector (BC22N-10), the M8398 module and the internal
interconnecting T1 cable are checked for proper operation. When the turnaround connector is connected
to the distribution panel end of the T1 cable, the T1 cable (BC18L-15) is also checked for proper
operation.

This loopback is supported by EVDAE with event flag 3 set.

NOTE
This loopback can be used ONLY on a remote
installation up to a maximum distance of 762 m

(2500 ft).

H3027

SIGNAL NAME (REFERENCED TO H3027)

0O ~NOOO
P~ WN-=

PIN NUMBER

DATA OUT A (+ ———
CHASSIS

H3027

UNUSED
UNUSED
UNUSED

UNUSED

—

CHASSIS GROUND

DATA OUT B (—)——>—

apwWN-=0

GROUND

DATA IN A (+)

UNUSED

DATA IN B ()

———=

UNUSED

SIGNAL GROUND
UNUSED
UNUSED

H3028

H3014

BC22N-10

[”DDBEED}E
|

H3027

29-24929-00

B = LoOPBACK

[ = VERIFIED GOOD

MKV84-0505

Figure 4-6

H3027 Loopback Connector

4-18

4.8.3 Single Line EIA Loopback (H3248)
The single line EIA loopback test is conducted by Field Service personnel using the H3248 turnaround
connector (Figure 4-7), which is supplied in the CD Kit (A2-WQO707-10). The H3248 turnaround connector is inserted either at the H3014 RS-232-C connector or at the EIA cable, which connects to the modem.
When the H3248 is connected to the suspect channel (directly on the remote distribution panel), the
connector, line drivers, receive/latches, and all modem signals for that channel are checked for proper
operation. When the H3248 turnaround connector is connected to the EIA cable associated with the
channel, the EIA cable is also checked for proper operation.
This loopback is supported by EVDAE with event flag 5 set and EVDAF loopback type 5 selected in the
attach sequence.

TX DATA

RX DATA

RTS

CTS

CARRIER

LOCAL LOOP

<
s

SIGNAL NAME

H3248

REAR VIEW

FRONT VIEW

H3248 SINGLE LINE
TEST CONNECTOR

(PLUGS INTO J4-J12 OR

TEST MODE

DATA SIGNALING RATE SELECT

RING

END OF A BC22 CABLE

YYYYY

BC22N-10

H3248

BC18L-15

29-24929-00

B = LOOPBACK
[ = VERIFIED GOOD

MKV84-0506

Figure 4-7

H3248 Turnaround Connector

4-19

4.8.4 Staggered Multiline Loopback (29-24929-00)
The staggered multiline loopback test is conducted by Field Service personnel using six (6) 29-24929-00

(Figure 4-8) turnaround connectors, which are supplied in the CD Kit (A2-WO707-10). The 29-24929-00

turnaround connectors are attached to the distribution panel so that all connectors have
a loopback
attached. When connected, this test checks for line interaction and asynchronous line problems.
This loopback is supported by EVDAE with event flag 6 set. Tests 35 through 41 of EVDAE are

this connector is used.

29-24929-00

TX DATA (n)

RX DTA (n+1)

RST (n)

CTS (n+1), CARRIER (n+1)

DTR (n)

DSR (n+1)

LOCAL LOOP (n)

TEST MODE (n+1)

DATA RATE SELECT (n)

RING (n+1)

TX DATA (n+1)

RX DATA (n)

RTS (n+1)

CTS (n), CARRIER (n)

DTR (n+1)

DSR (n)

LOCAL LOOP (n+1)

DATA RATE SELECT (n+1)

——m8M8M

‘

(FRONT VIEW)

TEST MODE (n)

RING (n)

(BACK VIEW)

(n) WHERE n EQUALS THE LINE NUMBER.

H3028
BC22N-10

H3027

H3248

BC18L-15

29-24929-00

B = L.oopPBACK
[ = vERIFIED GOOD

MKV84-0507

Figure 4-8

29-24929-00 Staggered Loopback Connector

4-20

run when

4.8.5 Manual Analog Modem Loopback
The manual analog modem loopback test is conducted by

Field Service personnel by pressing the analog
loopback button (AL) on the modem (Figure 4-9). This loopbac
k verifies that data can be sent to and
received from the local modem.
This loopback is supported by EVDAE with event flag 7 set,

the attach sequence.

H3028

and EVDAF with loopback type 7 selected in

H3014

F L

BC22N-10

H3027

= e

BC18L-15

lof

29-24929-00

B = LOOPBACK

[ = VERIFIED GOOD
MKV84-0508

Figure 4-9

Manual Analog Modem Loopback

4-21

4.9 SOFTWARE LOOPBACK METHODS
There are many loopback methods that can be used in running the DMZ32 diagnostics. The software
loopback methods that are used with the DMZ32 are as follows:

Shared RAM loopback,
Local trunk loopback,
Internal single-line loopback, and
Programmable local modem loopback.
4.9.1
Shared RAM Loopback
The shared RAM loopback loops data and modem signals on an individual line basis without affecting

other lines. This also applies to modem signals at the shared RAM interface between the UBI and TIU
sections of the UNIBUS module. (Refer to Figure 4-10.)
This loopback is used under EVDAE only. The shared RAM loopback is invoked by attaching loopback
type 1 or by setting the Diagnostic Supervisor event flag 1.

POWER
SUPPLY

MODEM

INTERFACE

CONTROL

VAX UNIBUS

1.544

MBPS

INTERFACE

EIA

DRIVERS/

ASYNC

RECEIVERS
NN
WN—

DEMUX

\}k

LINES

LINK

M8398

CABLE

H3014

-= LOOPBACK

B= veriFieD Goop
MKV84-0471

Figure 4-10

Shared RAM Loopback Test

4.9.2 Local Trunk Loopback
The local trunk loopback loops data back before the T1 driver/receiver on the M8398 module. (Refer to
Figure 4-11.)
This loopback is supported by EVDAE and the microdiagnostics. The local trunk loopback is invoked by
attaching loopback type 2 or by setting Diagnostic Supervisor event flag 2.

POWER

SUPPLY
MODEM

L 0

CONTROL

= ?

f=—=.2

:V'Ig‘;:

11— \nrereace [

x
<
>

LINK

EIA

ORIVERS/

>ASYNC

RECEIVERS

LINES

5
L
99
53

DEMUX

B >

M8398

CABLE

H3014

-= LOOPBACK

-= VERIFIED GOOD
MKV84-0471

Figure 4-11

Local Trunk Loopback Test

4-23

4.9.3

Internal Single-line or All Lines Loopback

The single-line loopback is associated with the channel being tested. (Refer to Figure 4-12.) A message is
sent, one line at a time, on all lines selected. EIA latches, drivers, and receivers are not tested with this
loopback.
This loopback is used by EVDAE with event flag 4 set, and EVDAF with loopback type 4 selected in the
attach sequence.

POWER

SUPPLY

0 )
1
2

0
2

o
5

:V'I:‘;;

EIA

DRIVERS/

) ASYNC

EIA

X
x

LNk

RECEIVERS

LINES

21
— 22
— 23

M8398
~"

CABLE
~"

H3014
~"

[= LoopeAck

B
- veriFieD oo
.

MKV84-0471

Figure 4-12

Single Line Loopback Test

4-24

4.9.4

Programmable Local Modem Loopback

NOTE
This loopback works only with a modem that supports programmable local loopback.

The programmable local modem loopback verifies the DMZ32 modem

signals and will be executed if the

programmable local modem loopback is selected in the superviso
r attach sequence and if the modem

control is available. (Refer to Figure 4-13.)

This loopback is supported by EVDAE with event flag 8 set, and EVDAF
the attach sequence.

with loopback type 8 selected in

2\
Y [mooem]
2 r

?ASYNC

LINK

e
21
22
23

M8398

CABLE

H3014

B
= Loopeack

-=VERIFIED GOOD
MKV84-0509

Figure 4-13

Analog Modem Loopback Test

4-25

4.10 DMZ32 LEVEL 3 (EVDAE) DIAGNOSTIC
There is only one Level 3 Diagnostic used to support the DMZ32, EVDAE. This diagnostic operates under
the VAX Diagnostic Supervisor (VDS).
4.10.1
EVDAE Hardware Prerequisites
The following must be functional before the Level 3 diagnostic may be used:
e

e
e
4.10.2

VAX-11 CPU,
Memory (512K bytes), and
UNIBUS adapter.

EVDAE Software Diagnostic Requirements

The Level 3 Diagnostic (EVDAE) requires VAX Diagnostic Supervisor 7.0 or later. The different VAX

Diagnostic Supervisors are as follows:
e

VAX-11/725/730 - ENSAA,

VAX-11/750 - ECSAA, and

VAX-11/780/782 - ESSAA.

4.10.3 EVDAE Diagnostic Description
EVDAE is an aid to Field Service personnel in verifying proper system operation. EVDAE is also used to

aid in troubleshooting the DMZ32. A summary of the test performed by EVDAE is listed in Table 4-2.
The manual intervention test (test 42) verifies that a 256-byte block, or multiple, of data can be
transmitted error-free.

Table 4-2

EVDAE Diagnostic Summary

Test Number

Description

CSR Bit Test

Indirect Space Access

Master Reset Line Control & TX Modem Register

Master Reset Octet CSR

Line Parameter

TX Silo Count Master Reset

UNIBUS INIT

Flush Silo Test

TX Ready, TX Enable, and TX Silo Count

4-26

Table 4-2

EVDAE Diagnostic Summary (Cont)

Test Number

Description

RX Data Available & Master Reset

Data Loopback

TX Enable/Disable

Character Length

Load Word Test

Transmit Interrupt

Receive Interrupt

Receive Interrupt at 64 Characters

Multiple Interrupt

NPR-Nonexistent Memory

DMA Transfer (NO AUTO - INC)

DMA Transfer (AUTO - INC)

DMA Transfer, Unaligned Address

DMA Transfer (Memory Extension)

Receive Silo Alarm Time-out

TX Break Test

Receive Silo Overrun

Pre-empt

Interaction Test

Dynamic Baud Rate

Dynamic Word Length

Dynamic Parity

TX & RX Modem Signals (H3248)

4-27

Table 4-2

EVDAE Diagnostic Summary (Cont)

Test Number

Description

Data Test — Single Line (H3248) or Modem

XON/XOFF (Staggered)

Framing Error (Staggered)

Parity Error (Staggered)

Auto Echo Mode (Staggered)

RX & TX Modem (Staggered)

Data Set Change (Staggered)

Split Baud Rate (Staggered)

Manual Section

NOTE
To perform Tests 35 through 41, 29-29249-00 loopback connectors must be installed on the distribution
panel.

4-28

4.10.4

Loading, Attaching, and Running EVDAE

After the Diagnostic Supervisor is loaded, the operating instructions in Figure 4-14 can be used for the
EVDAE diagnostic. The colored portions are what the user enters into the system.

EVDAE uses the standard VDS input sequence for attaching the UNIBUS adapter and loading the
program. The user must select the lines to be tested, the baud rate to be used in external testing, and the
loopback type.

On-line help may be obtained by typing HELP EVDAE.

DIAGNOSTIC SUPERVISOR.
DS>

ATT DW780 SBI

DWO 3

ZZ-EXSAA-T7.0-YYY
4

8-FEB-1983

09:40:14.80

;

FOR VAX/780 ATTACH THE UBA

ON THE

SBI

HUB

DWO

DS>

ATT DW73@ HUB

DWO

DS>

LOAD EVDAE

DS>

ATT DMZ32

-e

~-e

FOR VAX/730 TESTING

LOAD THE DMZ32

-e

ATTACH THE

LINK?

DWO

ATT DW75¢

FOR

THE

DEVICE NAME?

TZA

;

THE GENERIC NAME FOR DMZ32

DS>

VAX/7506

TESTING

DEVICE

BR?

TEST LINES (OCTETO)? 377

LINKED

TO THE

UBA

UNIT

" THE CSR ADRS IS 760440
(RANGE=760000-777776)

-e

VECTOR? 300

DMZ32

VECTOR ADRS IS

-s

wme

CSR? 760440

DMZ32

DIAGNOSTIC

300

;

LINES 9-7 OF OCTET ¢ WILL BE TESTED

INTERRUPT LEVEL

(RANGE=300-776)
IS

(RANGE=5-6)

LEVEL 3 ONLY - TEST LINES(OCTET1)? 1
;

LINE

LEVEL 3 ONLY - TEST LINES(OCTET2)?

TESTED

BAUD RATE TO BE USED IN TEST 34

TMo

wo
we

2 WILL BE

TEST LINES

WM
Wme
W
e

Figure 4-14

7 OF OCTET

300

200

(OCTAL BIT MAP OF DESIRED
TEST, BIT@ = LINE @,
BIT1 = LINE 1, ETC.
RANGE = @006-377)
EXAMPLE: TEST LINES? 123

wNE

BAUD RATE?

LINE

1 WILL BE TESTED

;

¢ OF OCTET

SIX,

MANUAL TEST.
BAUD RATES THAT

ARE,

56,

75,

FOUR,

CAN BE

11,

135,

600, 1200, 1800, 2000,
4800, 9600, 19200

LINES

ONE AND ZERO

SELECT

1560,

24040,

304,

Loading, Attaching, and Running EVDAE (Sheet 1 of 2)

4-29

we
ws
%o
we

DS>

SELECT

DS>

START

TZA

Figure 4-14

nwawaan

YES

W~V

LOCAL
MANUAL

CONTROL?

MODEM

INTERNAL
SHARED

w NS

LOOPBACK TYPE?

-e

(AUTO)

RAM

TRUNK

CONNECTION

INTERNAL LINE
SINGLE

LINE

STAGGERED
LOCAL

H3248

MODE

(MANUAL

PROGRAMMABLE

LOCAL

= H3014 CONTAINS
(EXPANSION MODULE)
NO = DATA ONLY
SELECT

CONNECTOR

SPECIFIC

DMZ32

ANALOG

LOOPBACK)

MODEM

OPTION

RUN.

Loading, Attaching, and Running EVDAE (Sheet 2 of 2)

4-30

EVDAE Event Flags

4.10.5

The loopback type is also selected by setting the appropriate event flag. Only ONE event flag is to be set
at a time. The event flag set overrides the loopback type selected during the attach sequence. The colored
portions are what the user enters into the system.
To use a specific loopback, type the following:

DS> CLEAR EVENT ALL
DS> SET EVENT X

: CLEAR PREVIOUS LOOPBACK, IF ANY
: X = EVENT FLAG = LOOPBACK TYPE
1 = SHARED RAM
2 = LOCAL TRUNK

3 = MANUAL T1 CONNECTOR (H3027
or H3028)
4 = INTERNAL LINE

5 = SINGLE LINE (H3248)
6 = STAGGERED LOOPBACK
7 = LOCAL MODEM (MANUAL)

8 = LOCAL MODEM (PROGRAMMABLE)

DMZ32 LEVEL 2R (EVDAF) DIAGNOSTIC

4.11

EVDAF can run only with VAX/VMS Operating System Version 4.0 or later, the latest DMZ32 driver,

and the VAX Diagnostic Supervisor Version 7.0 or later.
4.11.1

EVDAF Hardware Prerequisites

The following must be functional before the Level 2R diagnostic may be used:
e

DW780, DW750, or DW730 fully tested without errors,

VAX family of processors with at least the minimum VMS configuration, and

Modem (optional).

4.11.2

EVDAF Software Diagnostic Requirements

This diagnostic is intended to test the DMZ32 product that is attached to a VAX family of processors. The
host VAX system must have the following:

¢
e

Minimum memory required by VMS operating system, and
One (1) DMZ32 module with H3014 distribution panel.

The VAX Diagnostic Supervisors are as follows:
e
e
e

VAX-11/725/730 - ENSAA,
VAX-11/750 - ECSAA, and
VAX-11/780/782 - ESSAA.

4-31

4.11.3 EVDAF Diagnostic Description
This diagnostic is an aid to Field Service personnel in the following:
®

Verification of customer installation, and
Service calls: device isolation and verification.

A summary of the tests performed by EVDAF are listed in Table 4-3.

Table 4-3

Test Number
|

EVDAF Diagnostic Summary

Description
_

Single Line Internal EIA Data Loopback

Single Line Internal Data Loopback (DMA)

Modem Signals Loopback (H3248)

External Data Loopback

4.11.4 Loading, Attaching, and Running EVDAF
The DMZ32 architecture is similar to the DMF32; therefore, many programm
DMZ32 appears very much like the async portion of three (3) DMF32s.

there are three DMF32s on the UNIBUS conductor.

ing similarities exist. The
CSRs and vectors will appear as if

The program treats each octet selected as though it is a separate device.

For example:

When TZA alone is selected, only the first eight lines (octet) of the

When TZA and TZB are selected, the program tests TZA (lines 0-7),
then the program starts
over and tests TZB (lines 8-15). The program treats the two octets
as though they were two
separate devices. Because of this, the program must run twice.

When TZA, TZB, and TZC are selected, the program runs TZA first,

last.
®

DMZ32 are tested.

TZB second, and TZC

The attach sequence must be performed for each octet. (Refer to Figure

4-32

4-15.)

On-line help may be obtained by typing HELP EVDAF.

Before EVDAF will run, the following must be performed:

: START SUPERVISOR (11/780/782=ESSAA,

$ RUN ENSAA

: 11/750=ECSAA, 11/725/730=ENSAA

After the Diagnostic Supervisor is loaded, the operating instruction in Figure 4-15 can be used for the
EVDAF diagnostic.

The colored portions of Figure 4-15 are what the user enters into the system.
9-0CT-1983 ©09:40:14.80
ZZ-ENSAA-6.10-YYY
DIAGNOSTIC SUPERVISOR.
; ATTACH THE UBA TO THE SBI, VAX/788
DS> ATT DW780 SBI DW@ 5 7
OR

DS> ATT DW75¢ HUB DW@
OR

DS> ATT DW73¢0 HUB DW@

ATTACH THE 1ST OCTET
THE OPTION IS LINKED TO THE UBA

DEVICE LINK? DW@

THE CSR ADRS IS 760440
(RANGE=760000-777776)

VECTOR ADRS

wme
e

760440

; THE OPTION IS NAMED TZA

DEVICE NAME? TZA

VECTOR?

LOAD THE DIAGNOSTIC

-e

DS> ATT DMZ32

300

BR? 5
(OCTET @)? 377

IS 300

LINES @#-7 IN OCTET @ WILL BE TESTED
(OCTET BIT MAP OF DESIRED LINES TO
BIT@ = LINE
RANGE

WME

TEST,

BIT1 = LINE

(RANGE=300-776)

BR INTERRUPT LEVEL IS 5 (RANGE=5-6)

WME

WMo

TEST LINES

CSR?

; FOR VAX/730 TESTING
-e

DS> LOAD EVDAF

: FOR VAX/758 TESTING

ETC.

000-377)

ACTIVE LINES? 123

EXAMPLE:

TEST LINES

SIX,

ONE AND ZERO

FOUR,

LEVEL 3 ONLY - TEST LINES (OCTET 1) 2?2

; Applies only to Level 3

LEVEL 3 ONLY - TEST LINES (OCTET 2) ?

; Applies only to Level 3

-e

BAUD RATE? 9600

LOOPBACK TYPE?

600,

BAUD RATES THAT CAN BE SELECTED
75,

1200,

9600,

114,

18006,

135,

2000,

150,

3049,

2400, 48040,

195200

;

7 = LOCAL MOCEM IN ANALOG LOOP

we
-e

Figure 4-15

50,

LOOPBACK TYPES ARE:
4 = LOCAL LINE (EIA)

;

TESTS.

ARE,

;

MODEM CONTROL?

BAUD RATE TO BE USED IN EXTERNAL DATA

= H3248 TURNAROUND

8 = LOCAL MODEM

(INTERNAL LOOPBACK)

(PROGRAMMABLE LOOPBACK)

DOES THE DEVICE HAVE MODEM CONTROL,
YES

NO.

Loading, Attaching, and Running EVDAF (Sheet 1 of 2)

4-33

ATT

DW@

DEVICE

NAME?

TZB

CSR?

THE

OPTION

LINKED

THE

OPTION

NAMED

TZB

THE

TEST

LINES

(OCTET

9)?

-e

BR?

300

VECTOR ADRS

VECTOR?

THE

2ND

OCTET
THE

UBA

CSR ADRS IS 760449
(RANGE=760000-777776)

“e

760440

LINK?

-e

DEVICE

ATTACH

-e

DMZ32

DS>

INTERRUPT

300

LEVEL

(RANGE=300-776)
IS

(RANGE=5-6)

377

LEVEL

ONLY

TEST

LINES

(OCTET

1)?

;

Applies

only

Level

LEVEL

ONLY

TEST

LINES

(OCTET

2)?

;

Applies

only

Level

RATE?

LOOPBACK

CONTROL?

ATT

4
Y

DMZ32

DEVICE

LINK?

DW@

DEVICE

NAME?

TZC

CSR?

ATTACH
THE

OPTION

LINKED

THE

OPTION

NAMED

TZC

THE

VECTOR?
BR?

3¢¢

TEST

LINES

(OCTET

@9)?

THE

3RD

OCTET
THE

UBA

SCR ADRS IS 760440
(RANGE=760000-777776)

¢+

VECTOR

760440

-e

DS>

TYPE?

-e

MODE

9600

BAUD

ADRS

INTERRUPT

300

LEVEL

(RANGE=300-776)
IS

(RANGE=5-6)

377

LEVEL

ONLY

TEST

LINES

(OCTET

1)?

;

Applies

only

Level

LEVEL

ONLY

TEST

LINES

(OCTET

2)?

;

Applies

only

Level

BAUD

RATE?

LOOPBACK

MODEM

9680

TYPE?

CONTROL?

DS>

SEL

TzA

SELECTS

LINES

@6-7

DS>

SEL

TZB

SELECTS

LINES

8-15

DS>

SEL

TzC

SELECTS

LINES

16-23

DS>

START

Figure 4-15

Loading, Attaching, and Running EVDAF (Sheet 2 of 2)

4-34

H3014 FRONT PANEL INDICATORS

4.12

There are three (3) LED indicators on the H3014 distribution panel. These LED indicators are located
directly above the T1 connector, as viewed from the connector side of the panel. (Refer to Figure 4-16.)
These indicators are as follows:
e
e

Power (PWR),
Sync (SYNC), and

Trunk Quality (TRNK QLTY).

The three LEDs display information that indicates the status of the H3014. (Refer to Table 4-4 for the
different indication combinations.)

POWER (PWR) INDICATOR

SYNC (SYNC) INDICATOR

/TRUNK QUALITY (TRNK QLTY) INDICATOR

UUL

=
-

MKV84-0510

Figure 4-16

4.12.1

H3014 LED Indicators

Power Indicator (PWR)

The PWR LED indicator provides an on-line indication that the three power supply outputs (+12 V, —12
V, and +5 V) are good. If any of the three power supplies fail, the PWR indicator will go out.
Refer to Table 4-4 for the coded display indications.
4.12.2

Sync Indicator (SYNC)

The SYNC LED, when ON, indicates the presence of T1 synchronization.
Refer to Table 4-4 for the coded display indications.
4.12.3

Trunk Quality Indicator (TRNK QLTY)

When the T1 circuitry in the H3014 detects a bipolar violation, the TRNK QLTY LED will be turned
OFF for approximately one (1) second.

4-35

Table 4-4

H3014 Front Panel Indicators

PWR

SYNC

TRNK

Signal Conditions

Probable Cause

Power OK

‘Normal operation

T1 link synchro-

nized
No bipolar violations

OFF

Loss of T1 synchronization

Refer to microdiagnostic
status LEDs on M8398 for
failing device

BLINKING

Two masters tied
together

Wrong jumper settings on
M8398 or H3014 processor
module

OFF

Loss of incoming
T1 signal

T1 cable disconnected
T1 cable broken
T1 cable installed backwards
on M8398 module

OFF OFF

OFF

Power loss

Bad H3014 ac power fuse
Bad H3014 power supply

4.13 H3014 REMOVAL/REPLACEMENT PROCEDURES
This section contains the removal and replacement procedures for all field
the H3014 distribution panel.

replaceable units contained in

The tools required are:

®
e

7/64 Allen wrench, and
Small Phillips screwdriver.
WARNING
Before performing these removal or replacement
procedures, make sure that the H3014 is turned
OFF and the power cord is removed from the power
controller.

4-36

4.13.1

H3014
.- Power Supply Assembly Removal/Replacement (29-24799-00)
Open the VAX cabinet using a 7/64 Allen wrench.

‘Disconnect input power cable from the H3014 power receptacle. (Refer to Figure 4 -17.)
Loosen the two (2) 1\4 turn Phillips head lock fasteners on the H3014 distribution panel. (Refer
‘to Figure 4-17.)

Open the rear cover of the H3014 distribution panel.
Disconnect the power connector that is connected to the fan assembly. (Refer to Figure 4-18.)
Disconnect the power connectors from the processor module and the expansion module. (Refer
to Figure 4-18.)
Remove the processor. module. (Refer to Figure 4-18.)
Lift the power supply assembly about 12.7 mm (1/2 inch) and pull the assembly out of the
H3014 chassis. (Refer to Figure 4-18).
Using a 3/8 nut driver, disconnect the CHASSIS GND connection from the power supply
chassis.
10.

To replace the power supply assembly, reverse Steps 1 through 9.

)
S
E
C
A
L
P
Z
/(

¥4 TURN LOCK FASTENERS

\INPUT

POWER CONNECTOR
MKV84-0511

‘Figure 4-17

1/4 Turn Lock Fasteners

4-37

EXPANSION MODULE POWER CONNECTOR

FAN POWER CONNECTOR

PROCESSOR MODULE POWER CONNECTOR

[

bbbt
ded ettt

EXPANSION

TSN

bl L

A L

L L

o]l

—

PROCESSOR

‘

LU
L

I I

TMM

POWER SUPPLY ASSEMBLY
MKV84-0512

Figure 4-18

H3014 Power Supply Location

4-38

4.13.2

H3014 Fan Assembly Removal/Replacement (29-24800-00)

1.:-

Open the VAX cabinet using a 7/64 Allen wrench.

2. -~ Disconnect the input power cable from the H3014 power receptacle (Figure 4-17).
3.

Loosen the two 1/4 turn Phillips head lock fasteners on the H3014 distribution panel. (Refer to

Figure 4-17.)
4.

Open the rear cover of the H3014 distribution panel.

Disconnect the power connector that is connected to the fan assembly. (Refer to Figure 4-19.)

Slide the fan assembly out of the H3014 chassis by pullmg the fan mounting bracket toward the
rear of the chassis (Figure 4-20).

CAUTION
Make certain that the fanis installed so that the air
flows inward.
To replace the fan assembly, reverse Steps 1 through 6.

FAN POWER CONNECTOR

[

[}.

TM51

WTM\J

P1
AG

EXPANSION

PROCESSOR
—

=~ —

[

—

wheehavhtdteheidnadfnhatbodrirmralmietedetadedadwdbbedebddebe
L L L E T
L L
TR D L
P T RN
I Y
I
N
L
L
I T T I T I I Y I I
T T
Y

MKVv84-0513

Figure 4-19

H3014 Fan Assembly Location

4-39

\ FAN MOUNTING
||

BRACKET

MKV84-0526

Figure 4-20

Fan Mounting Bracket Assembly

4-40

H3014 Expansion Module Remove/Replacement (29-24798-00)
Open the VAX cabinet using a 7/64 Allen wrench.

—

4.13.3

Disconnect the input power cable from the H3014 power receptacle (Figure 4-17).

Loosen the two 1/4 turn lock Phillips head fasteners on the H3014 distribution panel. (Refer to
Figure 4-17.)

Open the rear cover of the H3014 distribution panel.

Disconnect the expansion module and the processor module power connectors. (Refer to Figure
4-21.)

Grasp the two finger handles on both sides of the expansion module (Figure 4-21). Pull the
finger handles toward the back of the H3014 to physically remove the expansion module from
the backplane.

To replace the expansion module, reverse Steps 1 through 6.

EXPANSION MODULE
POWER CONNECTOR

PROCESSOR MODULE

FINGER HANDLE

POWER CONNECTOR

¥ [C]Wi

[ EXPANSION ]

FINGER HANDLE

PROCESSOR

R LI I LI

| Tal)

:
0]

ettty

i il

it i

tlid

il deilgllilglll

Il
MKV84-0515

Figure 4-21

H3014 Expansion Module Location

4-41

4.13.4

H3014 Processor Module Removal/Replacement (29-24797-00)

Open the VAX cabinet using a 7/64 Allen wrench.

Disconnect the input power cable from the H3014 power receptacle (Figure 4-17).

Loosen the two 1/4 turn lock Phillips head fasteners on the H3014 distribution panel. (Refer to
Figure 4-17.)

Open the rear cover of the H3014 distribution panel.

Disconnect the processor module and expansion module power connectors. (Refer to Figure 4-

21.)

Grasp the two finger handles on both sides of the processor module (Figure 4-21). Pull the

finger handles toward the back of the H3014 to physically remove the processor module from
the backplane.

To replace the processor module, reverse Steps 1 through 6.

NOTE
Before placing the processor module back into the

H3014, verify the following jumpers and switch
settings.
®

Jumper between switch settings E6 and E7 is

always in place. (Refer to Figure 4-22.)
e

Jumper between switch settings E4 and ES is
always in place. (Refer to Figure 4-23.)

4-42

C133

C131

R39

Ub7 G U58 U59x EGE\

IjR44

R50

uso 't us1llus2

E6/E7

JUMPER

[Ifl
u8s3

S1 DIP

SWITCH

(NOT

USED)

\\ ;

U105 U106 U107 U108 U109

2l
U104

C178

TP11_TP13

MKV84-0516

Figure 4-22

Processor Module Clock Jumper and Dip Switch

4-43

—~

DS1 DS2 DS3

R10Lj:[:]jfl12

Ub4U55 Ub6

Rillig
us3

E3 E4 E5

TP6O [sTem]

0000 5

Cll

/‘u79

MASTER/SLAVE

—S

JUMPER

MKV84-0517

Figure 4-23

Processor Module Master/Slave Jumper

4-44

4.13.5

H3014 Chassis/Backplane Replacement
CAUTION
Two people are needed to perform this procedure.
One person must hold the chassis in place while the
other person removes the screws.

Disconnect all cables that are attached to the distribution panel.

Loosen the two 1/4 turn lock Phillips head fasteners on the H3014 distribution panel. (Refer to
Figure 4-17.)
Disconnect the input power connectors to the expansion module and the processor module.
(Refer to Figure 4-24.)
Remove the expansion module from the distribution panel. (Refer to Section 4.13.3.)

Remove the controller module from the distribution panel. (Refer to Section 4.13.4.)
Remove the power supply module from the distribution panel. (Refer to Section 4.13.1.)

Remove the fan assembly from the distribution panel. (Refer to Section 4.13.2.)
Remove the eighteen (18) Phillips screws that secure the mounting bracket of the distribution
panel to the chassis. (Refer to Figure 4-25.)
To replace the H3014 chassis/backplane, reverse Steps 1 through 8.

16T
_
WTM

Tl
1" n®

EXPANSION

al l

PROCESSOR

—

=
=
0]

MKV84-0523

Figure 4-24

Processor/Expansion Module Input Power

4-45

SECURING SCREWS FOR H3014

AN
f c—

\SECURING SCREWS FOR H3014/

MKV84-0518

Figure 4-25

Chassis/Backplane Securing Screws Location

4-46

APPENDIX A

FLOATING DEVICE
ADDRESSES AND VECTORS

A.1 FLOATING DEVICE ADDRESSES
UNIBUS addresses starting at 760010 and continuing through 763776 are designated as floating device
addresses. (See Figure A-1.) These are used as register addresses for communications (and other) devices
interfacing with VAX-11 computers.

A gap of 10g must be left between the last address of one device type and the first address of the next
device type. The first address of the next device type must start on a module 10g boundary. The gap of 10g
must also be left for devices that are not installed but are skipped over in the priority ranking list. Multiple
devices of the same type must be assigned continuous addresses. Reassignment of device types already in
the system may be required to make room for additional ones.

777 777

DIGITAL EQUIPMENT

CORPORATION

WORDS

(FIXED ADDRESSES)

770 000

DR11-C

767 777

{

WORDS

USER ADDRESSES

764 000
763 777

WORDS

FLOATING ADDRESSES

760 010

DIGITAL EQUIP CORP (DIAGNOSTICS) | 760 006
760 000

757 777

001 000
000 777

VECTORS

FLOATING VECTORS
000 300

000 277

TRAP & INTERRUPT

VECTORS

VECTORS
000 000

MK-2190

Figure A-1

UNIBUS Address Map

A-1

Table A-1 gives the floating CSR address assignments for UNIBUS and QBUS devices.

Table A-1

Floating CSR Address Assignments

Rank

Option

Decimal
Size

Option
Modulus

DJ11

DHI11

DQl11
DU11,DUV11

4
4

10
10

DUP11

LKIIA

DMC11/DMRI11

10
10
10

DZ11/DZV11,

9
10

DZS11,DZ32
KMCl11
LPP11

4
4
4

10
10
10

VMV21

VMV31

DWRT70

RL11,RLV11

(After first)

LPA11-K

(After first)

KW11-C

Reserved

RX11/RX211
RXVI11/RXV21

(DMC Before DMR)

(DZ11 Before DZ32)

(After first)
(RX11 Before RX211)

DR11-W

DR11-B

DMP11

DPVI11

ISB11

DMV11

DEUNA

(After first)

UDASO

(After first)

DMF32

KMSI11

VS100

30
31
32

Reserved
Reserved
Reserved

2
8
8

4
20
20

DMZ32

(After second)

(After first)

A.2

FLOATING VECTOR ADDRESSES
Vector addresses starting at 300 and proceeding upward to 777 are designated as floating vectors. These
are used for communications (and other) devices that interface with the VAX family of computers. Vector
size is determined by the device type.
Multiple devices of the same type would be assigned vectors sequentially. Table A-2 shows the floating
interrupt vector device assignment sequence.

Table A-2

Floating Interrupt Vector Device Assignment

Rank

,
Device

Decimal
Size

Octal
Modulus

1
|

DCl11
TUSS8

4
4

10
10

KL11

2
2

DL11-A
DL11-B

4
4

10
10

2
2

DLVI11-J
DLVI11,DLV1I1-F

16
4

10
10

DP11
DM11-A
DN11
DM11-BB/BA

4
4
2
2

10
10
4
4

2
4

4
10
10

4
5
6

7
8
9
10

DH11 Modem Control
DR11-A,DRV11-B
DR11-C,.DRV11
PA611
(Reader + Punch)

LPDI11

DTO7

DX11

14
14
14
15
16
17
17
18

DL11-C
DL11-D
DL11-E/DLV11-E
DJ11
DH11
GT40
VSVl
LPS11

4
4
4
4
4
8
8
12

10
10
10
10
10
10
10
10

DQl11

KW11-W, KWV11

DU11,DUV11

DUPI11

DV11 + Modem Control

LK11-A

DWUN

26
26

DMCIl11
DMRI11

4
4

10
10

(DMC Before DMR)

Table A-2

Floating Interrupt Vector Device Assignment (Cont)

Decimal
Rank

Device

Size

Octal

Modulus

DZ11/DZS11/DZV11,
DZ32

KMCl11

29
30

LPP11

VMV21

31
32

VMV3l1
VTVO0l1

4
4

10
10

(DZ11 Before DZ32)

DWR70

RL11/RLVI11

35
36
37

TS11,TU80O

(After the first)

LPA11-K
IP11/IP300

2
4

(After the first)

KWI11-C

RX11/RX211
RXVI11/RXV2l

DR11-W

DR11-B
DMP11

2
4

4
10

10
(After the first)

(After the first)

(RX11 Before RX211)
(After the first)

DPVI11

ML11

45
46
47
48
49

ISB11
DMV11
DEUNA
UDASO

(MASSBUS device)

4
4
2
2

10
10
4
4

(After the first)
(After the first)

KMSI11

PCL11-B

VS100

53
54

Reserved
Reserved

2
4

55
56
57
58

Reserved
Reserved
Reserved

4
10

DMZ32

DMF32

4
4

10
10
10
4

(After the first)

APPENDIX B
T1 CABLE SPECIFICATIONS

B.1
INTRODUCTION
This appendix gives information concerning the T1 link from the 2 X 4 1/O panel insert on the FCC
bulkhead frame to the T1 connector input of the remote distribution panel (H3014).
B.2 CABLE CONFIGURATION
The T1 cable (BC18L-xx or BC18M-xx) is connected between the 2 X 4 1/O panel insert on the FCC
bulkhead frame and the T1 connector input of the H3014. This T1 cable configuration defines the detail
requirements for a 4-conductor shielded cable assembly with a 15-position female D-subminiature connector at one end and a 15-position male D-subminiature connector at the other end.
A BC18L-15 is supplied with this option when purchased. Cables of other lengths may be fabricated using
the component specifications listed in Table B-1 or ordered directly from Digital Equipment Corporation.
(Refer to Table B-2.)
Table B-1

BC18L-xx Component Parts

DIGITAL

Part Number
12-10493-39

Description

Material & Finish

Crimp terminal pin

Brass, gold flash over nickel

(contact)

0.00005 minimum thickness on
entire contact with addition-

Accommodates AWG
20-24

al 0.00002 gold thickness on
mating end for length of
0.150/0.175 inch.

Carrier strip may not be gold plated.
NOTE
An AMPTM 90265-1 crimping tool is to be used
when inserting pin into the connector housing (1210493-57).
12-10493-41

Crimp terminal socket

Phosphor bronze gold flash

(contact)

over nickel 0.00005 minimum

Accommodates AWG
20-24

thickness on entire contact
with additional 0.00002 gold
minimum thickness on mating
end for length of 0.150/0.175 inch.

AMP is a trademark of AMP, Inc.

Table B-1

BCI18L-xx Component Parts (Cont)

DIGITAL
Part Number

Description

Material & Finish

NOTE
An AMPTM 90302-1 crimping tool is to be used
when inserting the socket into the connector housing
(12-10493-58).
12-10493-57

Connector housing

for 15 male (pins)
contacts with strain

Shell: Steel with tin

plating.

relief.

Insulator: Glass filled nylon, color
black.

12-10493-58

Connector housing

for 15 female

Shell: Steel with tin
plating.

(sockets) contacts
with strain relief.

Insulator: Glass filled nylon, color

black.

B-2

Table B-2

DIGITAL Cable Option Designations

T1 External PVC Cable BC18L

Cable Length

DIGITAL Option
Number

4.5 m (15 ft)
15.2 m (50 ft)
30.5 m (100 ft)
45.7 m (150 ft)
61.0 m (200 ft)
76.2 m (250 ft)
106.7 m (350 ft)
152.4 m (500 ft)
228.6 m (750 ft)
305.0 m (1000 ft)

BCI18L-15
BC18L-50
BC18L-A0
BCI18L-AS5
BC18L-B0
BC18L-B5
BC18L-C5
BC18L-EO0
BCI18L-H5
BC18LOLO

T1 External Plenum Cable BC1SM

4.5 m (15 ft)
15.2 m (50 ft)
30.5 m (100 ft)
45.7 m (150 ft)
61.0 m (200 ft)
106.7 m (350 ft)
152.4 m (500 ft)
228.6 m (750 ft)
305.0 m (1000 ft)

BC18M-15
BC18M-50
BC18M-A0
BC18M-AS
BC18M-B0
BC18M-C5
BC18M-EO
BC18M-HS5
BC18M-LO

B-3

B.3 T1 CONDUCTOR CHARACTERISTICS
The conductor that is used for the T1 link has the following characteristics.
Electrical Characteristics
Pairs:

Nominal impedance — 100 ohms
Nominal capacitance between conductors — 16 pF/ft

Nominal velocity of propagation — 66%
Nominal delay - 1.54 nanoseconds per ft
Capacitance unbalance (pair to pair) - 160 pF/1000 feet — maximum at 1000 Hz
Resistive unbalance (individual pair) — 1.20 ohms dc/1000 ft — maximum

Crosstalk — 70 dB/1000 ft minimum at 150 kHz far end

Insulation resistance — 10 X 106 ohms/1000 ft minimum at 200-500 Vdc for one (1) minute
Attenuation — 6.0 dB/1000 ft maximum at one (1) MHz

Shield coverage - 100%
Nominal shield dc resistance — 5.0 ohms/1000 ft
Nominal conductor dc resistance — 17.0 ohms/1000 ft
Maximum operating voltage — 150 Vac RMS

UL listed AWM style 2919

Physical Characteristics

Nominal weight/1000 ft — 40 lbs
Minimum bending radius — 3 inches

Temperature rating - —30 to 80°C
Shield type - foil and braid with 22 AWG drain wire
Maximum pulling tension — 64 lbs

Insulation material — polyethylene
Jacket material - PVC

‘Outside dimensions - .296 inches diameter
NOTE
Refer to Table B-3 for T1 cable color codes and
point-to-point wiring.

Table B-3

T1 Cable Schematic

Wire Table

Description

From

AWG Color

Connection

WHT/BLU

P1-9

P2-9

BLU

P1-1

P2-1

22
22
22

WHT/ORN
ORN
DRAIN

P1-1
P1-3
P1 Shell

P2-11
P2-3
P2 Shell

B-5

EDUCATIONAL SERVICES
DEVELOPMENT AND PUBLISHING

UPDATE NOTICE
DMZ32 User Guide

EK-DMZ32-UG-CNI1

July 1984

The original DMZ32 User Guide is wire-o bound and cannot
accommodate inserted update pages. This update
notice directs the document user in the changes that must be made
to correct errors. This update should be pasted
on the reverse of the front cover in order to maintain a record
of changes to the document.

CORRECTIONS
Page 3-6 - - Figure 3-2
[OCTET.CSR (READ/WRITE)]
15

Change bits 02 and 03 to agree with art shown.

[

TRANSMIT

! UNJSED

INTERRUPT

ENABLE

[

RECEII\/E 1C
MASTER

DATA

“

TRANSMITTER

Qa7

T LINE I

RESET

AVAILABLE ;

UNUSED BIT

READY

RECEIIVE

INDIRECT

INTERRUPT

REG

INDIRECT HEG
LINE NUMBER

NUMBER

ENABLE

TRANSMIT

DMA ERROR

Page 3-11 - - Figure 3-6

Change bits 02 and 03 to agree with art shown.

LINE

RECEIVE

MASTER

INDIRECT REG.

DATA

RESET

LINE NUMBER

AVAILABLE

RECEIVE

INTERRUPT

INDIRECT

REG. NUMBER

ENABLE

Page 4-22 — - Figure 4-10; Page 4-23 — - Figure 4-11;
Page 4-24 - — Figure 4-12; Page 4-25 — - Figure 4-13

BLUE —» : = VERIFIED GOOD

In the color key, change LOOPBACK to VERIFIED
GOOD and change VERIFIED GOOD to LOOPBACK.
(See diagram.)

ReD

— [

]

LOOPBACK