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XX-A5935-96-E

March 1982

87 pages

Original

6.3MB

Document:	T-11 Engineering Specification Update
Order Number:	XX-A5935-96
Revision:	E
Pages:	87
Original Filename:	http://bitsavers.org/pdf/dec/pdp11/t11/T11_Engineering_Specification_Rev_E_Mar82.pdf

OCR Text

+---+---+---+---+---+---+---+
Idlilgliltlalll
+---+---+---+---+---+---+---+
To: T-ll Spec. Distribution

SUBJECT:

I N T E R 0 F F ICE

ME M0

24 MAR 82
. {\C\ .:::bDate:
David Fors~the~.~.CV,
Fronl:
Dept:
Low Cost LSI
Ext:
225-5283
Decnet:
SNICKR::FORSYTHE
LoclMail Stop:
HL1-1/Q08

T-11 UPDATE

The T-11 is now a proven microprocessor which is being
manufactured in production auantities (over 3500 to date) and has
been successfull~ incorporated into man~ s~stem designs and
applications.
The T-11 has achieved Limited Release status at
Hudson as well as at S~nertek, our second source.
T-ll's are now
available to the outside world through Chip Sales as u/T-ii.
The
T-11 HOT LINE number is (DTN) 225-5061; the HOT LINE is available
to internal users for answering T-1i applications auestions.
As we look ahead, the price of T-11's will be coming down as
production costs decrease with improved ~ields, better testing,
etc.
The predicted transfer cost for FY83 is $25 and the cost for FY84 is not to exceed $18 per chip.
Reduced pricing should
open UP new areas for T-l1 applications.
Revision E of the T-11 EnSineerinS Specification includes all
specification updates as of 1 MAR 82.
All changes were approved
at Chip Change Control (CCC) Meetings.
These meetings give T-11
us~rs a chance to review proposed chanses so the changes that are
approved will not be user sensitive.
Most of the changes between
Revisions D and E of the Spec. fall into. the categor~ of
documentation clarification. For specific details of the
chanses, please refer to ·Documentation of T-li Engineering
Specification Histor~·.
This will be the last automatic update ~ou will receive.
SubseQuent updates will be processed throuSh the normal ECO
procedure.
See HL Document Control in the future.
THE T-l1 SPECIFICATION IS COMPANY CONFIDENTIAL, SO,
PLEASE HAVE YOUR OLD SPECIFICATIONS SHREDDED.
Thank

~ou

for

~our

interest in the T-i1 Microprocessor.

+---+---+---+---+---+---+---+
I d I i I g I i I t I a I 1 I
+---+---+---+---+---+---+---+
To: T-11 ENGINEERING
SPECIFICATION DIST.

SUBJECT:

I N T E R 0 F F ICE

M E M 0

Date:
1 MAR 82
C\~
From: David Forsythe ~Jjtt.
Dept:
Low Cost LSI
Ext:
225-5283
Decnet:
SNICKR::FORSYTHE
Loc/Mai1 Stop: HL1-1/Q08

DOCUMENTATION OF T-11 ENGINEERING SPECIFICATION HISTORY

In order to better document the history of the T-11 Engineering
Specification, the following lists of the differences between
Rev's. C and D and Rev's. D and E of the T-11 Engineering
Specification have been compiled.
I would also like to draw your
attention to two conventions which were adopted in order to help
document the changes between revisions of the T-11 Engineering
Spec. Each page has a revision letter on it corresponding to the
last revision in which any changes were made on that page. For
instance, a page with "Rev B" on it was changed between Revisions
A and B, but has had no changes since. Also, the lines that were
changed between the current and former revisions of each page are
denoted by a "I" in the right hand margin.
The following differences exist between Rev. C and Rev. D of the
T-ll Engineering Specification.
1.

Page 8, Section 2.2.7 Signal Utilization for Each Bus Mode:
A column in the table was added with the heading "Dynamic All
Modes" and entries were made in the AI rows. Notes were
added in 8 Bit Dynamic mode and 16 Bit Dynamic mode, "In
4ynamic mode at refresh time the AI are the output of an 8
bit counter"; in 16 Bit Dynamic 64K mode, "Caution because
DALO maps to AI<6> word and byte operation are mapped to
different memory locations unless external AI logic is
used."; for AI<O> in 16 Bit Dynamic 4K/16K mode, "Fetch cycle
if not doing a refresh cycle."

Page 14, Sections 2.3.16 DAL<15:8> (Input/Output TRI-STATE)
Data and Address Lines and 2.3.17 Da1<7:0> (Input/Output)
Data and Address Lines:
In explanation of when the DALs
output indeterminate data, "byte not addressed during byte
operation" was changed to "byte not addressed during
Write/byte operation with ready slips".

ftDIFFERENCES BETWEEN REVS. C AND Dft
Page 2

Page 15, Section 2.3.18 AI<7:0> (Input/Output TRISTATE)
Address and Interrupt:
the paragraph;
During refresh, the refresh address is provided on
the AI Lines. The refresh counter is decremented
after each refresh.
was changed to;
During refresh in all dynamic modes, the refresh
address 8 bit counter is provided on the AI Lines.
The refresh counter is decremented after each
refresh.
Also, Refresh Counter Bit 7 was designated "MSB" and Refresh
Counter Bit 0 was designated ftLSBft.

Page 17, Section 2.3.18: Under the FETCH description, the
note, ·CAUTION: During Refresh, the AI lines have the refresh
counter address on them.ft was added.

Page 18, Section 2.3.19 Sample Signal Equivalency for
Specific Manufacturer's Chip Families: For the Mostek
MK4027-3/4, the Equivalent T-ll Signals for Manufact. Family
Signals A<S:0> were changed from "AI<S:0>ft to "AI<6:1>ft; for
the Mostek MK4116-2/3, the Manufact. Family Signals for the
Equivalent T-ll Signals, AI<7:1>, were changed from ftA<7:1>"
to "A<6:0>".

Page 23, Section 3.1 Absolute Maximum Ratings: The
statement, ·Currents sourced by the DC3l0 are indicated by a
negative prefix to the value listed." was added. Section 3.2
Static Characteristics: ·TJ = 0 to 100 C" was changed to "TA
= 0 to 70 CHi the IlL limit was changed from +/-20 uA to
+/-50 uA; the IFL limit was changed from +/-20 uA to +/-50
uA. The parameter IILP was deleted. The current direction
on the IIH parameters was corrected to correspond with the
current direction convention;
IIH (MIN) was changed from 0.1
mA to -0.1 mA, and IIH (MAX) was changed from 1 uA to -1 mA
(the uA to mA change was a documentation error correction).
The following new parameters were added in the Rev. D. Spec.:
IXLIH (Input High Current on XTLl) has a maximum limit of
+700 uA with 2.4<VIN<VCC and XTL0 grounded, IXLIL (Input Low
Current on XTLI has a maximum limit of -6.4 rnA with
-0.S<VIN<+0.8V and XTL0 grounded, and VOHB (Output High
Voltage for -BCLR has a minimum limit of 2.2V with IOH = -700
uA and the -BCLR line terminated with a lK resistor to VSS.

"DIFFERENCES BETWEEN REVS. C AND 0"
Page 3

Page 24, Section 4.1 Bus Timing Annotated for Maximum XTL1,
XTLg Operating Frequency: Limit on TASF changed from
"(T - 48) = 85 ns min" to "(T - 83) = 5~ ns min"; TASR
changed from "(T - 68) = 65 ns min" to "(T - 83) = Sg ns
min".

page 26, Section 4.1: Documentation error corrected;
for
TMRC, "(2T + 19) = 177 ns min" changed to "(2T + l~) = 277 ns
min".

Page 27, Section 4.1: TNHC limit changed from "(T - 19) =
123 ns min" to "(T - 32) = 19l ns min"; TNHR limit changed
from "(T - 118) = 15 ns min" to "(T - 198) = 25 ns min";
TNHP limit changed from "(T - 21) = 112 ns min" to "(T - 43)
= 9g ns min"; TNMP limit changed from "(6T - 3g) = 77g ns
minn to n(6T - 66) = 734 ns minn.

19. Page 28, Section 4.1: TPIP limit changed from "(2T - 37) =
23g ns minn to "(2T - 47) = 22g ns min"; TPSN limit changed
from "(3T - 58) = 342 ns minn to n(3T - 9g) = 31g ns min";
TPSR limit changed from n(2T + 24) = 291 ns minn to
"(2T + 14) = 281 ns min".
11. Page 29, Section 4.1: TRWD limit changed from "(T + 112)
245 ns max" to "(2T + 4) = 27g ns max"; TSS limit changed
from "2g ns min" to "g ns min".

12. Page 3~, Section 4.1: TWSP limit changed from "(3T - 85) =
315 ns min" to "(3T - 11g) = 29g ns min".
13. Page 31, Section 4.1, Notes: Note 11 was deleted; it said
"When user aserts these signals, he is responsible for
preventing TRI-STATE conflicts and for meeting any precharge
times otherwise required by his own external circuits.
14. Page C-3, Comparison of T-11 to other processors in the
PDP-II Family: Activity 11A was added for the T-11 only.
11A. When operating with the T-bit set (e.g. single
stepping) no interrupt requests will be serviced.
At the end of instruction execution, the T-bit
has higher priority than interrupt requests.
Once in the T-bit service routine, other interrupts
are blocked to insure no unexpected occurances.
When the RTT instruction is executed to leave
the service routine, interrupts will not be
serviced if the T-bit is set in the new PS
popped off the stack. The user will, therefore,
not see any interrupt requests he is expecting.

"DIFFERENCES BETWEEN REVS. D AND En
Page 4
The following differences exist between Rev. D and Rev. E of the
T-1l Engineering Specification:
Item Number

Description of Change

Change TUPP limit to 100,000 ns min. Reference
Bug Report 84.
(Approved CCC Meeting of 1 April,
1981) •

* Delete TASF from A.C. Characteristics. Change
TASF to TASR on Refresh Timing Diagram. Reference
Bug Report 125.

* Change limit on TSHF to 10 ns
Bug Report 134.

* Delete TAHF from A.C. Characteristics. Change
TAHF to TAHR on Refresh Timing Diagram. Reference
Bug Report 135.

Change "BUS, Nap" to "BUS Nap" on page 14.

Show TORT on READY Timing Diagram.

Delete the word TRI-STATE where it applies to the
AI lines; rewrite text appropriately. Reference
Bug Report 148.

Delete IFL from D.C. Characteristics list.
Bug Report 150.

Change nTSDE" to nTDSE" on lACK diagram.
Bug Report 151.

10.

Add TSSF to A.C. Characteristics list.
Bug Report 152.

11.

Revise Power-Up Timing Diagram to include RESET
timing. Reference Bug Reports 153, 163.

12.

Change "TSFR" on Read/Write Timing Diagram to
WTFFR". Change TFFR definition to "Refresh or
Fetch on SEL0 (L.E.) Set Up Time to -RAS (L.E.)".
Reference Bug Report 156.

13.

Add list of pins to each D.C. Characteristic.
Reference Bug Report 157.

min.

Reference

Reference
Reference

-DIFFERENCES BETWEEN REVS. D AND E"
Page 5
14.

Redefine TKHR as TWHR and change definition of TWHR
to -SAL<15:8>, Write Data, or lACK Information Hold
Time from -RAS (T.E.)-. Reference Bug Report ISS.

15.

Change -READY (T.E.)" to -READY (L.E.)- in
definitions for TYSC and TYSR. Reference
Bug Report 159.

16.

Add TMHB to A.C. Characteristics List.
Bug Report l6~.

17.

Change -TCMP- to "TCSP- on DMA Timing Diagram.
Reference Bug Report 161.

IS.

Add TDFB to A.C. Characteristics List. Change Note
l~ on page 31 (Rev. D page number) to "-BCLR may be
used to gate mode input during RESET. TDFB may be
violated on DAL<15:S,1:0> only. Violation of TDFB
on DAL<7:2> may corrupt the processor.- Reference
Bug Report 162.

19.

Use new convention for showing active pullups on
all timing diagrams where applicable. Reference
Bug Report 164.

2~.

Change VIHPUP limit to 2.2V min.
Bug Report 143.

21.

Change VILPUP limits to
Bug Report 145.

22.

Change ICC limit to "19~ rnA, STATIC, TA =
Reference Bug Report 144.

23.

Change Absolute Maximum Power Rating to "1.1 Watt".
Reference Bug Report 149.

24.

Change IlL limit to --5~ uA, VIN = ~.4V; +l~ uA,
VIN = VCCMAX". Reference Bug Report 13~.

-~.5V

Reference

to +~.6V.
~

Cu.

These changes approved at the CCC meeting of 12 NOV Sl.
Rev E. changes with no special notes were approved at the
26 FEB S2 CCC Meeting.

rar:l.2~

T-ll ENGINEERING SPECIFICATION

Revision as of March 1, 1982

COMPANY CONFIDENTIAL

Rev E

TABLE OF CONTENTS
Page No.
1.0

T-11
1.1
1.2
1.3
1.4

2.0

(Pages 1-3)
Scope
Applicable Documents
T-11 Chip Description
Special Features

FEATURES
2.1
2.2

Interrupt Structure
System Modes
Mode Register Bit Designation
Bus Modes
Tester Mode
Bus Length Mode
Restart Modes
Clock Modes
Signal Utilization for Each Bus Mode

External Signals
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
2.3.11
2.3.12
2.3.13
2.3.14
2.3.15
2.3.16
2.3.17
2.3.18
2.3.19

2.4
2.5
2.6

1
1

(Pages 4-22)

2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.3

VCC
GND
BGND
PUP (Input)
XTLI (Input)
XTL0 (Output/Input)
COUT (Output)
BCLR (Output)
-RAS (Output TRI-STATE)
-CAS (Output TRI-STATE)
PI (Output)
R/-WHB (Output)
R/-WLB (Output)
SEL<l:~> (Output)
READY (Input)
DAL<15:8> (Input/Output TRI-STATE)
DAL<7:~> (Input/Output)
AI<7:~> (Input/Output TRI-STATE)
Sample Signal Equivalency for Specific
Manufacturer's Chip Families

Pinout
T-11 Block Diagram
Instruction Set

COMPANY CONFIDENTIAL

4
5
5
6
7
7
7
7
8
9
9
9
9
9
9
10
10
10
10
10
11
11

11
12
13
14
14.
15
18
2~

21
22

TABLE OF CONTENTS CONTINUED
3.~

D.C. CHARACTERISTICS
3.1
3.2

4.~

Absolute Maximum Ratings
Static Characteristics

A.C. CHARACTERISTICS
4.1
4.2
4.3

(Page 23)
23
23

(Pages 24 - 33)

Bus Timing Annotated for Maximum XTL1,
Operating Frequency
Crystal Specification
Timing Diagrams

XTL~

25
33
34

APPENDIX A
T-ll Instruction Execution Times at Maximum Operating
Frequency
APPENDIX B
T-11 Instruction Execution Times in Microcycles
APPENDIX C
PDP11 Differences List
APPENDIX D
Worst Case Refresh Rate Calculations
APPENDIX E
I/O Transactions per instruction
Rev B

COMPANY CONFIDENTIAL

l.~

T-ll

1.1

SCOPE

This document specifies the functionality of MOS/LSI chip which I
is a one chip PDP-II.
The descriptions herein assume readers are
familiar wi th the PDP-II instruction set and software archi tecture.
For further information, the applicable documents should be consulted.
THIS SPECIFICATION
LAYOUT CONSIDERATIONS.

SUBJECT TO

CHANGE

BECAUSE

LOGIC

AND

ALL CONTENTS OF THIS DOCUMENT ARE COMPANY CONFIDENTIAL, AND DUE
CAUTION SHOULD BE EXERCISED TO CONTROL EVEN INTERNAL DISSEMINATION.
1.2

Applicable Documents

For DEC documents, they are assumed to be applicable in general,
but this document has precedence.
For other vendors documents, all attempts have been made for this
document to be correct, but other vendors' specs must dominate.
DEC's Microcomputer Processors 1978-1979 (Section 3, Chapters 9,
l~, & 12)
DCTll-AA User's Guide
MOSTEK's MK4~27-2/3/4 Functional Specification
MOSTEK's MK4l16-2/3 Functional Specification
INTEL's Component Data Catalog
MOTOROLA's M68~0 Microcomputer System Design Data Handbook
MOTOROLA's 1.5 and 2.0 MHz Components for the M6800 Microcomputer
System Data Sheet
1.3

T-ll Chip Description

The T-ll is a one chip PDP-II intended to be internally
competitive (cost and
chip count) with the 8085 in bounded system
applications.
Its major features are the LSI-II instruction set, an
efficient l6-bit internal architecture and a bus which is compatible
with TTL, memory chips, 8~85 and 6800 peripheral chips, etc.
A
user-loadable mode register customizes T-ll to a variety of
envi ronments:
for example, a mode is avai lable which operates the
16-bit T-ll on an 8-bit data bus. Other special features of the T-ll,
many not found on other microprocessors, are listed in Section 1.4.
Rev. B

COMPANY CONFIDENTIAL
Page 1

The T-ll is a l6-bit microprocessor which connects easily to many LSI
memory and S-bit I/O chips.
The 4e pins of T-ll do multiple duty.
They are designed to require few support chips for simple systems, and
to need only a few more chips for complex systems.
The system
designer may save cost when he needs to or may achieve high functionality at still modest costs.
To accomplish this range of I/O
adaptability, the T-ll accesses during power up an external MODE
REGISTER and modifies its pin functions based on the state of the mode
register bits.
For example, the simplest T-ll system might have limited memory and
I/O. For this system, T-ll in STATIC, S-BIT, DELAYED STROBE mode has:
an address and data-transfer bus identical to the sess; an internal
oscillator amplifier needing only a crystal and two capacitors to
clock the CPU; an input PUP, needing only a single capacitor to send
the processor to the chosen startup address; an oscillator output,
COUT, to drive a baud rate chip; and direct interrupt inputs,
AI<7:6,4:l> which are internally prioritized, masked and vectored.
Addition of large ROMs to this system requires an MSI octal latch to
demultiplex the low address bits <7:1>; -RAS may clock this latch.
Addition of more interrupting devices requires an MSI priority encoder
to send a code, instead of bits, to AI<4:l>.
Addition of 6See-type devices to this system requires a different
mode, NORMAL STROBE, for 6Sel-type Read/Write.
An MSI or SSI chip
then is needed to make the SeSS-type signals -RD, -WT, using the T-II
-CAS signal.
Addition of large amounts of Read/Write memory implies low-cost-perbit dynamic RAM chips. T-ll in DYNAMIC MODE accomplishes all of the
address multiplexing and refreshing these memories need.
The only
additional support this mode requires is an MSI TRI-STATE buffer
enabled by PI (to bring interrupt signals to AI<7: e> only when T-II
has freed those pins from their address multiplexing function).
Finally, the T-II in 16-BIT MODE executes programs 6e% faster than in
S-BIT MOD~.
It requires two MSI support chips, one to latch address
bits <lS:S> which are now multiplexed with data, and one to decode
-RD, -WT strobes from the R/-WHB & R/-WLB pins.
In all cases, the T-Il runs PDP-ll software, if the system designer or
programmer has provided new drivers or compatibility hardware for all
II-incompatible I/O devices.
Rev E

COMPANY CONFIDENTIAL
Page 2

1.4

Special Features

Special features are:
-

LSI-l1 Instruction Set, less MARK
Internal Clock Oscillator
Automatic Power-on Initialization
+5V only operation
TTL level signals, designed for ~inimum support chip count
Specially multiplexed addresses for direct connection to l6-pin
dynamic RAM chips, with buried refresh
- Optional features set at power-up by information on data
lines (MODE REGISTER).
8 or 16 bit data bus
Start/Restart address
Static or 4K/16K/64K RAM chip address multiplexing
Bus-synchronous or constant frequency output clock
Normal or lenghthened bus cycle
- Internally generated interrupt vectors, with extra conditions
possible by external expansion

Special PDP-II differences are:
-

Halt is an unmaskable interrupt (at restart address)
Automatic Start sets stack pointer to 376, PSW to 340
Internal interrupt vectors are dedicated to specific priorities
No bus timeout
Not I/O program compatible with standard DEC operating systems

Approximate speed benchmarks:
All times given in microseconds, unless otherwise noted.

MOV R0,R1
ADD MEM1,MEM2
BEQ (taken)
AVERAGE BYTES
per microsecond

T-1l/l6

T-l1/8

LSI-l1/0

11/34(MOS)

1.6
6.00
1.6
1.5-1.7

2.4
10.8
2.4
1.9-1.1

4.3
14.4
4.3
0.7

1.96
7.27
2.31

NOTE:
T-1l benchmarks are calculated using
microcode and static modes and are subject to change.

Revision

5.18 I

Rev B

COMPANY CONFIDENTIAL
Page 3

2.~

FEATURES

2.1

Interrupt Structure

The T-ll inputs interrupt requests on the AI lines dur ing the
assertion of PI.
If -VEC is passive and any of the -CP<3:~> lines are active, and
the implied priority of that set of asserted -CP<3:8> lines is not
masked by the PSW, an interrupt will be taken using the vector address
indicated below.
If -VEC is active and any set of -CP<3:~> lines are active and
the implied priority of that set is not masked by the PSW, an
interrupt will be taken using a vector address read in from DAL<7:2>.
Request Level

Implied

Other
-CP3 -CP2 -CPl
X- X-X -X
-DMR
-CP~

Address

-HLT

-PF

L
L
L
L
L
L
L

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H

7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
NO ACTION

l4~*

H
H
H
H
H
H
H
H

*NOTE:

Priority
8

Implied
Vector

L
L

L
H
H
L
L
H
H

H
H
H

H
L
H
L
H
L

H
L

Other
Action
DAL<15:8> <-TRISTATE>
AI<7:~> <-LOWCURRENT PULLUPS
-(SP) <- PS
-(SP) <- PC
PS <- 34~
PC <-START ADDRESS
+ 4

I
I

144*

I
I

15~*

154*

I
I

1~~*

184*

I,
t

ll~*

114*
12~*

124*

13~*

134*

6~*

64*

7~*

if interrupt was accompanied by -VEC, Vector Address <7:2> is
determined by DAL <7:2>.
Rev B

COMPANY CONFIDENTIAL
Page 4

2.2

System Modes

The system is configured into specific operating modes at
power-up and during a RESET instruction.
This is accomplished by the
T-ll automatically reading in specific bits of the DAL while it is
asserting -BCLR.
This -BCLR signal can be used to enable TRI-STATE
drivers external to the T-ll that in turn will assert specific bits of
the DAL to set the operating mode desired.
(NOTE:
Since low current
pull-ups internal to the T-ll (DAL<15:8>,<2:12J»
are enabled on the'
DAL inputs during -BCLR, only those bits that must be driven low need
to be asserted.) The different modes are defined below. MR refers to
the mode register that exists internally in the T-ll.
There is a
one-to-one bit mapping of the MR bits and the DAL (i.e., DALI2J8=MRI2J8,
DALI2J9=MRI2J9, etc.).

2.2.1

Mode Register Bit Designation

Summary:
15

1121

<-- RESERVED -->

-------------------------------------.-------------------------\
Restart
Addresses

,, ,,,
I
I
I

I
I
I
I

I
I
I

,, \I NORM

,I \I PMC

, \I DYNAMIC

\ LMC

I
,
\ MD64K
I
,I \ MD16
\ TESTER
Mode register
sections.

details will

be described

in detail

the

following

Rev B

COMPANY CONFIDENTIAL
Page 5

Bus Modes

2.2.2

Static

MR11 MR1'" MR9

---

MR8

Address Mode

Data Bus

H
H

H
H
H
H

H
H
H

H
H

STATIC
STATIC
STATIC
STATIC

8 BITS
8 BITS
16 BITS
16 BITS

NOTE
NOTE
NOTE
NOTE

H
H

L
L
L
L
L
L
L
L

H
L

4/16K DYNAMIC
4/16K DYNAMIC
4/16K DYNAMIC
4/16K DYNAMIC
64K DYNAMIC
64K DYNAMIC
64K DYNAMIC
64K DYNAMIC

8 BITS
8 BITS
16 BITS
16 BITS
8 BITS
8 BITS
16 BITS
16 BITS

NOTE 1
NOTE 2
NOTE 3
NOTE 4
NOTE 1
NOTE 2
NOTE 3
NOTE 4

L
L

1
2
3

D~namic

H
H
L
L
H
H

L
L

H
H

L
L
L
L

L
H

L
H
L

NOTE 1:

Delayed -RD and -WT control signals.
These signals
become valid after the assertion of -RAS.
This mode
makes the T-ll bus a proper subset of the 8"'85 bus.

NOTE 2:

-RD and -WT control signals are stable before the leading
edge of -RAS.

NOTE 3:

Delayed R/-WLB and R/-WHB control signals.
become valid after the assertion of -RAS.

NOTE 4:

R/-WLB and R/-WHB control signals are stable before the
leading edge of -~AS.

MR11

MD16
8 bit data bus
16 bit data bus

MD64K
4/l6K dynamic memory support
64K dynamic memory support

DYNAMIC
Static addressing
Dynamic addressing

NORM
Delayed Read/Write control signals
Normal Read/Write control signals

H
L
MR1'"

H
L

MR9

H
L

MR8

These signals

Rev B

COMPANY CONFIDENTIAL
Page 6

Tester Mode

2.2.3

MR12 = TESTER (reserved for DEC testing use-not a user
feature)
H
L

Normal
A special cycle preceeds every instruction fetch.
The cycle appears as a WRITE bus cycle.
The address
of the WRITE will be 0, PS<7:0).
In 8 bit modes the
address of the write will be 0, PS<7:9), for the low
byte and 9, PS<7:0) with the low bit forced to a 1
for the high byte. The Data of the WRITE will be the
contents of the PDP-II destination register of the
last instruction.

Bus Length Mode

2.2.4

= LMC (Long Micro Cycle)

MRI
H
L

Normal Micro cycle
Long Micro cycle - Every microcycle is increased by one
phase (@7.5MHz = 133 ns). This can
provide synchronization of COUT to
the I/O cycles (if PMC mode
H).

Restart Modes

2.2.5

The START Address is used at power-up.
The RESTART
Address is used for the hardware HALT interrupt and during the
execution of a PDP-II HALT instruction.
MR15 MR14 MR13
-H
H
H
H
L
L
L
L

H
H
L
L
H
H
L
L

H
L
H
L

RESTART Address

START Address

172004
173004
000004
010994
029004
940994
1"0004
140""4

172000
173990
000000
910990
020000
940""0
100000
14"900

Clock Modes

2.2.6

MR0
H
L

= PMC (Processor Mode Clock)
Clock asserted once every microinstruction (3 or 4
oscillator periods)
Clock out constant frequency (two oscillator periods)
Rev B

COMPANY CONFIDENTIAL
Page 7

2.2.7 Sisnal Utilization for Each Bus Mode
16 BIT

8 BIT
Chip Pin
Out Name

Dynamic*
4K/16K
ill

Static

D~namic*

4K/1K

64K

'ICC
GND
BGND
PUP
XTLl
XTL0
COUT
-BCLR

VCC
GND
BGND
PUP
XTLl
XTL0
COUT
-BCLR

VCC
GND
BGND
PUP
XTLl
XTU
COUT
-BCLR

VCC
GND
BGND
PUP
XTLl
XTL0
COUT
-BCLR

-RAS
-CAS
PI
R/-WHB
R/-WLB
SEL0
SELl
READY

-RAS
-CAS
PI
-RD
-WT
FET+DMG
IAK+DMG
READY

-RAS
-CAS
PI
-RD
-WT
REF+DMG
IAK+DMG
READY

-RAS
-CAS
PI
-RD

-RAS
-CAS
PI
R/-WHB
R/-WLB
FET+DMG
IAK+DMG
READY

-RAS
-CAS
PI
R/-WHB
R/-WLB
REF+DMG
IAK+DMG
READY

-RAS
-CAS
PI
R/-WHB
R/-WLB
FET+DMG
IAK+DMG
READY

DAL<15:l3> SAL<15:l3> SAL<15:13>
(0)
un
DAL<12>
SAL<12>
SAL<12>
(-VEC)
( -VEC)
SAL<ll>
SAL<ll>
DAL<ll>
(-CP<0»
(-CP<0»
SAL<lf11>
SAL<10>
DAL<l">
(-CP<l»
(-CP<l»
SAL(9)
DAL<9>
SAL<9>
(-CP<2»
(-CP<2»
DAL<8>
SAL<8>
SAL<S>
(-CP<3> )
(-CP<3»
DAL<7:2>
SAL<7:2>
SAL<7:2>
(VECTOR
(VECTOR
INPUT)
INPUT)
SAL<1:0>
nL<l:">
SAL<l:">
AI<0>
AI<l>
AI<2>
AI<3>
AI<4>
AI<5>
AI<6>
AI<7>

-DMR
-CP3
-CP2
-CPl
-CP0
-VEC
-PF
-HLT

-WT
FET+DMG
IAK+DMG
READY

SAL<15:13> DAL<15:13> DAL<15:13>
(0)
(0)
(0)
DAL<12>
SAL<12>
DAL<12>
(-VEe)
(-VEC)
(-VEC)
DAL<ll>
SAL<ll>
DAL<ll>
(-CP<0»
(-CP<"»
(-CP<"»
SAL<10>
DAL
DAL
(-CP<l»
(-CP<l»
(-CP<l»
DAL(9)
SAL<9>
DAL<9>
(-CP<2»
(-CP<2»
(-CP<2»
SAL<S>
DAL<S>
DAL<S>
(-CP<3»
(-CP<3»
(-CP<3»
DAL<7:2>
DAL<7:2>
SAL<7:2>
(VECTOR
(VECTOR
(VECTOR
INPUT)
INPUT)
INPUT)
SAL<1:0>
DAL<1:0>
DAL<l:">

FET:A14-DMR A15:A14-DMR
A1:A2-CP3
Al:A2-CP3
A3:A4-CP2
A3:A4-CP2
A5:A6-CPl
A5:A6-CPl
A7:AS-CP0
A7:AS-CP0
A9:A10-VEC A9:Al0-VEC
All:A0-PF
All: A"-PF
Al3:A12-BLT A13:A12-BLT

-DMR
-CP3
-CP2
-CPl
-CP0
-VEC
-PF
-BLT

DAL<15:13>
(0)
DAL(12)
(-VEC)
DAL<ll>
(-CP<"»
DAL
(-CP<l»
DAL<9>
(-CP<2»
DAL<S>
(-CP<3»
DAL<7:2>
(VECTOR
INPUT)
DAL<1:0>

+FET:A14-DMR Al5:A14-DMR -7 MSB
Al:A2-CP3
Al:A2-CP3
-0 LSB
A3:A4-CP2
-1
A3:A4-CP2
A5:A6-CPl
A5:A6-CPl
-2
-3
A7:AS-CP0
A7:AS-CP0
A9:A10-VEC A9:A10-VEC -4
All:A12-PF All:A12-PF -5
A13:Al4-BLT Al3:Al4-BLT -6

- means asserted low
Al:A2-CP0 means:

Address bit i at -RAS leading edge,
Address bit 2 at -CAS leading edge,
-CP" input during PI.

Names in ( ) are valid during lACK cycle
*In dynamic mode at refresh time the AI are the output of an 8 bit counter

+Fetch cycle if not doing a refresh cycle.
Rev E

COMPANY CONFIDENTIAL
Page 8

Dynamic
All Modes I

2.3
2.3.1

External Signals
VCC

+5 volt supply (+/- 5%).
2.3.2

GND

Reference ground for most of chip
2.3.3

BGND

Second ground pin. It is recommended that BGND be connected to ground
by a separate ground run from the GND pin.
2.3.4

PUP (Input)
Power Up

This schmitt-triggered input has a low-current internal pull-down that
is always enabled.
When PUP is high, the T-ll internal cycles are
forced to an ini tial condi tion wi th undefined register states, wi th
-BCLR asserted, and with low-current pullups on AI<7:S> and those DAL
lines used for Mode Register inputs. When T-ll detects a low voltage
on PUP, a power-up sequence begins, which:
starts the internal clock
loads the Mode Register for several microcycles from DAL;
negates -BCLR (returns to high);
.
performs (if Dynamic Mode) several refresh cycles;
loads PC with Mode-selected Start Address;
loads PSW with 34S;
loads SP with 376;
checks DMR and HALT inputs (others masked by PSW) with an ASPI*
begins normal operation.
Connecting a capacitor between PUP and VCC can give a simple powerup
detector circuit.
*See note on ASPI under 2.3.14.
2.3.5

XTLl (Input)
Crystal In/External Oscillator In

Crystal connection to the internal clock oscillator. With a crystal/
capaci tor network connected to XTLI and XTLS, T-ll implements a
crystal oscillator to generate the operating clock.
Alternatively,
the user may ground XTLS, and apply an external operating clock (atl
TTL levels) to XTLI.
Rev B I

COMPANY CONFIDENTIAL
Page 9

2.3.6

XTL0 (Output/Input)
Crystal Out

Crystal connection to the internal clock oscillator. This pin must be
grounded if an external clock is to drive XTLI. See XTLl.
2.3.7

COUT (Output)
Clock Out

This pin outputs a TTL level clock that is a function of the operating
clock and Mode Register bi t 0 (MR0).
If MRI=l, then a clock is
asserted every 3 or 4 oscillator periods.
If MR0=0, then a clock is
asserted that is half the frequency of the operating clock frequency.
A high level on PUP initializes MR0=1.
2.3.8

-BCLR (Output)
Bus Clear

This signal is asserted low by the T-ll during power-up (see PUP) and
also in execution of a PDP-II RESET instruction.
(Note:
this pin
must be connected to GND through a lK ohm + 1% metal film resistor at
all times, to ensure correct T-ll operation.)
An internal pull down
in the T-ll will sink 0.3 to 1.6 rnA (see IILP section 3.2), thus -BCLR
is a strobe which should enable user Mode pulldowns on DAL<15:8,2:9>.
The normal high output level will be lower on this pin than on any
other pin.
However, it will always be at least 3V.. Mode bi t input
begins several microcycles after -BCLR is asserted and PUP is low, and
continues until microcode returns -BCLR to a high.
2.3.9

-RAS (Output)

~Address Strobe

The row address strobe used by dynamic memories.
It can be used to
latch the address on the DAL bus for ROMs, static RAMs and 8185 type
peripheral chips.
It can also be used to latch refresh information
when the refresh output flag is selected.
This signal remains active (i.e., emulates I/O bus timing every two I
machine cycles) when DMG (SEL<l:9>=3) is asserted.
2.3.10

-CAS (Output)
Column Address Strobe

The column address strobe used by dynamic RAMs. -CAS can also be used
as a cri tical signal for peripheral chips that need long address
set-up times relative to the leading edge of the control signal (e.g.,
M68XX type parts), or long address and data hold times relative to the
trailing edge of the control signal (e.g., 2659 type parts).
The
leading edge can also be used to clock interrupt lines to insure
theyare stable during PI.
Rev C
COMPANY CONFIDENTIAL
Page 10

This signal remains active (i. e., emulates I/O bus timing every two
machine cycles) when DMG (SEL<1:1>=3) is asserted.
2.3.11

PI (Output)
Priority In Strobe

This signal is asserted when the T-1l is executing an I/O cycle, has
given up the bus for a DMA cycle, or is moni toring for interrupts.
During a Write operation, the data on the DAL lines are stable when PI
is asserted.
Since the AI internal drivers are off whenever PI is
asserted, PI can be used to gate -HALT, -PF, -VEC, -DMR and the
-CP<3:1> signals onto the AI lines.
A -CAS signal always accompanies PI, thereby
indication of the interrupt/DMA input operation.

providing

early

2.3.12 R/-WHB (Output)
NOTE:
Since the R/-WHB and -RD signals use the same pin, the signal
enabled depends on whether l6-bit or 8-bit mode has been selected.
R/-WHB (16 bit mode)
Read/Write High Byte
In l6-bit modes this signal indicates whether the current I/O cycle
is a read from or a write to the high byte of the location
addressed.
In normal control mode, R/-WHB is stable before the
leading edge of -RAS.
In delayed control mode, R/-WHB is issued by
the T-1l after the assertion of -RAS.
-RD (8 bi t mode)
Read
In 8-bit modes this signal indicates that the current I/O cycle is
an eight bi t read from the location addressed.
In normal control
mode, -RD is stable before the leading edge of -RAS.
In delayed
control mode, -RD is issued by the T-ll after the assertion of -RAS
(this corresponds to the 8085 timing relationship between ALE and
-RD). R/-WHB pin has an internal low-current pullup during DMG.
2.3.13

R/-WLB (Output)

NOTE:
Since R/-WLB and -WT signals use the same pin, the signal
enabled depends on whether 16-bit or 8-bit mode has been selected.
Rev C

COMPANY CONFIDENTIAL
Page 11

R/-WLB (16 bit mode)
Read/Write Low Byte
In l6-bit modes this signal indicates whether the current I/O cycle
is a read from or a write to the low byte of the location addressed.
In normal control mode, R/-WLB is stable before the leading edge of
-RAS.
In delayed control mode, R/-WLB is issued by the T-ll after
the assertion of -RAS.
-WT (8 bi t mode)
Write
In 8-bit modes this signal indicates that the current I/O cycle is
an eight bi t write to the location addressed.
In normal control
mode, -WT is stable before the leading edge of -RAS.
In delayed
control mode, -WT is issued by the T-ll after the assertion of -RAS
(this corresponds to the 8"85 timing relationship between ALE and
-WT). The R/-WLB pin has an internal low-current pullup during DMG.
**************************************************
*NOTE:
A DATA OUT Cycle to a location is*
*preceeded by a DATA IN to the same location*
*(except for stack operations). A DMG can not be*
*issued in the interval between DATA IN and DATA*
*OUT.
*
**************************************************
2.3.14 SEL<1:0> (Output)
Select Output Flags
This signal pair is used to select special output
functions are defined as follows:
SEL<l>

SEL<0>

L
L
H
H

L
H
L
H

functions.

The

FUNCTION
Read/Write or Bus NOP or ASPI
REFRESH**/FETCH*
IACK - Interrupt acknowledge***
DMG - Direct Memory Grant****

*See discussion of FETCH in AI section.
**Refresh in dynamic modes (except 64K), Fetch for static modes (plus
64K) •
***See discussion of lACK under INTERRUPT in the AI section.
****See discussion of DMG under -DMR in the AI section.
The SEL<l: 0> are stable before the lead ing edge of -RAS.
(NOTE:
If
DMA is not implemented in the external hardware, SEL<l:0> may be used
as direct strobes.>
It is sufficient for a DMG decode to monitor for a SEL<l:">
without using the leading edge of -RAS.

= 3 decode
Rev C

COMPANY CONFIDENTIAL
Page 12

REFRESH
In 8-bit dynamic mode, a refresh occurs after each instruction fetch
and once with each source or destination mode 5, 6 or 7 operand fetch.
Two additional refreshes occur during any trap sequence.
In l6-bit dynamic mode, refreshes happen at half the frequency of the
8-bi t mode refreshes (i. e. every other opportuni ty, opportunities
defined in 8 bit mode). This buried refresh scheme gives a worst case
specification of 128 refreshes in 1.33 ms. @7.5MHz operating
frequency.
This allows 3.66 ms out of every 2 ms for DMA cycles and
I/O transaction extensions (READY slips or LHC; long micro cycle
mode). See APPENDIX D.
ASPI
An ASPI occurs to check for DMR and HALT inputs before the first I
instruction fetch and to check for interrupts as well as DMR and HALT I
during the WAIT instruction.
During an ASPI only -CAS and PI are I
asserted (-RAS remains unasserted).
BUS NOP
A bus NOP occurs whenever the processor requires an internal operation:
and no other acti vi ty can occur on the bus (i. e. no READ/WRITE, I
REFRESH, ASPI, lACK, or DMG).
I
2.3.15

READY (Input)

This signal places the T-ll into an idle state waiting for the device
that issued the READY to finish the I/O transaction.
This signal
allows memory or I/O devices of any speed to be synchronized to the
T-ll.
READY slips can occur while -RAS is active except duringl
Refresh cycles (Le. DATA IN, DATA OUT, lACK, and during DMG).
AI
single assertion of READY causes a single machine cycle slip.
READY must be pulsed in order to cause additional cycle slips.
As a
special case, an extra machine cycle (483ns min) of idle time can be
guaranteed by simply gating -RAS wi th the external device's Chip
Select signal onto the READY line.
If the READY line is connected to
GND, this single cycle slip will occur during every I/O or lACK cycle.
READY is always internally connected to a low current pull up.
Rev E

COMPANY CONFIDENTIAL
Page 13

2.3.16

DAL<15:8> (Input/Output TRI-STATE)
Data and Address Lines
SAL<15:8> (Input/Output TRI-STATE)
Static Address Lines during 8 Bit Mode

Time multiplexed data and address bus.
Addresses are stable before
the leading edge of -RAS.
Input data should be available before the
trailing edge of -CAS. In 8-bit mode, the high byte of the address is
static throughout the I/O cycle.
During power-up or the execution of a RESET instruction the MODE
register bi ts are read in from these lines.
Low current internal
pull-ups on DAL <15:8> are enabled when -BCLR is asserted.
During an interrupt cycle, the priority level of the interrupt is
output on DAL<12:8>.
(DAL<12> = -VEC, DAL<ll> = -CP<9>, DAL<10> =
-CP<l>, DAL<9> = -CP <2>, DAL <8> = -CP <3>.)
At all other times (i.e. ASPI, BUS NOP, REFRESH, byte not addressed
during Write/byte operation with ready slips) indeterminate data isl
output on DALs.
TRI-STATED when DMG (SEL<1:0>=3) is asserted.
2.3.17

DAL<7:0> (Input/Output)
Data and Address Lines

Time multiplexed data and address bus.
Addresses are stable before
the leading edge of -RAS.
Input data should be available before the
trailing edge of -CAS.
During external vector lACK cycles (SEL<l:0>=2 and assertion of
-VEC), DAL<7:9> are tristated to read a vector address from DAL<7:2>
(NOTE:
Data on DAL<l: 0> is ignored).
DAL<7: 0> are tristated also
during internal vector lACK cycles.
During power-up or the execution of a RESET instruction the MODE
register bits are read in from these lines.
Low current internal
pull-ups are enabled on DAL <2:0> when -BCLR is asserted.
At all other times (i.e. ASPI, BUS NOP, REFRESH, byte not addressed
during Write/byte operation with Ready Slips) indeterminate data isl
output on DALs.
TRl-STATED when DMG (SEL<1:9>=3) is asserted.
Rev E

COMPANY CONFIDENTIAL
Page 14

2.3.18

AI<7:~> (Input/Output)
Address and Interrupt

-ADDRESS (Output)
(Dynamic Mode)
Dynamic RAM address bus and interrupt information bus.
In dynamic modes, row addresses are stable before the
leading edge of -RAS, column addresses before the
leading edge of -CAS and interrupt information is read
in during PI time. The addresses available at -RAS and
-CAS times duplicate the address on the DAL, and are in
a format controlled by the mode bits in the MODE
register.
4K, 16K and 64K dynamic RAMs can be
accommodated as well as the different address bit
mappings required for 8 or 16 bi t data busses.
In
static modes, these lines are always connected as
inputs.
During refresh in all dynamic modes, the refresh I
address 8 bit counter is provided on the AI Lines. The I
refresh counter is decremented after each refresh.
AI BIT
~

1
2
3
4
5
6
7

Refresh Counter Bit
7 MSB
LSB

2
3
4
5
6

In all modes, these pins provide internal low current
pu11up when DMG (SEL<1:8>=3) is asserted.
INTERRUPT (Input)
-CP<3: ~> (Input)
Coded priority
During the assertion of PI (except during . DATA OUT
transactions), T-11 reads these signals from AI<4: 1>.
Logic internal to the T-II decodes this input as
interrupt requests on 15 levels, maskable at 4 levels
(using PSW<7:5>; the highest requesting level, if not
masked, will be recognized and a PDP-II trap sequence
executed.
For CP interrupts only (both internal and
external), recognition of an interrupt is acknowledged
on the bus with an lACK cycle (where SEL<1:~>=2 and the
recognized input (-VEC, -CP<0:3> is asserted by T-ll on
DAL <12:8».
Rev E
COMPANY CONFIDENTIAL
Page 15

-VEC (Input)
Vector
During the assertion of PI (except during DATA OUT
transactions), T-11 reads this signal from AI<S>, but
it has meaning only if a CP request is also present on
AI.
-VEC can be used to increase the number of T-11
interrupts, because it signals the processor to ignore
the vector indicated by CP<3: ,,> and use instead the
vecto r to be provided by the user.
Our ing the lACK
cycle, in this case, the user-provided vector address
data is read by T-11 from DAL<7:2>.
-VEC is
acknowledged by T-11 asserting DAL <12> low during the
lACK cycle.
-PF (Input)
Power Fail Interrupt Request
During the assertion of PI (except during DATA OUT J
transactions), T-ll reads this signal from AI<6>.
-PF
is the highest priority interrupt on Level 7.
The
input circuit requires no data setup time because
internal logic samples -PF, then pauses for a time (up
to one instruction) before recognizing a request.
Also, a request must be read as negated once, before
another assertion will be recognized.
This set of
logic makes -PF appropriate for a power-fail interrupt,
especially since -PF results in an interrupt with the
PDP-II powerfail vector (24 a ).
Note:

AN lACK cycle is not issued.

-HALT (Input)
Halt Interrupt Request
During the assertion of PI (except during DATA OUT I
transactions), T-il reads this signal from AI<7>.
The I
-Halt input circuit is pseudo-edge-sensitive, since the
signal must be read as a negation before an assertion
read ing wi 11 have any effect.
-Hal t i s an unmaskable
interrupt.
It causes an immediate transfer (after
stacking PC, PSW), with PSW=34", to the RESTART address
(see Restart Modes).
Note:

An lACK cycle is not issued
Rev B

COMPANY CONFIDENTIAL
Page 16

-DMR (Input)
DMA Request
During the assertion of any PI, T-ll reads this signal
from AI.
If the T-ll reads -DMR asserted, it will
(upon termination of the current bus cycle except the
DATA IN preceeding a DATA OUT) free the bus for DMA,
signifying this state with SEL<1:">=3. The T-ll
TRI-STATES DAL<15:B> and places low-current pullups on
AI<7:~3>
and the R/-WHB and R/-WLB pins.
The T-ll
remains somewhat in control of bus timing: -RAS, -CAS,
and PI pulse; signalling of AI address changeover time
is by the trailing edge of COUT (if COUT is in Pulse
Mode);
DMG remains asserted as long as the device
keeps AI<"> asserted during PI.
FETCH (Output)
This signal is issued by the T-ll on AI<"> when in
dynamic mode (except 64K) , and by SEL<l:B>=l in static
mode or 64K mode. It signifies that the current I/O
operation is an instruction fetch*.
FETCH on AI is
valid before the leading edge of -RAS and stops driving
before the leading edge of PI. When SEL<"> signifies
fetch, it is asserted only during the read cycle (In 8
bit mode only during the low byte read cycle).

*CAUTION: During Refresh, the AI lines have the refresh counter J
address on them.
I
Rev E

COMPANY CONFIDENTIAL
Page 17

2.3.19 SamEle Signal
Families

Manuf.

Family

MOSTEK

MK4flJ27-3/4

Esuivalenc~

for SEecific Manufacturer's ChiE

Applicable
T-ll Modes
(See Note 1)

Manufact.
Family
Signals

Equivalent
T-ll
Signals

4K DYNAMIC
8 or 16 BIT
REFRESH ON

A<5:8>
-CS
-RAS
-CAS
-WRITE

AI<6:1>
AI<6>
-RAS
-CAS
R/-W AND PI
-WT AND PI
DAL<n>
DAL<n>

DIN
DOUT
MK4l16-2/3

16K DYNAMIC
8 or 16 BIT
REFRESH ON

A<6:8>
-RAS
-CAS
-WRITE
DIN
DOUT

INTEL

MOTOROLA

8085
(e·9· ,
8155,
8355,
8755)

STATIC
DELAYED
CONTROL
8-BIT

8flJ8flJ
(e.g. ,
8251,
8253,
8255,
8279)

STATIC
DELAYED
CONTROL
8-BIT

68XflJflJ
(e.g.,
68X21,
68X5flJ)

STATIC
NORMAL
CONTROL
8-BIT

AI<7:1>
-RAS
-CAS
-R/W NAND PI
-RD NAND PI
DAL<n>
DAL<n>

Notes
2
3
4
5

3
4

A<15:8>
AD<7:flJ>
ALE
-RD
-WT
RESET
IO/M
READY

SAL<15:8>
DAL<7:flJ>
-RAS
-RD
-WT
-BCLR

-READY

A<15:8>
A<7:flJ>
D<7:8>
-RD
-WT
RESET
WAIT

SAL<15:8>
DAL<7:flJ>
DAL<7:flJ>
-RD
-WT
-BCLR
READY

A<15:8>
A<7:flJ>
D<7:flJ>
ENABLE
R/W
-RESET

SAL<15:8>
DAL<7:flJ>
DAL<7:0>
-CAS
-WT
-BCLR

8
9
9

6
7,lflJ
8
9

Rev D

COMPANY CONFIDENTIAL
Page 18

NOTES:
1. The applicable mode listed for each particular family is only
meant to be a guideline for minimum hardware systems.
It does
not mean to imply that chips from a particular family can only
be used in the mode listed for it.
For example, 898~, 8985 or
68X~~ peripheral chips can be used in any of the dynamic modes
with an overhead of only a few extra gates.
2. AI<6> can be used as Chip Select only if there are less than 2
banks of 4K RAM in the system.
In systems wi th more than 2
banks, the user will have to use decoding logic to generate the
Chip Select signals. Also AI<6> must be gated with the REFRESH
signal to properly refresh the MK4~27s.
3. To synthesize the -WRITE signal in l6-bit mode, the user must
logically NAND the two T-ll signals: PI and an inverted R/-WLB
(and/or R/-WHB depending on which byte(s) are being written).
4. To synthesize the -WRITE signal in 8-bit mode, the user must
logically NAND the two T-ll signals: PI and -RD.
5. Since the MK4~27-3/4 has latched outputs, the user must use
TRI-STATE buffers in interfacing these RAM outputs to the T-ll
Data Bus.
'6. An inverter must be used on
signals logically equivalent.

the

T-ll

output

make

these

7. The 8~8X signal is level sensitive and causes the 8~8X to slip
clock cycles. The T-ll signal is edge sensitive and causes the
T-ll to slip machine cycles.
8. An address low byte that is stable throughout the I/O cycle is
generated by using a transparent octal latch which is clocked
by the assertion of -RAS.
9. To insure timing compatibility for some of the chips in this
family, the length of time this T-ll signal is asserted must be
increased by either asserting the -READY line or by operating
the T-ll at a slower frequency.
l~.

When asserted, this signal must be
input into the T-ll.

COMPANY CONFIDENTIAL
Page 19

inverted to

be an active

2.4

Pinout

1
<--->1
1
DAL14 <--->1
1
DAL13 <--->1
1
DAL12 <--->

DAL1S

1
1<---- VCC
1
39 1<---> AI7
1
38 <---> AI6

<---> AIS

1
2

DAL11

<--->

<---> AI4

DAL19

<--->

<---> AI3

DAL9

<--->

<---> AI2

BGND ---->

<---> All

DAL8

<--->

1<---> AI9

DAL7

<--->

T-11

----> PI

D~L6

<--->

caIP

----> -CAS

DALS

<--->

-RAS
---->
.

DAL4

<--->

----> R/-WLB

DAL3

<--->

----> R/-WHB

DAL2

<--->

<---- READY

DALI

<--->

DAL9

<--->

-BCLR <----

PUP ---->

GND ---->

----> SEL9
1
24 1----> SELl
1
23 1<---> XTL9
1
22 1<---- XTL1
1
21 1----> COUT
1
1
25

Rev B

COMPANY CONFIDENTIAL
page 29

2.5

T-l1 Block Diagram

INSERT DIAGRAM

COMPANY CONFIDENTIAL
Page 21

___4______~______~3______~I,LJL.~~~I=.-.=.l9~12~1

___________

_''''r'''~I~''''~·.I·ir.r.·H'·''· "IUt~ UI mf

n ,,~, ~~':..

": (', . 1I"f' ,

I I ' l l i ' · I •...• ,'II'I'.t.

'11 ._.' 1(1" .N!! !JWJ.

,II'O),"u:'f,,""'.\ltIIIll'I

f.,'J.·."'il .• ··,r.'.I .., """,,._·IIII('V.1.<.:lto!'

, 'II: .. ',.,-j; I'I~I! II'" r!'~' . ,',

I
b

C:!! o" ...... 1 (;'"

• ~;;'JI" ',"\II~IoI[/H ~ll.TlOII""

Rrt
R1

p ~

R 2.
R3

o N
lL& -

E TR

~f)RE~S

Rf.&lSTf..,:(

CLOGK

'"
(10)

1""-- ~EfRES"

_
_

XTLO

I"ST~UC Tl ')N

(It.

REGIsr£r!'

EXECUTION .___

v _____ .... -~
(6)1

{J
ADDRESS

. - . : l J~l ,

c-~-D---]
I

Iil
HOPE RE<TrSTER
J)

r1ULTIPLOER

(8) I

-DMR

-HLT

-p~

1 Ii
'"

A1,·<I')

AI<!·:7)

CONTROL

P"'T~/"'OD
e.UFF E

INTERNAL

EHCUTJON

(11)1

EX E C uTI ON

BUFFE.RS

RESJtITUES" (8)

(!)

U
ADPRESS/ I NTE RRVPl

xTLl

- -----

COUNTER

v
COUT

---

(>oj

,...,

8UFHltS

:-'----

) ARITIHfETIC -

(HI

(16)

R4
( ")
R5
R 6 (SP)/h'
R7 (pC), •• 1

R 0

(Ito)

,,----._-

0 "T/I./ADDR£SS

(8)

eu,.fI'ER.

Ii'I

,-~

-c p(3:¢>
-vEe

AI(I!5')
/'

Ii!I
...V

5-AUG-80
flHST USEO ON

-:'c'~"-'-:c:-:-_-+_-fT1T'..E T-11 BLOCK
fr .. ;:

;".,

'~~'~.-.,-.,- ' - - - j

DTAGP.AM

2.6

Instruction Set
SOP
CLR (B)
COM (B)
INC (B)
DEC (B)
NEG (B)
ADC(B)
SBC (B)
TST(B)

PC MOD

DOP

ROR(B)
ROL(B)
ASR (B)
ASL(B)
SWAB
SXT
MTPS
MFPS

MOV(B)
CMP(B)
BIT(B)
BIC(B)
BIS (B)
ADD
SUB
XOR

B(XX)
SOB
JMP
JSR
RTS
RTI
RTT

EMT
TRAP
BPT
lOT

MISC
S(CC)
C(CC)
HALT
WAIT
RESET
NOP
MFPT*

Addressing Modes
Mode

Name

fI
1
2

REGISTER
REGISTER DEFERRED
AUTO-INCREMENT
AUTO-INCREMENT DEFERRED
AUTO-DECREMENT
AUTO-DECREMENT DEFERRED
INDEX
INDEX DEFERRED

3
4

5
6
7

*Note:

T-ll processor code is 4.
Rev A

COMPANY CONFIDENTIAL
Page 22

3.0

D.C. CHARACTERISTICS

3.1

Absolute Maximum Ratings
Pin voltages
Operating Junction Temperature Range
Storage Temperature Range
Power Dissipation
Chip Ambient Temperature Operating Range

-0.5 to +7V
o to 190 degrees C
-55 to +125 degrees C
1.1 watt
o to 70 degrees C

Notes:
Stress greater than those listed may cause permanent
damage to the device. Exposure to the absolute maximum rating
conditions for extended periods may affect device reliability.
Currents sourced by the DC3l0 are indicated by a negative
prefix to the value listed.
3.2

Static Characteristics
(TA = 0 C to 70 C, VCC = 5.0V +/- 5%, VSS = 0V)

Max

Units

Comments &
Conditions

(Low Input) Tri-State
Leakage Current on
DAL<0:15>

-50

VIN = 0.4V

IlL

(High Input) Tri-State
Leakage Current on
DAL<0:l5>

+10

VIN = VCCMAX

IIH

(MIN) Input Current for
Internal Pull ups on
AI<0:7>, DAL<0:2,7:l5>,
READY

VIN = 0.4V

IIH

(MAX) Input Current for
Internal Pullups on
AI<0:7>,DAL<0.2,7:15>
READY

-0.1

VIN = 0.4V

IXLIH

Input High Current on
XTALI

+700

2.4<VIN(VCC,
X TAL 0
Grounded

IXLIL

Input Low Current on
ITALI

-6.4

-0.5V<VIN<+0.6\
XTAL0 Grounded;

Symbol

Parameter/Pins

IlL

Min

-0.1

Rev E

COMPANY CONFIDENTIAL
Page 23

~ommen1;.::;

Symbol

Parameter/Pins

lee

Power Supply Current
on VCC

VIH

Input High Voltage on
READY, DAL,0:15>,
AI(S:7>

2.S

VCC

VIHPUP

Input High Voltage on
PUP

2.2

VCC

Input Low Voltage on
READY, DAL(S:lS>,
AI(S.7>

-S.5

VILPUP

Input Low Voltage on
PUP

-S.5*

VOH

Output High-Voltage
for DAL(S:lS>, COUT,
PI, SELl, SELS

2.4

VOHA

Output High Voltage
for AI(S:7>

2.6

VOHB

Output High Voltage
for BCLR

2.2

VOHe

Output High Voltage
for -RAS, CAS,R/-WLB,
R/-WHB
-

2.8

lOB = -7SS uA t

VOL

Output Low Voltage for
DAL(S:IS>, AI(S:7>,
COUT, PI, SELl, SELS
BCLR, RAS, CAS, R/-WHB,
R/-WLB

9.4

IOL = 3.2 mA

eIN

Input Capacitance for
READY, OAL(S:lS>,
AI(S:7>

eOUT

Output Capacitance for
Tri-State Load Calculation
on DAL(S:15>,

VIL

Min

Max

+9.8

UnitS

Conditions

Static,
TA = S e

I
I

+S.6

I
I
lOB = -7SS uA I

I
I
I
lOB = -7SS uA I
IOH = -7SS uA,I
Terminated to I
VSS (Ground) I
with 1 K
I
percision
Resistor of 1%1
accuracy.
I

I
t

AI(S:7>,COUT,PI,SELl~SELS,

BCLR,RAS,CAS"R/-WHB,R/-WLB

-S.5V on input pins allows for ringing on unterminated lines
RevE
COMPANY CONFIDENTIAL
Page 24

4.~

A. C. CHARACTERISTICS

4.1

Bus Timing Annotated for Maximum XTL1,

XTL~

Operating Frequency

(TJ = ~ to l~~oC, VCC = 5.~V +/-5% VSS = ~.~V)

Comments &
Conditions

Symbol

Parameter

fOP

XTL1,

tAFP

Column Address on AI<7:~>
Float to PI (L.E.)

min

AI<7:8> Float to DNA Select
on SEL<~>

min

Column Address on AI<7:8> Hold
Time from -CAS (L.E.)

T - 43 = 98 ns

min

Row Address on AI<7:8> Hold
Time from -RAS (L.E.)

T -

= 73 ns

min

Column Address on AI<7:8> Set
Up Time to -CAS (L.E.)

20 ns

min

Row Address on AI<7:0> Set Up
Time to -RAS (L.E.)

T - 83 = 50 ns

min

T-11 -BCLR Pulse Width on
a Reset instruction

(84T) ns

min

-BCLR Set Up Time to Mode Bits
on DAL<15.~> Valid Following
a RESET Instruction

(74T) ns

max

= 310 ns

min (4)

tAFS
tAHC
tAHR
tASC
tASR
tBCR
tBMR

XTL~

Function of tCYC
Operating Frequency

tCAS

-CAS Pulse Width

tCDE

-CAS (T.E.) or Delayed Mode
R/W (T.E.) to next DAL <15:0>
Address Enable

tCPR

-CAS Precharge Time

tCRD

-CAS (L.E.) or Delayed Mode
R/W (L.E.) to Read Data
Valid

max
min (11)

7.5 MHz
~.l MHz

(3T - 90)

T - 18 = 115 ns

min

(3T - 5)

= 395 ns

min

(3T - l88)

= 228 ns

max (4)
Rev E

COMPANY CONFIDENTIAL
Page 25

tCSP

tCSR
tCWD

-CAS (L.E.) or Delayed Mode
R/W (L.E.) Set Up Time to
PI (L.E.)

(T - 28) = 135 ns

-CAS (L.E.) Set Up Time to
-RAS (T .E.)

(3T - 43)

= 363 ns

min
min (4)

-CAS (L.E.) or Delayed Mode
R/W (L.E.) to Write Data
Valid

83 ns

max

tCYC

XTL1, XTL3 Operating Period

T = 133 ns

min

tDFB

DAL<15:3>Float from -BCLR (L.E.)

tDFC

DAL<15:3> Address Float to
-CAS (L.E.) or Delayed Mode
R/W (L.E.)

3 ns

min

DAL<15:3> Float to DMA Select
on SEL<3> (L.E.)

3 ns

min

tDFS
tOHN

tOHR
tDRD
tDSC

tOSE
tDSP
tDSR
tFFR

153 ns

max (13)

DAL<15:3> Address Hold Time
from Normal Mode Control
Strobe (L.E.)

(2T - 23)

= 247 ns

min

DAL<15:3> Address Hold Time
from -RAS (L.E.)

(T - 12) = 121 ns

min

DAL<15:3> Address Set Up Time
to Read Data Valid
(5T - 157)

= 513 ns

max (4)

DAL<15:3> Address Set Up Time
to -CAS (L.E.) or Delayed
Mode R/W (L.E.)

(2T - 22) = 245 ns

min

DAL<15:3> Enable from DMA
Select on SEL<l> (T.E.)

(T - 27)

= 136 ns

min

DAL<15:3> Address Set Up Time
to PI (L.E.)

(3T - 23)

= 383 ns

min

OAL<15:3> Address or DAL<15:8>
IACK information Set Up Time
to -RAS (L.E.)
(T - 48) = 85 ns
Refresh or Fetch on SEL3(L.E.), Set Up
Time to -RAS(L.E.)
(T - 23) = 113 ns

min

tFRP

Refresh -RAS Pulse Width

(2T + 35)

= 332 ns

min

tFSP

Refresh Select on SEL<3>
Pulse Width

(4T - 23)

= 513 ns

min
Rev E

COMPANY CONFIDENTIAL
Page 26

tIHP
tISP
tKDS

Interrupt or DMA Input on AI<7:0>
Hold Time from PI (T.E.)
PI (L.E.) to Interrupt or
DMA Input on AI<7:0> Valid

0 ns

(2T - 167)

= 100 ns

Vector Data on DAL<7:2> Hold
Time from lACK Select on
SEL<l> (T.E.)

min
max (4 )

0 ns

min

lACK Information on DAL<15:8>
Hold Time from lACK Select
on SEL<l> (T.E.)

(T - 50)

= 83 ns

min

lACK on SELl (L.E.) Set Up
Time to -RAS (L.E.)

(T - 63)

= 70 ns

min

lACK -RAS (L.E.) to Vector
Data on DAL<7:0> Valid

(2T - 148)

= 119 ns

max (4)

tKRP

lACK -RAS Pulse Width

(2T + 35)

= 302 ns

min (4)

tKSD

lACK Select on SEL<l> (L.E.) to
Vector Data on DAL<7:2>
Valid
(3T - 155)

= 245 ns

max (4 )

lACK Select on SEL<l> Pulse
Width

= 334 ns

min (4)

49 ns

min

0 ns

min

= 143 ns

min

0 ns

min

tKHS

tKKR
tKRD

tKSP
tLPO

tMHB
tMOC

tMOR

tMPO

tMRC
tMRO

(3T - 66)

DMA or Long Micro Cycle PI
(L.E.) Set up time to Constant
(T - 84)
Mode COUT (T. E. )
Mode Input on DAL<15:0> Hold
Time From -BCLR (T.E.)
ASPI or DMA Pulse Mode COUT
(T. E. ) Set up Time to -CAS
(L.E.)

(T + 10)

Read/Write or DMA Pulse Mode
COUT (L.E.) Set Up Time to
-RAS (L.E.)
DMA or Long Micro Cycle PI
(L.E.) Set Up Time to Pulse
Mode COUT (L.E.)

(2T - 84)

= 183 ns

min

DMA Select -RAS (L.E.) Set Up
Time to -CAS (L.E.)

(2T + 10)

= 277 ns

min

Read/Write or DMA Pulse Mode
COUT (T. E. ) Hold Time from
-RAS (L.E.)

(T - 51)

= 82 ns

min
Rev E

COMPANY CONFIDENTIAL
Page 27

tMRP

DMA Select -RAS Pulse Width

(5T + 35) = 792 ns

min (S)

tMSF

DMA Select on SEL<9> Pulse
Width

(ST - 3S) = 1929 ns

mineS) (9)

DMA Select on SEL<l> Pulse
Width

(7T - 6S) = S65 ns

mineS) (9)

Normal Mode R/W Hold Time
from -CAS (T. E.)

(T - 32) = 191 ns

min

Normal Mode R/W Hold Time
from PI (T. E. )

(T - 43) =

99 ns

min

Normal Mode R/W Hold Time
from -RAS (T. E.)

(T - 19S) = 25 ns

min

tNMP

Normal Mode R/W Pulse Width

(6T - 66) = 734 ns

min (4)

tNMR

Normal Mode R/W Recovery Time

tNRD

Normal Mode -RD Strobe Set Up
Time to Read Data Valid
(ST - 14S) = 519 ns

max (4)

tNSC

Normal Mode R/W Set Up Time
to -CAS (L.E.)

(2T - 37) = 239 ns

min

Normal Mode R/W Set Up Time
to PI (L.E.)

(3T - 45) = 355 ns

min

Normal Mode R/W Set Up Time
to -RAS (L.E.)

(T - 78) = 55 ns

min

tMSK
tNHC
tNHP
tNHR

tNSP
tNSR

13 ns

min

(T - 33) = 1913 ns

min

tORD

Pulse Mode COUT Pulse Width
Pulse Mode COUT Recovery
Time when 130 Present

(3T - 37) = 367 ns

min

tORT

Pulse Mode COUT Recovery Time

(2T - 37) -~230 ns

min

tOSC

Pulse Mode COUT (T. E. )
Set Up Time to -CAS (L.E.)

113 ns

min

tPAE

PI (T. E.) to next AI<7:0>
Address Enable

(T - 40) = 93 ns

min

tPBC

T-11 Power Up to -BCLR (L.E.)
Set Up Time

100 ns

max

tPBU

Power Up (T. E.) to -BCLR (T. E.)

99T = 13200 ns
lr30T = 13333 ns

min
max

tOPW

Rev E

COMPANY CONFIDENTIAL
Page 2S

tPCO

Power Up (T.E.) to COUT (L.E.) T + 69 ns = 193 ns

tPFF

Power Up {T.E.} to Beginning of
First Instruction Fetch

tPHC

PI Hold Time from -CAS (T.E.)
or Delayed Mode R/W (T.E.)

295T = 39333 ns
31ST = 42999 ns
10 ns

= 229 ns

max
min
max
min

PI Pulse Width

(2T - 47)

Power Up (T.E.) to Mode bits
on DAL<15:1> valid

74T

max

PI Precharge Time

(4T - 33)

min
max (4)

min (4)

tPRD

PI (L.E.) to Read Data Valid

= 590 ns
(2T - 176) = 91 ns

tPSC

PI (L.E.) Set Up Time to
-CAS (T.E.) or Delayed Mode
R/W (T.E.)

(2T - 75)

= 192 ns

min (4)

PI (L.E.) Set Up Time to
Normal Mode Control
Strobe (T.E.)

(3T - 90) = 310 ns

min (4)

PI (L.E.) Set Up Time to
-RAS (T.E.)

(2T + 14)

tPSN

tPSR
tPUT

Power Up (L.E.) to Output
Pins Preset

tRAS

-RAS Pulse Width

tRDC

Read Data Hold Time from
-CAS (T.E.) or Delayed Mode
R/W (T.E.)

tRDE
tRHC

tRBP
tRHS

tRPR

(4T + 35)

= 281 ns

min

250 ns

max

= 568 ns

min (4)

9 ns

min

= 15 ns

min

-RAS (T.E.) Hold Time from
-CAS (T.E.) or Delayed Mode
R/W (T.E.)

50 ns

min

-RAS (T.E.) Hold Time from
PI (T.E.)

19 ns

min

-RAS (T.E.) Hold Time from
lACK or DMA Select on
SEL<l> (T.E.)

45 ns

min

= 147 ns

min

-RAS (T.E.) to next DAL<15:0>
Address Enable

-RAS precharge Time

(T - 118)

(2T - l2j)

(4)

Rev E

COMPANY CONFIDENTIAL
Page 29

tRRD
tRSC

tRSD

tRSE
tRSP
tRWD
tSFR
tSHF

tSKR
tSPR

-RAS (L.E.) to Read Data
Valid
-RAS (L.E.) Set Up Time to
-CAS (L.E.) or Delayed Mode
R/W (L. E.)

min

o ns

min

(T - 27)

= 106 ns

min

-RAS (L.E.) Set Up Time to PI
(L.E.)

(2T + 10)

= 277 ns

min

-RAS (L.E.) to Write Data
Valid

(2T +

= 270 ns

max

DMA on SEL(0) (L.E.) Set Up
Time to -RAS (L.E.)*

(2T - 23)

= 243 ns

min

Refresh or DMA Select on SEL(0)
(T.E.) Hold Time from -RAS
(T.E.)
(T -123)

= 10 ns

min

DMA Select on SEL(l> (L.E.)
Set Up Time to -RAS (L.E.)

(2T - 63)

= 203 ns

min

lACK or DMA Select on SEL(l>
Recovery Time

(T)

= 133 ns

min

(3T - 38)

= 362 ns

min

o ns

min

100,000 ns

min

83)

= 50 ns

min

Write Data or SAL(15:8> Hold Time
from -CAS (T.E.) or Delayed
Mode R/W (T.E.)
(T - 28)

= 105 ns

min

= 45 ns

min

tSSS

SEL(0) (L.E.) Set Up Time to
SEL(l> (L.E.)

tUPP

T-ll Power Up Time

tWDP

Write Data Set Up Time to
PI (L.E.)
.

(T -

Write Data Hold Time from PI

(T - 88)

(T. E. )

tWHR

max (4)

R/W Driver Enabled from DMA
Select on SEL(l> (T.E.)

Pulse Width on SEL(0)
During Fetch

tWHP

= 405 ns

(T + l0) = 143 ns

R/W Drivers disabled and Passive
Pull Up Enabled Set Up Time to
DMA Select on SEL(0) (L.E.)

tSSF

tWHC

(4T - 128)

SAL(15:8>, Write Data, or
lACK Information Hold Time
from -RAS (T.E.)

J
(T - 118)

= 15 ns

min

*On R/W SEL0 set up time to RAS is T-23
Rev E
COMPANY CONFIDENTIAL
Page 30

tWSC

Write Data Set Up Time to -CAS
(T.E.)
(3T - 15r1J) = 25rIJ ns

min (4)

tWSP

Write Data Set Up Time to PI
(T.E.)

(3T - 11r1J) = 29rIJ ns

min (4)

tWSR

Write Data Set Up Time to
-RAS (T. E.)

(3T - 55) = 345 ns

min (4)

tYHC

READY (L. E.) Hold Time from
COUT (T. E. )

rIJ ns

min (6)

tYPW

READY Pulse Width

6rIJ ns

min (5)

tYRT

READY Recovery Time

6rIJ ns

min (6)

tYSC

READY (L.E. ) Delay from -CAS
(L.E.)

(2T - 135) = 132 ns

max (5)

tYSO

READY (L.E.) Delay from
Pulsed Mode COUT (T.E.)

(2T - 127)

= l4rIJ ns

max (5)

READY (L.E.) Delay from -RAS
(L.E.)

(3T - lr1JrIJ)

= 3rIJrIJ ns

max (5)

tYSR
NOTES:
1.

Timings are measured at the following output voltages:
-RAS, -CAS, R/-WLB
& R/-WHB
VOL = rIJ.8V
VOH = 2.4V
AI<7:8>
VOL = rIJ.8V
VOH = 2.2V
All others
VOL = rIJ.8V
VOH = 2.rlJV
Noise Hazard Timing:
t{8.8V - rIJ.4V) = 12 ns max
t(2.rlJV - 2.4V) = 1rIJ ns max
t(2.2V - 2.6V) = 11 ns max
t{2.4V - 2.SV) = 12 ns max

Output timings are measured using a purely capacative load of 8rIJ
pf. For loadings other than SrIJ pf use the following correction
factors:
8r1Jpf < CL < 2rIJrIJ pf
+rIJ.3 ns/pf
25pf < CL < SrIJ pf
-rlJ.3 ns/pf

T = l/fop
L.E. => Leading Edge
T.E. => Trailing Edge

Add T ns if in long bus cycle mode, then if ROY slips are
initiated, add H*T ns, where:
T = l/fop, H = number of ROY pulses times 3 if mode = normal,
times 4 if mode = long bus cycle.
Rev E

COMPANY CONFIDENTIAL
Page 31

READY is an edge-triggered input that is usually activated by
asserting a low on its pin. However, READY is internally
activated by the leading edge of -RAS if its pin has been
asserted low before these edges.

These timing parameters apply only to cases where multiple READY
pulses are required, i.e. multiple microcycle·slips.

Asserting PUP high will leave all registers, including the
POP-II General Purpose Registers (R9 thru R7) in an
indeterminate state except for Mode Reg <1> force to normal
micro cycle.

Add 4T for each Ready pulse.

Add BT if multiple DMA cycles are granted.

19.

-BCLR may be used to gate mode input during RESET.
violated on DAL<15:B,1:8> only.

11.

If external TTL clock is used, tCYC min is 9Hz (i.e. DC) since
the T-1l is a static part.

TDFB may be

Rev E

COMPANY CONFIDENTIAL
Page 32

4.2

Crystal Specification

Symbol

Parameter

Min

Max

Units

Conditions

FREQ

Frequency

".1

7.5

MHz

Rs
Cp

Mode
Spurious Mode
Series Resistance
Parallel Capacitance

+1-0.81%0
o to 70 C

Fundamental
To Be Determined
To Be Determined
To Be Determined
Rev E

COMPANY CONFIDENTIAL
Page 33

4.3

Timing Diagrams
INSERT TIMING DIAGRAMS

COMPANY CONFIDENTIAL
Page 34

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T-ll BLOCK DIAGRAM

H1 REFRESH,IACK TIMING

T-ll ASPI CYCLE (ASSERT PRIORITY IN)

H1 BUS NOP (NO TRANSACTION ON BUS)

T-l1 DMA TIMING

T-U READY TIMING

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t~~p

y..----+--- t DSP

1!------t1,tp-----+-'--lI

tpn, -l

R/iJ

-1--

~----_+_+----r-------------+t__-~t_--

r-----------------ff-----tNMP----------~------~

(DELAYED MODE)

*SEE NOTE 't

SEL eI

1: DALU5:81 IN SBIT MODE,WILL CONTAIN THE HIGH BYTE ADDRESS WORD FOR THE ENTIRE BUS CYCLE, IN 16BlT MODE BYTE OPERATIONS, DAL BYTE NOT BEING
S't<rNAL IN 8 B:tT Moel (Nocr'll'.)
ADDRESSED WILL DRIVE INDETERMINATE DATA.
SUNH IN a en MOD~ (D~LAYED)
NOTE 8: IN 8 BIT MODE WORD OPERATIONS,TWO BYTE TRANSACTIONS ARE
Non 'I: Rji;{ (DI'Ayo~MoD') If .. ''''f TIMrN" A. -CAS
DONE, THE FIRST TO THE LOW BYTE (ADDRESS ON DAL<0>:0) THE
NOTE 5: ONLY Dua..NGo FETGH, IN A~,- MODES E lCC:5"PT 41</161< t>YN"MI4
SECOND TO THE HIGH BYTE (ADDRESS ON DAL<0>=11.
NOTE 6: DURING A WRITE CYCLE,ONLY THE DMR IS ACCEPTED BY THE CHIP,
NOTE ~: PULSE MODE CLOCK.
INTERRUPTS ARE NOT ACCEPTED,
NOTE 7: EXCEPT DURING STACK OPERATIONS,ALL WRl TE TRANSACTIONS
ARE PRECEEDED BY READS,

NOn.

NOTa 4: -RI>
NOTE 3: -RD

r:r-

ill- -

.Ii :
I

I 5-,.........
.u.~

-MAR-82
DRN.

fiRST USIDO~

r: ",1. F

CHK'O

ENG·IWIT...: .... ;

"01 IJJ. 'If

TITLE

'ROJ. ENG. Re'O

11 YoJl ')'

'ROD
NEXT HIGHi" ASSY,

"-;;::;;-;------1 SIDlE rOOf

I SCALE
SHEET

OIST.

-11

IHAD/vJP-.:T£
T:"11N::-

APPENDIX A
T-ll INSTRUCTION EXECUTION TIMES AT MAXIMUM OPERATING FREQUENCY
The following pages contain charts that give execution times for
all instructions executable by the T-ll. The charts are organized
to help those individuals who want to calculate program execution
times.
To do such a calculation, first choose your system
configuration and then outl ine that column in the charts.
Use
only those execution times listed in the outlined column.
The
possible system configurations are:
1.
2.
3.
4.

16 bit mode--REFRESH on;
16 bit mode--REFRESH off;
8 bit mode--REFRESH on;
8 bit mode--REFRESH off.

Since a REFRESH cycle adds a small increment of time to the
machine cycle, and since in 8 bit mode REFRESH is done everyl
instruction cycle and addressing mode 5, 6, or 7 I/O and trap (2 I
occurances) it is possible for an instruction to have varyingl
execution times when REFRESH is on. This is why you will find MIN
and MAX execution times for all (in 16 bit mode REFRESH is donel
every other) "REFRESH on II configurations.
You can calcul ate I
program execution times for "REFRESH on" configurations by summing
the average of the MIN and Max execution times.
I
The following notes apply to all instruction execution charts:
1. All times are in microseconds.
2. Add 0.4 us for every -READY pulse during an I/O
transaction.
3. Operating frequency is 7.5 MHz. To calculate instruction
execution times (lET) at different operating frequencies
use the following formula:
IET(fOP)

= (7.5 MHz/fOP) * IET(7.5)

Where:
lET (fOP) = Instruction
frequency, fOP.

Execution

Time

for

the

new

fOP = The operating frequency at which the instruction
execution times are needed.
IET(7.5) = Instruction Execution Times with an operating
frequency of 7.5 MHz. These times are listed
in the following charts.
4. NA =>Not Applicable
NOTE:

Times calculated using Revision 5.18 Microcode
Rev B
COMPANY CONFIDENTIAL
Page A-I

XOR & SINGLE OPERAND INSTRUCTIONS
======~==========================

INSTRUCTIONS

I
16 BIT MODE
I
8 BIT MODE
1------------------1--------------------------------------I
I REFRESH ON
I
REFRESH ON
I REFRESH OFF
IDESTI------------ REFR 1--------------------------------------I MODE I
I
OFF I
I
WORD
BYTE
I WORD I BYTE I
I
I
I
I
I
I MIN I MAX
I INSTR
I
INSTR
I INSTRI INSTRI

==============1====1=====1====== =====1============1============1======1======
I
CLR(B) ,COM(B),I 0
INC(B) ,DEC(B), I 1
NEG(B),ROR(B),12
ROL (B) , ASR (B) , I 3
AS L (B) , SWAB,
I 4
ADC (B) , SBC (B) , I 5
SXT,MFPS,
16
XOR
I 7

I
I
I 1.6 1 1.73
I 2.8 I 2.93
12.8 I 2.93
I 3.6 I 3.73
I 3. 2 I 3.33
I 4.131 4.26
14.1314.26
I 4.931 5.06

I
1.6 I
2.8 1
2.8 I
3.6 I
3. 2 I
4.0 1
4.0 I
4.8 I

2.53
5.33
5.33
6.93
5. 73
7.46
7.46
9.06

I
I
I

I
I
I
1

I
I
I

2.53
3.73
3.73
5.33
4. 13
5.86
5.86
7.46

I
1
1
I

2.4
5.2
5.2
6.8
5.6
7•2
7.2
8.8

2.53
3.33
3.33
4.93
3.73
5.46
5.46
7.06

I
I
I
I
I
I
I
I

2.4
4.0
4.0
5.6
5.2
6.0
6.0
7.6

4.0
4.8
4.8
6•4
5.2
6.8
6.8
8.4

I
I
I
I
I
I
I
I
I

2.4
3.6
3.6
5.2
4 •0
5.6
5.6
7.2

==============1====1=====1====== =====1============1============1======1=====
I 0
1
2
3
4
5
6
7

TST(B)

I 1.6 I 1.73

I 2.4 I 2.53
I 2.4 I 2.53

3.2 I 3.33
I 2.8 I 2.93
I 3.731 3.86
1 3.731 3.86
14.5314.66
1

1.6
2.4
2.4
3.2
2.8
3.6
3.6
I 4.4

I
I

2.53
4.13
4.13
5.73
5.33
6.26
6.26
7.86

4.13
4.93
4.93
6 • 53
5.33
7.06
7.06
8.66

I
I
I
I

I
I
I
I
I
I

I
I

I
I
I
I
I
I

2.4
3.2
3.2
4.8
3.6
5.2
5.2
6.8

============== ====1=====1======1=====1============1============1======1=====
o

1
2
3
4
5
6
1 7

MTPS

I 3.2 I
I 4.0 I
1 4.0 I
I 4.8 I
I 4.4 I
1 5.331
1 5.331
1 6.131

3.33
4.13
4.13
4.93
4.53
5.46
5.46
6.26

I 3.2 I

I 4.0 I
I 4.0 I
I 4 .8 I
I 4.4 I
1 5.2 1
1 5.2 I
1 6.0 1

I
1
I
I

4.13
4.93
4.93
6 • 53
5.33
7.06
7.06
8.66

I
I
I

I
1

I
I

I
I
I

I
I

4.0
4.8
4.8
6 •4
5.2
6.8
6.8
8.4

==============1====1=====1======1=====1============1============1======1=====
NOTES:

XOR and Single Operand Instruction execution times include
instruction fetch, instruction decode, operand fetch, instruction
operation and result output (except in Mode 0 and the TST(B)
instruction where there is no output).
Rev B

COMPANY CONFIDENTIAL
Page A-2

DOUBLE OPERAND INSTRUCTIONS

-----------------------------------------------------

******************************************************************************

*
* (DOUBLE OPERAND EXECUTION TIME) = (SOURCE MODE TIME) + (DESTINATION MODE
*
TIME)
*

*
*
*
*

******************************************************************************

SOURCE MODE TIME
I
16 BIT MODE
I
8 BIT MODE
1-------------------------------1-------------------------I
REFRESH ON
1
1 REFRESH ON 1 REFRESH OFF
ISRC 1------------------------1 REFR 1-------------------------INSTRUCTIONS IMODEI DST MODE IDST MODE
I OFF 1
1
I
I
I
0-4
1
5-7
1
IWORD I BYTE I WORD 1 BYTE 1
IINSTRIINSTR I INSTRI INSTRI
I
I MIN I MAX I MIN I MAX I
=============1====1=====1======1=====1=====1======1=====1======1======1======
1
I
I
I
1
1
1
I
I
I
1 0 1 1.2 1 1.33 1 1.331 1.331 1.2 12.13 1 2.13 I 2.0 1 2.0
I 1 1 2.0 I 2.13 1 2.131 2.131 2.0 13.73 I 2.93 I 3.6 I 2.8
MOV (B) , CMP (B) , 1 2 1 2.0 I 2. 13 1 2. 13 1 2.13 1 2.0 13 .73 1 2.93 1 3.6 1 2.8
ADD,SUB
13 12.812.9312.9312.9312.8 15.33 I 4.53 I 5.2 I 4.4
BIT(B) ,BIC(B),I 4 I 2.4 I 2.53 I 2.531 2.531 2.4 14.13 I 3.33 I 4.0 I 3.2
BIS(B)
1 5 I 3.331 3.33 1 3.331 3.461 3.2 15.86 I 5.06 I 5.6 1 4.8
1 6 I 3.331 3.33 I 3.331 3.461 3.2 15.86 I 5.06 I 5.6 I 4.8
I 7 1 4.131 4.13 1 4.131 4.261 4.0 17.46 I 6.66 I 7.2 I 6.4
==============1====1=====1======1=====1=====1======1=====1======1======1=====

NOTES:

Source Mode times include instruction fetch, instruction decode
and source operand fetch.

Rev B

COMPANY CONFIDENTIAL
Page A-3

DESTINATION MODE TIME

INSTRUCTIONS

I
16 BIT MODE
I
8 BIT MODE
1------------------1--------------------------------------I REFRESH ON I
I
REFRESH ON
I REFRESH OFF
DESTI------------IREFR --------------------------------------MODEl
I OFF
I
WORD
BYTE
I WORD I BYTE
I
I
I MIN
MAX
I
INSTR
1
INSTR
1 INSTRIINSTR I

============== ====1===== ======1===== ============1============ ======1======
MOV(B) ,ADD,
SUB,BIC(B)
BIS(B)

13
1
2
3
4
5
6
7

13.4
1.6
1.6
2.4
2.0
2.8
2.8
3.6

I
I
I

0.4
1.2
1.2
I 2.0
I 1.6
I 2.4
I 2.4
I 3.2 I

0.4
1.2
1.2
2.0
1.6
2.4
2.4
3.2

0.4
1.2
1.2
I 2.0
I 1.6
1 2.4
I 2.4
I 3.2

I
I
I
I
I
I
1

I
I
I
I

13.4
1.6
1.6
2.4
2.0
2.8
2.8
3.6

13.4
2.4
2.4
4.0
2.8
4.53
4.53
6.13

1
1
1
1

13.4
1.6
1.6
3.2
2.0
3.73
3.73
5.33

13.4
2.4
2.4
4.0
2.8
4.4
4.4
6.0

0.4
I
2.0
I
2.01
3.6
I
2.4
1
4.13
1
4.13
I
5.73
I

0.4
1.2
1.2
2.8
1.6
3.33
3.33
4.93

13.4
2.0
2.0
3.6
2.4
4.0
4.13
5.6

I
1
1

1
1
I

I
I
I
1

0.4
1.6
1.6
3.2
2.0
3.6
3.6
5.2

============== ====1===== ======1===== ============1============ ======1=====
o

~MP (B) , BIT (B)

1
2
3
4
5
6
I 7

I
I
I

I
1
I

I
I
I

I
1

0.4
1.2
1.2
2.8
1.6
3.2
3.2
4.8

==============1====1=====1======1===== ============1============1======1=====

NOTES:

Destination Mode times include destination operand fetch,
instruction operation and resul t output (except in Destination
Mode 0 and the CMP (B) and BIT (B) instructions where there is no
output) •
Rev B

Rev B

COMPANY CONFIDENTIAL
Page A-4

I
1

I
I

I
I
1

rUMP & SUBROUTINE INSTRUCTIONS
=============================

1
16 BIT MODE
1
8 BIT MODE
1------------------1--------------------------------------1
1 REFRESH ON 1
1
REFRESH ON
1 REFRESH OFF
IDESTI------------IREFR 1--------------------------------------INSTRUCTIONS 1MODE 1
1
1 OFF 1
1
1
1
1
1
1
WORD
BYTE
1 WORD 1 BYTE
1
1 MIN 1 MAX 1
1
INSTR
1
INSTR
1 INSTR 1 INSTR 1
==============1====1=====1======1=====1============1============1======1======
1
1
1
1
1
1
1
1
1 1 1 2.0 1 2.13 1 2.0 1
2.93
1
NA
1 2.8 1 NA
1 2 1 2.4 1 2.53 1 2.4 1
3.33
1
NA
1 3.2 1 NA
\ 3 \ 2.4 \ 2.53 1 2.4 \
4.13
\
NA
1 4.0 1 NA
JMP
1 4 \ 2.4 \ 2.53 1 2.4 \
3.33
1
NA
1 3.2 1 NA
\ 5 \ 2.93\ 2.93 \ 2.8 \
4.53
1
NA
\ 4.4 1 NA
\ 6 \ 2.931 2.93 \ 2.8 1
4.53
\
NA
\ 4.4 1 NA
\ 7 1 3. 731 3. 73 \ 3.6 1
6.13
\
NA
1 6.0 1 NA 1
==============1====1=====1======1=====1============\============1======1======
1 1 1 3.6 1 3.73 1 3.6 1
5.33
1
NA
I 5.2 1 NA 1
5.73
1
NA
1 5.6 1 NA 1
1 2 1 4.0 1 4.13 1 4.0 1
1 3 1 4.0 1 4.13 1 4.0 1
6.53
1
NA
I 6.4 I NA 1
JSR
1 4 1 4.0 1 4.13 1 4.0 1
5. 7 3
1
NA
1 5.6 1 NA 1
1 5 1 4.531 4.53 \ 4.4 1
6.93
1
NA
1 6.8 1 NA 1
\ 6 1 4.531 4.53 1 4.4 1
6.93
\
NA
1 6.8 1 NA 1
8.53
1
NA
1 8.4 1 NA \
1 7 1 5.331 5.33 \ 5.2 1
==============1====1=====1======\=====1============1============1======1======
RTS
1 NA 1 2.8 \ 2.93 1 2.8 1
4.53
1
NA
1 4.4 1 NA 1
==============1====1=====1======1=====1============1============1======1======
SOB
1 NA \ 2.4 1 2.53 1 2.4 1
3.33
1
NA
1 3.2 \ NA \
==============\====\=====\======1=====\============\============\======\======
NOTES:

1. JMP/JSR Destination Mode 0 is an illegal instruction that traps
to vector location 10.
2.

JMP execution times include instruction fetch,
decode, operand fetch and loading of the PC.

instruction

JSR execution times include instruction fetch, instruction
decode, operand fetch, pushing the 1 inkage register onto the
stack and loading the PC.

RTS execution times include instruction fetch, instruction
decode, loading the PC and popping the stack and loading the
linkage register.

SOB execution times include instruction fetch, instruction
decode, decrementing the count register, testing for zero and
branching if necessary (NOTE: whether or not a branch is taken
does not affect the execution time).
Rev B
COMPANY CONFIDENTIAL
Page A-5

BRANCH, TRAP & INTERRUPT INSTRUCTIONS
=====================================

1
16 BIT MODE
1
8 BIT MODE
1------------------1--------------------------------------1
1 REFRESH ON 1
1
REFRESH ON
1 REFRESH OFF
IDESTI------------IREFR 1--------------------------------------INSTRUCTIONS 1MODE 1
1
1 OFF 1
I
WORD
BYTE
I WORD 1 BYTE
1
1
I
1
1
I
1 MIN 1 MAX 1
1
INSTR
1
INSTR
1 INSTR 1 INSTR I
==============1====1=====1======1=====1============1============1======1======
1
1
1
1
1
1
1
1
BR,BNE,BEQ,
I
1
I
1
1
I
1
1
BPL,BMI,BVC,
I
1
1
I
1
I
I
I
BVS,BCC,BCS, 1 NA 1 1.6 1 1. 73 1 1.6 1
2.53
1
NA
1 2.4 I NA
BGE,BLT,BGT,
I
I
1
I
I
I
I
1
BLE,BHI,BLOS, I
I
I
1
1
I
1
I
BHIS,BLO
1
1
I
1
I
1
I
I
==============1====1=====1======1=====1============1============1======1======
INA 16.5316.6616.4 I
9.73
1
NA
1 9.6 I NA II
EMT,TRAP,
BPT , IOT
1
I
1
I
1
1
I
1
==============1====1=====1======1=====1============1============1======1======
tTI
I NA 1 3.2 I 3.33 I 3.2 I
4.93
I
NA
I 4.8 1 NA 1
==============1====1=====1======1=====1============1============1======1======
RTT
I NA 1 4 • 4 1 4. 5 3 I 4 • 4 I
7 • 13
1
NA
I 7 • 0 I NA 1
==============1====1=====1======1=====1============1============1======1======

NOTES:

1. Branch instructions execution times include instruction fetch,
instruction decoding, doubling the offset, testing the conditions
and adding the offset to the PC if the conditions are met
(NOTE: Whether or not a branch is taken does not affect the
execution times).
2.

Trap instructions execution times include instruction fetch,
instruction decode, pushing the PS and PC onto the stack, loading
the PC with the contents of the vector location and loading the
PS with the contents of the vector location plus two.

Return from interrupt instructions execution times include
instruction fetch, instruction decode and popping the PC and PS
from the stack.
Rev B

COMPANY CONFIDENTIAL
Page A-6

& CONDITION CODE INSTRUCTIONS
==========================================

~ISCELLANEOUS

1
16 BIT MODE
1
8 BIT MODE
1------------------1--------------------------------------1
1 REFRESH ON
1
REFRESH ON
1 REFRESH OFF
IDESTI------------ REFR 1--------------------------------------INSTRUCTIONS 1MODE 1
1
OFF I
1
WORD
BYTE
1 WORD 1 BYTE
1
I
1
I
1
I MIN I MAX
I
INSTR
1
INSTR
I INSTRI INSTRI
==============1====1=====1====== =====1============ ============1======1======
1
1
I
I
1
1
HALT
I NA 1 5.731 5.86
5.6 I
8.4
NA
1 8.0 I NA 1
============== ====1=====1====== =====1============ ============1======1======
WAIT
NA I 1.6 I 1.73
1.6
2.43
NA
I 2.4 I NA 1
============== ====1=====1====== ===== ============ ============1======1======
RESET
NA 114.6 114.73 14.6
16.53
NA
I 16.4 I NA I
============== ====1=====1====== ===== ============ ============1======1======
NOP
NA 1 2.4 I 2.53
2.4
3.33
NA
I 3.2 1 NA 1
============== ====1=====1======1===== ============ ============1======1======
CLC,CLV,CLZ,
I
I
I
1
1
CLN,CCC,SEC,
NA I 2.4 1 2.53 1 2.4
3.33
NA
1 3.2 I NA
SEV,SEZ,SEN,
1
I
1
1
I
SCC
I
I
I
I
I
I
.============= ====1=====1======1===== ============1============1======1======
iFPT
NA I 2.0 I 2.13 I 2.0
2.93
I
NA
1 2.8 I NA
I
============== ====1=====1======1===== ============1============1======1======
NOTES:

HALT execution times include instruction fetch, instruction
decode, writing the PC & PS into stack then loading the PS withl
340 and loading the PC with the RESTART address.

WAIT execution times include instruction fetch, instruction
decode, pulsing PI to sample the interrupt lines and doing a
REFRESH cycle if REFRESH is on.
(NOTE: If no interrupt lines
were sensed by the T-ll to be asserted during the PI pulse, the
WAIT instruction will cycle in a 1. 2 us loop (if REFRESH is on
the loop will be 1.33 us max) pulsing PI.
The looping will
continue until an interrupt line is sensed by the T-ll to be
asserted. )

RESET execution times include instruction fetch, instruction
decode, the assertion of -BCLR and the writing of DAL(15:0> into
the MODE register.

4. NOP execution times include instruction fetch, instruction decode
and idle time.
5. Condi tion Code instructions execution times include instruction
fetch, instruction decode and the setting or resetting of the
appropriate status flags in the PS.

COMPANY CONFIDENTIAL
Page A-7

MAXIMUM LATENCIES

----------------16 BIT MODE

8 BIT MODE

--------------1--------------

DYNAMICISTATICIDYNAMICISTATIC
DEST
-------1------1-------1-----ACTIVE INPUTS
1 MODE
1
1
1
====================1========= =======1======1=======1======
-CP(3:0),-PF
1
NA
15.47 115.20 1 22.13 121.60
(INTERNAL VECTOR) 4)1
1
1
1
====================1========= =======1======1=======1======
-VEC,-CP(3:0)
1
NA
15.87 115.60 1 22.53 122.00
(EXTERNAL VECTOR) 4) 1
1
1
1
====================1========= =======1======1=======1======
DMR
5) 1
NA
3.66 1 3.52 1 4.46 1 4.32 1
====================1=========1=======1======1=======1======1
WAIT INSTR
1
1
1
1
1
1
1---------1-------1------1-------1------1
INTERNAL VECTOR
1
NA
1 7.87 1 7.73 1 10.53 110.13 1
1---------1-------1------1-------1------1
EXTERNAL VECTOR 1
NA
1 8.27 1 8.13 1 10.93 110.53 1
1---------1-------1------1-------1------1
DMR
1
NA
1 1.66 1 1.66 1 1.79 1 1.66 1
====================1=========1=======1======1=======1======1
NOTES:

These timings are
frequency of 7.5 MHz.

given

microseconds

and

assume

clock

1. Interrupt latency is measured from the time the INTERRUPT REQUEST
is asserted either on the AI lines (in static modes), or the
input of the AI line driver (in dynamic modes), until the time
the T-l1 is ready to fetch the first instruction in the
interrupts' service routine. In this time T-11 takes 3 actions,
as shown in figure A.I:
a)
b)
c)

Keeps going until a PI latches the request. This could
happen in the instruction following the request.
Finishes the instruction that latched the request.
Executes the lACK microcode, which involves priority
arbitration, issuing lACK, generating the interrupt
vector (or in the case of -VEC being asserted, reading
in the external vector), pushing PSW and PC onto the
stack and loading PC and PSW from vector and vector +2.
Rev A

COMPANY CONFIDENTIAL
Page A-8

LAST
INSTRUCTION

I
!IACK
I MICROCODE

__________________

IFIRST INSTRUCTION
IOF SERVICE
IROUTINE

1 _______________ _

____~<--a-->I<---b--->I<----c----->I
I
I
!
I
IRQ

I
I
I
I
I
I
I-I

I
I
I
I
I
I
I

IACK _________________ I !
Figure A.I.

1 _ _ _ __

Interrupt Latency

Note that the time to synchronize the IRQ and to perform any
external priority arbitration is not included in the interrupt
latency.
2. DMG latency is calculated from the time DMR is valid on the input
of the AI line driver until the T-ll has asserted DMG.
3.

WAIT instruction latencies are the maximum encountered in
instruction's execution state.
These times do not include
instruction fetch or the instruction decode.

These times refer to IRQ occurring during a JSR
EMT sequence, which is worst case.

the
the

(Mode 2 or 4),

5. These time~ refer to DMR occurring during a MTPS (Mode 0)
instruction, which is worst case.
6. These timings assume T-II is not in long bus cycle (mode register
bit 1) and there are no ready slips either.
Rev B

COMPANY CONFIDENTIAL
Page A-9

APPENDIX B
T-ll INSTRUCTION EXECUTION TIMES IN MICROCYCLES
XOR & SINGLE OPERAND INSTRUCTIONS

---------------------------------

MICRO CYCLES REQUIRED

1---------------------------------------1 16 BIT MODE 1
8 BIT MODE
1
1-------------------------DEST 1
1 WORD
1 BYTE

1 MODE 1
1 INSTRUCTION 1 INSTRUCTION
================1======1=============1=============1============
INSTRUCTIONS

CLR(B),COM(B),
INC(B) ,DEC(B),
NEG(B) ,ROR(B),
ROL(B) ,ASR(B) ,
ASL(B) ,SWAB,
ADC (B) ,SBC (B),
SXT,MFPS,
XOR

I
1

0
1
2
3
4
5
6
7

I
1

4
7
7
9

13
13
17
14
18
18
22

9
9
13
10
14
14
18

1
1
1
I
1
1
8
I
I
I
1
10
1
1
1
1
10
1
1
1
1
12
1
1
================1======1=============1=============1============
1

0
1

TST(B)

1 3

8
7

9
9
11

5
6
7

4
6

6
10
10
14
11
15
15
19

1
1

6
8
8

12
9
13
13
17

1
1
1
1
================1======1=============1=============1============
1 0 1
8
1
10
1
10
1
1
1
10
1
12
1
12
1 2 1
10
1
12
1
12

MTPS

1
1
I

3
4
5

6
7

1
1
1

12
11
13
13
15

16
13
17

16
13

1
1

17
17

================1======1=============1=============1============
NOTES:

1. XOR and Single Operand Instruction execution times include
instruction fetch, instruction decode, operand fetch,
instruction operation and resultant output (except in Mode
o and the TST(B) instruction where there is no output) •
Rev B

COMPANY CONFIDENTIAL
Page B-1

DOUBLE OPERAND INSTRUCTIONS
===========================

****************************************************************

*
*
*

(DOUBLE OPERAND EXECUTION TIME) = (SOURCE MODE TIME) +
(DESTINATION MODE TIME)

*
*
*

****************************************************************

SOURCE MODE TIME

I
1

INSTRUCTIONS

1---------------------------------------16 BIT MODE
8 BIT MODE
1
1-------------------------1
1 WORD
1 BYTE
1

1
1
1

MICRO CYCLES REQUIRED

SRC
MODE

1 INSTRUCTION

================1====== =============1=============1============
1
1
1

MOV (B) , CMP (B) ,
ADD, SUB,
BIT(B) ,BIC(B) ,
BIS(B)

I
1

o
1
2
3

4
5

3
5
5
7
6
8
8
10

1
1
1

I
I

5
9
9
13
10
14
14
18

1
I
I

I
1

5
7
7
11
8
12
12
16

================1====== =============I=============~=============

NOTES:

1. Source Mode times include instruction fetch,
decode and source operand fetch.

instruction

Rev B

COMPANY CONFIDENTIAL
Page B-2

DESTINATION MODE TIME

MICRO CYCLES REQUIRED

1
1---------------------------------------1
1 16 BIT MODE I
8 BIT MODE
11 DEST 11
1-------------------------1 WORD
1 BYTE

INSTRUCTIONS
1 MODE 1
1 INSTRUCTION 1 INSTRUCTION
================1======1=============1=============1============
1
1
1
1
1 0
1
1
1
1
1
1
1 1
1
4
1
8
I
4
MOV(B) ,ADD,
1 2
1
4
1
8
1
4
SUB, B I C (B) ,
I 3
1
6
1
12
1
8
BIS (B)

I
I
1

4
5
6
7

1
1
1

5
7
7
9

9
13
13
17

1
1
1

5
9
9
13

================1======1============= =============1============
1
0
I
1
1
1
1
1 1
1
3
5
1
3
1 2
1
3
5
1
3
CMP(B),BIT(B)
1 3
1
5
9
1
7
1

1
1
1

5
6
7

1
1
1

6
6
8

10
10
14

1
1
1

8
8
12

================1======1=============1=============1============

NOTES:

1. Destination Mode times include destination operand fetch,
instruction operation and resultant output (except in
Destination Mode 0 and the CMP(B) and BIT(B) instructions
where there is no output).
Rev B

COMPANY CONFIDENTIAL
Page B-3

JUMP & SUBROUTINE INSTRUCTIONS
==============================

DEST
MODE

MICRO CYCLES REQUIRED

1--------------------------------

1
1 16 BIT MODE 1 8 BIT MODE
====================1==========1================1===============
1
1
1
1
1
1
5
I
7
1
2
1
6
1
8
1
3
1
6
1
10
JMP
1
4
1
6
1
8
1
5
1
7
1
11
1
6
1
7
1
11
I
7
1
9
1
15
====================1==========1================1===============
1
1
1
9
1
13
INSTRUCTIONS

JSR

1
1

4
5
6

1
1

10
11
11

1
1

14
17
17

1
1
1
1
7
1
13
1
21
====================1==========1================1===============
RTS
I
NA
I
7
1
11
====================1==========1================1===============
SOB
I
NA
1
6
1
8
====================1==========1================1===============
NOTES:

1. JMP/JSR Destination Mode 0 is an illegal instruction that
traps to vector location 10.
2. JMP execution times include instruction fetch, instruction decode, operand fetch and loading of the PC.
3. JSR execution times include instruction fetch, instruction decode, operand fetch, pushing the linkage register
onto the stack and loading the PC.
4. RTS execution times include instruction fetch, instruction decode, loading the PC and popping the stack and
loading the linkage register.
5. SOB execution times include instruction fetch, instruction
decode, decrementing the count register, testing for zero
and branching if necessary
(NOTE:
Whether or not a branch is taken does not affect
the execution time).
Rev B

COMPANY CONFIDENTIAL
Page B-4

BRANCH, TRAP & INTERRUPT INSTRUCTIONS
-------------------------------------------------------------------------

1
1

INSTRUCTIONS

DEST
MODE

MICRO CYCLES REQUIRED

1--------------------------------

16 BIT MODE

8 BIT MODE

====================1==========1================ ===============
1
I

1
1

BR,BNE,BEQ,
BPL,BMI,BVC
BVS,BCC,BCS,
BGE,BLT,BGT,
BLE,BHI,BLOS,
BHIS,BLO

1
1

EMT,TRAP,
BPT,IOT

1
1

====================1==========1================ ===============
1

====================1==========1================ ===============
1
NA
1
8
12
====================1==========1================ ===============
RTT
1
NA
1
8
1
12
====================1==========1================1===============
RTI

NOTES:

Branch instructions execution times include instruction
fetch, instruction decoding, doubling the offset, testing
the conditions and adding the offset to the PC if the
conditions are met
(NOTE:
Whether or not a branch is
taken does not affect the execution times) •

Trap instructions execution times include instruction
fetch, instruction decode, pushing the PS and PC onto the
stack, loading the PC with the contents of the vector
location and loading the PS wi th the contents of the
vector location plus two.

3. Return from interrupt instructions execution times include
instruction fetch, instruction decode and popping the PC
and PS from the stack.
Rev B

COMPANY CONFIDENTIAL
Page B-5

MISCELLANEOUS & CONDITION CODe INSTRUCTIONS
===========================================

CYCLES REQUIRED

1-------------------------------1
1

INSTRUCTIONS

DEST
MODE

HALT

CLC,CLV,CLZ,
CLN,CCC,SEC,
SEV,SEZ,SEN,

16 BIT MODE

8 BIT MODE

==================== ==========1================1===============
1

==================== ==========1================1===============
WAIT
NA
1
4 then loop
1
6 then loop
==================== ==========1================1===============
RESET
NA
1
39
1
41
==================== ==========1================1===============
NOP
NA
1
6
1
8
==================== ==========1================1===============
sec

1
1
1
====================\==========\================1===============
MFPT
1 NA
1
5
1
7
====================1==========1================\===============

NOTES:

1. HALT execution times include instruction fetch,_
instruction decode, writing the PC and PS into thel
stack, then load ing the PS wi th 34~ and loading the PC 1
with the RESTART address.

WAIT execution
times
include
instruction
fetch,
instruction decode, pulsing PI to sample the interrupt
lines and doing a REFRESH cycle if REFRESH is on •.. (NOTE:
If no interrupt lines were sensed by the T-1l to be
asserted during the PI pulse, the WAIT instruction will cycle in a 2 micro-instruction loop (if REFRESH
is on the loop will be 2 1/3 micro-instructions max)
pulsing PI.
The looping will continue until an interrupt
line is sensed by the T-l1 to be asserted.)

RESET execution times include instruction fetch,
instruction decode, the assertion of -BCLR and the writing
of DAL<15:~> into the MODE register.

4. NOP execution times include instruction fetch, instruction
decode and idle time.
5.

Condition Code instructions execution times include
instruction fetch, instruction decode and the setti ng 0 r
resetting of the appropriate status flags in the PS.
Rev B
COMPANY CONFIDENTIAL
Page B-6

MAXIMUM LATENCIES
=================

1
MICRO CYCLES REQUIRED
1
1-----------------------------------1
I STATIC IDYNAMIC 1 STATIC IDYNAMIC 1
DESTI
1
I
I
I
I ACTIVE INPUTS
MODEl
16 BIT MODE
1
8 BIT MODE
I
1=================== ====1=================1=================1
I
ICYI01uS ICYI01us ICYI01uS ICYI01us 1
I
1 I I
I 1 I
1 1 1
1 1 1
1
4)
NA 1381 1
138121
1541 1
154141
1
1 -CP<3:0>,-PF
1 1 1
1 1 1
1 1 1
1 1 1
1
1 (INTERNAL VECTOR)
1=================== ====1==1=1===1==1=1===1==1=1===1==1=1===1
1 -VEC,-CP<3:0> 4)
NA 13911
139121
15511
155141
1
1 (EXTERNAL VECTOR)
I \ 1
1 1 1
1 I 1
1 1 1
1
1=================== ====1==1=1===1==1=1===1==1=1===1==1=1===1
IDMR
5)
NA I 8111.191 8121.19110111.19110121.191
1=================== ====1==1=1===1==1=1===1==1=1===1==1=1===1
I WAIT INSTR
I
I I I
I I I
I I I
I I 1
\
I
\----1--1-1---1--\-1---1--1-1---1--1-1---1
I INTERNAL VECTOR 1 NA 119111
119121
125111
\25141
I
1----1--1-1---1--1-1---1--1-1---1--1-1---1
I
I EXTERNAL VECTOR 1 NA 12011\
120121
126111
126141
1
I
1----1--1-1---1--\-1---1--1-1---1--1-1---1
1 DMR
I NA I 3121.191 3121.191 3121.191 3131.191
1===================1====1==1=1===1==1=1===1==1=\===1==1=1===1
NOTES: 0. These timings are given in microcycles (assuming 3 phases/cycle)
+ extra phases + microseconds.
1. Interrupt latency is measured from the time the INTERRUPT REQUEST
is asserted either on the AI lines (in static modes), or the
input of the AI line driver (in dynamic modes), until the time
the T-11 is ready to fetch the first instruction in the
interrupts' service routine. In this time T-11 takes 3 actions,
as shown in figure A.I:
a)
b)
c)

COMPANY CONFIDENTIAL
Page B-7

I
IFIRST INSTRUCTION
LAST IIACK
IOF SERVICE
INSTRUCTION I MICROCODE
IROUTINE
____________________ ______________________________

I
____~<--a-->I<---b--->I<----c----->

IRQ

I
1

1
1

I
1
1
1

I
1

IACK

---------------------1
Figure A.I.

Interrupt Latency

WAIT instruction latencies are the maximum encountered in the
instruction's execution state.
These times do not include the
instruction fetch or the instruction decode.

4•

Th e set i me s ref e r to IRQ 0 c cur r i ng d uri n g a J S R ( Mo d e 2
EMT sequence, which is worst case.

These times refer to DMR occurring
instruction, which is worst case.

during

MTPS

r 4),

(Mode -0)

6. These timings assume T-ll is not in long bus cycle (mode register
bit 1) and there are no ready slips either.

Rev A

COMPANY CONFIDENTIAL
Page B-8

APPENDIX C
PDPll DIFFERENCES LIST

... ·.1

====
====
IC
.... ··1···I X

,
---- -.--

----1-----.._-.
1:(
l(

====1====

COMPANY CONfIDENTIAL
Page C-1

·.·--·-------.------••
-.-··.--------.-----•.
---i
LSI
, 15
35
45
Fit
34
11 I 10 I
rlt
..
..
---====
7, Realstr.r
tl717aa • 177117) are
Proqram
used bY.the.CPU.
-._.. -_.-- ._-- _........ ,.....I --- ---- .---~.- .. -.-.-.-------.----Peqister
(17710... -.-----.-.--.• 177117) time ....
out -.-.-.When ..
I

addresse~

w~_n

4/l

I X
I

:::=: :::: c:c: ::==:I:~=='l====

============================================~=======D====_
a~dresses

~'5

vall~

addresse~

Uspd 35 ~ progrAm a~dress bV the CPU. c~n be ad·
~ressed under c~n~o\e o~eratlonl
~otel AddreSSeS
c~nnot be addressp.d under conso e for LSI·t
or '-Sl,
--------.-.---.--~ReqistAr !~dresse~ (t17130 - (77111) are handled AI
reqular memory ad~relses (In the B510 paqe). No
x
internal reg ster! are addressable from eltner the
bUS or the console.
D===;a
-===·----=------~-----~=~~i. ~iiia i~iii~aii5;i-n;t;~ -~------.-~-=~-~-=-D~.--=-:-i~-~~~:il-~~O~;s;o~ ~a~~-- -X
book •
MrpT (move from proeeslor tvpo)
X
SOA, RfT, SXT instructions,
X
•••••
HARK instruction,
ASH, ~RHC, DIV, MUl, Instructions,

(

.. -.---- ....-- ...... -.--- .. --- .--- .... _.-.- ·.··1-·-. ._-- .. -..----_----_
----------.. ----••
..x -.x
x .. ----.. ... ====
..•....•.. ---- ..•....... --.----- ..... -- .... -- ........ . _.-.- ...... •••• ._-- -.-.- -.. -- ._ .. --_. ..- .
e._ •• .. -- --- . ---- . --.................................................•....•... ........---.----- ...........•......-- ...........•.• --.
• •••• _.-- _.-. --.- ._-X
......
......
•...•..•..•. -- .. ---- ............... -............•..... ......
-.-.
--.
---)(
x
.. _.... _..... _...___-.•...•........•........•.
....•.•...•...• -._- ..... ---- ..... -.-- .. - ... 1· .... ..-.
. __ .... __ . _______ . __ . ____ .. _.. _.. _... ... .. ...
.• •• _.-- .-... _.- _.-.
x
externnl oDtlon
provides MUL{ OIV and
I
X

.--.-----.-- ...

~2~.!~~~~~~~!~~!
T~e

::::1

I(
)(

KEll.~

I.~._

.-.-

_.-- ---. ._-.
I
I
;~;·~~ii:~-;~~;·~~i;~;·;~;~;-;~~:;;~·ii;;~i~;·~;i~~--· ····-t·· __ · ··--1---- -·_·-1 ... ·- •••• --X.. .--instructions. FAnD, rSUB, FMUL, fOIV.
.
I
I.. _- .--. -- . - .._.
-.-.-,
Th;-~~v:ii-;dd;-~TSiFis·i~;tructi~~;:-·-·---·-····~·-·t··_·-t····· ----1---·
X I
sPL·i~;~;~~ti~~:·--·---·~-·------·--·-··-·--·······--·1···--1-----1···-1···- ···--1···- •••• -_....... -----. -------~-~----==~-------.--==.---~-~----~-----~----=----~~~-=---~-l-~--='-==~--- :_=== =:== ..----.------~
----------- .---~------------~- ---~---- -- •• -----~- - - ---~~!~!.~~~~~~!~~~-!~.~~~.!~~~.~~~~-!~~~~-: ...... -.-........ - .. -..... _, .... ' .. -_.

The KE11-E (Expansion Instruction set) provides the
instructIons MUL, DTV! ASH, and ASHe. These ne~
instructions ftre 1t/4~ compatible,.

,
,
I

._.I(

COMPANY CONfIDENTIAL
Page C-2

PDP-Il FAMILY H1CUINES
LSI
11
04
34

----------------------------------------------Fl1
TIl
----- ---..---- 45
.. ---- ,..--- ------------------------------------------------~----------- ::=== ----ACTIVITY

--~7~:~-~~~i;d~ii:~-~~~EI~!~:~~~~1~~~i:ij~~i~~~~~}~ij~-----

milliseconds). RESET instruct on consist~ of 0
mi lsecond" pause with INIT occurring during f rst
20 milliseconds.
... ----------------------~-~~~-~~~~-------------------~-~~--Power fail iamedlatelv ends the RESET instruction "
and traps it an INIT 1s In progress. A m niaum
I
INlT ot 1 microsecond occurs it l~structtons aborted.
-~--Poue .... fai I acts the same as }1{45 1 (22 1I111isecopds
I
I
uith about 300 nanoseconds a n aua). Powor fail
X
during RESET fetch 1s tatal w1th no power down"
sequence.
"
------------------~-----~----~-~~~----~-----------~--- -~~~RESET
instruction consists ot 10 alcroseconds of INIT
X
followed by a 90 alcrosecond pause. power tall not
X
rocognized until the instructIon"" is complete.
-----------~-----------------------------------------~~--- ~~~-- ~--- ~--RESET instruction consists of a mlnlaua 8.4 aicroseconds followed by a minlmua 150 nanosecond pause.
I
Pouer fall is not recognized until the instruction"
is complete.
c:--- ----- ...
-------------------------~------------------------------X
•---------------------------~-------------------~-------No RTT instruction.
.... _...
---~.,
------------------------~----------------------------It
sets the T bit, the T bit trap occurs atter
X
X
X
X
X
the nstruction following RTT.
.
----- X
----- ----- ----. t
.==========~====:======================================== .........
It RTI sets the T bit, the T b1t trap 1s acknowledged
atter tho instruction following RTI.
--------------------------~-----------------~--------~
X
If RTf selts the T bit, the T bit trap is acknowledged
X
X
X
X
im~ed ate y following RTI.
'

--_ ---...,

-----

------------------------------------------------------

~ ___

~=:::=

-----

....

---

---- -------X
_=====- .. .. --- --- -----

---

;:---

----,X
I
-------- ----- ---. ---- ---- -.. _----- ...--- ... --- .--- ... ------- ----::--.....
_-- --------- ---- ---- ------------- ------ •
--:A:~~:~:i&ii~~!~i:~!~~:~~:;!~~!~:::~:Ir=i~=i!~ei~:::~====
RIT

--~-

At th~ end ot instruction execution, the T-bit
has hl~her prio{ity th~n interlupt requests.
"
Once in the T-btt service rout ne, otner nterrupts
are blocked to insure no unexpected occurances.
When the RTT instruction Is executedl to leave"
."
the ,ervice routine! nterrup~s will not be
se . . vlced if the T-b t is set intne new P'S
.
popped otf the stack. "The user uill, therefore,
not see any interrupt requests" he is expecting.

COHPANY CONFIDENTIAL
Page"C-3

r;:---

...

AC'1'lV[TY

... POP-It.. I Lsr I Wi I 1"
rA~tLY

-~-.-

Til

~.----

: fl1

14 I 11
In,
,
I 'u4 ====
==::=1====1====1:===

~c=:=I=;~:=I==:=

... --

4~CHrN~S

--~----.-.------~------

I lC

I
I X
I

=::::a

t X

----an.......
-.-... -.. --- .....----an......
...... -- ....... ._._.1-._ ... 1-.. - .--- ... _- , .. _- ..- .
interrupt
instruction
the r bit Is set,
interrupt Is
before the r bit
I
====1;;:::=
:===
====
======:===================:::==.==============a===========
====
_._.
r bit tritp'
sequence out
instruction.
X
X
x .
x
....
.•...•.•.....
-.........•• -..•...••.•.. ----..-......-.. .-~-... ~--l.~
.•
.. .. -- .....
r bit trai _111 not seQuence out of WAIT instruction.
x
, --_ .. ...----"___ -.
__
.. ----- ___ • __ • _________ =---=------al=----_x.... ===1:
----.---- ===;:;
1:====1-===
---.----It. Expll:1t referencp (direct access) to PS can---load
I X
x .---tne r bit. :on501e can also load the T bit.
t
.
......
..Only
-...implicit
-.-.-..-..references
-...--.....(ATI,----..RTT,--....
-...
....
.....
.
•••• •••• • •••• _.e • .--. ... - ···-1
traps and InoccurB~urlnQ

t~e

tr~o.

11.

will

)(

---~I---I

and

aCknowled~ed

t
~=:=: ===~I====

-=aD:: . . .

of WAIT

••••

lit . . . . .

~~!=t~_ ~~!_=l ~~_!~~:-r~~~~!=

------~

--~-

.--~---

--------.-~-----

--~-

terru~t$)

the T bIt.

can load

~ne

r bit,

Console cannot load

c-:----------------------===;:=-----c--:-;:----a--=---:-=:a=
15.-0dd-;ddr;;;inon:;;iitent reterences·usinq the-sp -

=====

ca~se a H~LT.
This Is I case of double bus error
With the second errOr occurrln~ 1n tne trao seI·
v c1n~ the flrst !rror. Odd address tra~ not n

==== =::=: ===:1 ----..

e=:;:.

)(

or F-Il.
......
_-.... _-_ ....•.•.. -----..---.....
_- ... _- ...... -.-.- ••••• •••• •••• ..'._ . -.-- .-.. ---- .....
Odd
reference,
uslnQ the SP
cause a fatal traDe On bUS error ln trap service,
new staCk created at U/2.
.•
...
..
.....
-.......
.......
...-... -.- .........X . -...- •••• •••• ...... _.-- .--. ...- ••••
Odd
references usinq the SP
(.st-tl

~ddress/non-e.lstent

-.-.~.-.-

a~dress/non·e~lstent

do not traDe

..... ====
::=: ==== ,.
---- -------.. :;:::a
-------I --- c---X
X
X
X
X
'X

~-=------:---=------=----==----------=---z----------c-=---I=~--=
i~.-i~e-il~;t in;~~~c~I;~ 1;~;n-in~;~r~;~ ~~~~in;-;ili
not be executerl i ' ~notner interrupt occurs at a
X

-...- ... _. .. _. ..... - ._.. -----,. ..........
-------. --.... ..- -_....
--.. --============================:=======================c:::== ===== =====
. -.--_
==== ---x
x
_..
......
..
-_.
.
....
----General
... --- ....---- •....•... --.-- .....-...-......•.• -..
-.--····1··· ..
....
---.
====1====
te:-PSw-a;dre;;;-171716;-not impiemeoted:--Must-use-new -- .=--- ---- ---- --- =====
t
~~!~:::~~::::.::::-:::::.~:-~~~.::~-::~~.~~:::-::::- ....:-- ----~!.---l.--·.---1---· ---. ·x--I-i-I
~~~~~~!--.-.-- ... ---.--... ---.~- .. -.... ----.....•. -.-...... ---...•.. 1.--- .-.... l~--. .. -. ----1·------~~~-~~~~!~!-~~~-~!~~-~~~-~~~~-!~~!:~!~~:~!a-==--:-=--- :---- =-~--I~---I-~:
---hlQner priority lev@l tnsn assumed by the first
interrUPt.
.
.

••••

Th;-fi;;t·i~;t;~~tl;~·i~·;~·i~t;~~u~t-;;;;l~:·i;·····-,_._--

guaranteed to he executed.
17. 8 General purpose registers.
16
purposp. reQisters.

==---~--=---~----=----~-----=-=--~----------~~--~---c--:--

••••

P5W a~dre5S implemented.

MTPS and M,PS not IMPle·

I lC

::::z:

=--~-I----l=--~

• •••

I X

---- ====1:::==
i9:-0niy-one-interruD~-tevei-(OR4)-cxist;:---- - -- - --- ----I ----, --- -- - =====1====
I
X
I
COMPANY rONFTnFNTTAI

Page C-4

...•.
J.---.. -.--.-.-...
---.--••.
ur ih"e r r u
1eVe
e 15
~
~. •
0 • _ . __ M ___ • •
0 t_ _
•

~~-.---_

.... .·--1,
.-..
•.•• _r -.-1---.- .. -.. •••• ...... ....... ...... ....
---- ..... -.-.- -.... ,..... ._.. ,

1 5 _ _ Ie• • _ _
t _• _ • •. • _ . _
. . _ • • _ . _ _ . _ • • _ • • •. _ • • I1_ •••• _._-x

"_._~.

:===~~~~=!~~~~~~~~=!~~~!~=~:~~~=:~;g~:~=!~=!~~~=!!~::===:=I==~=:
=====
!0. 5t~Ck overflow not implemented.
.
f ~

I X

--_ .. ---......----...- .---.. ... --A.-- :=:::t====
,
.........
......
--"K--I
X

)(

...

I
:::::1

..... ·-i·· _:==
X
X
.... ==:=1====
==;;= ----.......
---====1
-===:--=====-;-=======-:===--:-====-====a======_=====c====1=====
=====
,
it. o~~ addr;s; trap n~t 1m~ie;entea. .
.
I X
X
X
...... X.... ........ .. --- ----1-·
--.
~~~·:~~~;;;·t~:;-i;;i;;;~~;~:---··-····----·----···-··1-·-·- .... - X .X I X. · X
.... ====1==== ..
---.--.----~-~--------~---.---------~-. --=---~--=---=-------~-t~--=~·----
.. -I -.. _- a--- • ==== X ---FMUL ind FDIV instructllns implicitly use R6 (one
push
pop), henc! R6 Must be set up correctly.
I
I
.. -.
~~~~·;~~·~~i;-i~;;~;~~i;~;-~;·~;~-i;;ii~i~i;·~;;·~i:··:-·---1-···· ····1···· -.-.- _.-- --- .. ----_ .. .......
...
-----.. ..------- ---- ---.--=-------~--~--~-~----=-----~=-=---~--~--===-~-.---=:---t-====I=--~=
---23:
oue·to-thelr-e;ecution-rIie,-gis-in&tructloni can --- --- ====18:==
I
5~;;-;~~t·~f-;t~~;-~;;;fi;;-i;;i;;;~t;d:···-·-·-······

•• ... 1-· ••
X
t :<

)(

.----.--~---~---~~-~-----~~.--------~
-~---- ~~~2.

:1:=:=

-~------.

~nrl

)(

_.-.- .. X

.... .. -.
X
..
_
....
-_ ... ---....X_- ----.. -- ---_======================-.======================ac====::=:8 =a:c= =====
.. -----...... ---- ---~::=:~~~!:~~~:~:~:~!:::~:~!~::!~~~~~~!~~::~::!:::=:::=a===
====: ===== .===I==~= ----.---lnstruetions do a
and OATObUS sequence
X
abort because of

Interrupt.
I
•.••.•.•......•.•
-.•
_-•••••..•..••.•
_-•••••.••••••••••..•••••.••
-·--1··-[{S instructions do n~t abort because of a device
X
I'
interrupt.
ft

~eYl=e

':a==I~==:

~5.

~IS

••••

)(

=1::=~

=::;; --

O~'IP

-•. _•• _._ I.• _. ••••• •••• •••• .-.- .-- .
lC
F.ts instructions
a OlTI bus sequence When
X
I
{etching source oDerand.
I
......
------------.
~========:===================================~=======.====
-==== =====
---HOV 1nstruction dne! just a DATO bUS sequence for
X ====1=:_.
X I X
X
X
the last ~e~orv cYcle.
..
...... ...X - .--.
.. .. -.
~ov·i~;~;~~ti;~·d;;;·;·;irip·;nd·DiTo·b~;·;;q~;~~;···· .......... -i·· .-•.
X
for the last $emory cycle.
.
.
._.- .. -.
~o;·i~;~;~~~i;~-~:;;·;-~~i~·iDi;ii·;~~·;·;~i;~·i~ii~i·I·-i·· -.-.- ···-1···· .. -.- ..... 1•• -I
---~~~-!!~~~~~!-!~~-~~:-!~!~-~!~~~y-~!~!!!---=-----==--=-t~---=·
----=-.----1---=-.
11-------1---------i 1.
--------.---------------.~---~--------~--~~~X
X
X ---.
X ==== ====
If PC contains
memory address -~--and a .- -1---- -~--X
X I .X
e~!.~~~~:.~::~~~!.~~~~_~!_~~!~~~~!~_!~~~~~!~~!~! ...... I ••••• ----.·I ••• -t •••• ..... - ··· . 1---· --.- .....
X
Tt PC conta1ns non-!Kl,tent memory address
a
I
I
I
wl'len
ooerand..
. ...•• __ •.•.••••••••
.•.•.•.
_.•.. __ •source·
__ ..•••.•.
_.•.••• __ .ft_
tetcnln~

~_.

)(

~6.

=:=::

:;::::

)(

non.!~lltent

-.-.- ----1--•. .-.- _._.
I
,
.-.- .. -.
... -

an~

bUS error occurs, P~I w1ll he unchdnCJed.
I
I
I
---......
---•.•
---.•••.....•••
-••..•••••••....•••.••..
I·····
•
••
-·I·-·~I····
I
I
Does not support b~S errors.
t X
I
I
;===================::==.==:==.=====================~.===~I===== ==~==I.===I==== ===== ====1==== ==== ====
28. If re~tster contains non·existent memory addIe6s
I
I
J(
X
X
X
X
in mo~e 2 and a bUS err~r occurs, re~ister w 11
• X I
t
he In:remented.
.
.,.
.,
,
........
_--... _-.-......... -_.-....... -_._-........ -.. I,_ .. --,-._.-1----1··-----1---t
If re11ster cont~tns non-existent ~emorv addIess
I
I
I
I
in mode 2 and a bUS err~r occurs, register w 11
I
I
I X I X
I
t
be unchan1ed.
.
.
.
I
I

O;;;·~~t-;~~~;~t·bU;·;~~;~;:··-····--·-·--·····--···-·

I.wi--t-·_·· .......
I . ····-1-.··1···- ---- .-..

----....
-... I ---. -------=1---=1---ii:-iF-;;;i;~;~-~;~~;i~;-;~-o;~-;;i~;-i~-;~~;-i-;~~-;t ----, -i--,
1-~---------------------------=-------------------------=-==,=----1:----1.=-=,--=x
X I
X

rnMPftNV rnNFTnFNTTnl

Pa~e

C-5

.. ---1_.)( __ .. -. ._ ... ,.. _...... I-.. -- .. -. _.... _.--_ ......
--_ .... --_ .. ==== -------. --------1---...... ,....
.... - .. ...
I

••••

I
I

::::1
====:1:=:= ====
====
lC
I
X
IX
····-1·"-· ····1--·· .. _.

,
x

c:=:alz==:
x ====1====
x
x ====

----1.--.
, --.- _._-.
----1---- ====1====

:~~~I::~~ .~
I

...~..

-_X.... ---........
-------===
X
X

----.-- .-.. ---- .--.
._-X

==== ----

_.-.
---x
x

---- ... -.

I
I

.. x_-- ====,I
---)(

-.-.- -.-- ---a -...... -tt
---...
-"-.-.-------.---.-.-."-~-.-~ .... -.--... -....... .
, .. _--1
4~MI ~ar. m~tnten!n=e mo~e SR0 bit a 15 not
, ...X_-1-·--1····
I
I
lmo el\"nt~t1.
I
1
I
I
--:----------------------------------------------------=-=----I-=---Ir:-=-·---=====
====
====
====
====,
-"
- -I
11. ---------~-~----~--~--~~--.~----~-~--~--~----~-----PS<t5'12>r user ~Od!, user stack pointer, and
"

-- ---- ---

MrpX and ~FPX Instrdctions exist even when ~£M. MGT. I
I X I
15 not confl~ured.
'. .
I
I
I·····,·--~·
PS<lS&'2>l user morle, user stack pOinter, and
t
I
~,pX ~nd MFPX instructions exist only w h e n '
I
I
MEH. ~GT. 15 conflqure~.
I
•
I

-.-_.

I··--1····
I
_.-- ._-.. -... _..
.•.......... __ ..................•.....................
•
I
x
-_ ..
&==== ===;; ==== ==== ------------=---=-------------a--,
-==-=-=-----=-===-••••
C---=-I&===-.---==I=-==I=--io:-cuI-rent-;ode·ps-bii;-<isii4)
set
to-ii
or
10
-.-1----x
1 Cause a MEM. Mr,T. trap upon any memory
I
reference.
. .
.
1
I
I X ..... .... .-- ........
C~-;;~t·;;d;-P5·bit;.<i;·i4;·;;t.tti·0i-~;·i0 ....• ·-· •• · .... 1····. -.. - ....
~~rl De treated as ~ernel mode (00) an~ not cause
II X .
tI
a ME ... MGT. trap.
'
I
-------·-_-~------~------=-=::=-==---~~-~=---=-a-:==---.--c-=---1==-~---=.-._z====
==== ==== ===_
-------19.
MTPS in user mode will- :ause a------HEM. MGT\ trao
it._ ..
P S-' I --I
111176 Is not
If mappeQ
I
I K •
and <110~ are affl'!ct:ed.
"
I"
I
--... -.. -.... -.-..•.. -•.....•. -•...... --..•.••.••••••. ···_·1··-·-1···....
.. ---. _... ..-.
====~~~:~~!:~~:~~::~:~~!~::~::!~i;:::!~~!!~!:!:=::~g:~~==.,.====!=====I.===IC:==
----_- ----=:== .=== ===: ....
---- t
4a. adrlreSs
MFPS in Qser mode will cause HEM.
trao it PS
I
I
I
I
111716 not
If mapped, PS(710)
I
I
X
I
are accessed.
.
.
I
I
._-.
.
....
...
....
••• .. 1I
Hrps·i~·~;;;·;~~;·;lii·;;;;;·P5<li0;-;:;;~di;;;····-··I···--:··i·· ···-1····
-=:-~!-:~~~~~~-~~-~~~~!:!-!!!!!~-!:-:~~~!~!-=-=-=-.-c=---=I==a--I.--=:
=::= c=c: ====:1 .........
---- ====1==== ====1
41.-l-HALr-i~;truction-t~-us;r-mOde-traps to 4 - - - ~-- I
--.-X I
l(

--~------ --~-----~-----

==~=

-~-

ft~dre5s

ma~ped.

-.-.- -.

PS<715~

M~T.

~app.d.

A-HAi.j.-i~;t;~;tl~n-i~-~;;;·;~d;·t;;~;·t~·io:·····~····1····-1··,··

••••
.... ·i·· .. -.- ---aa=::

:=======================:=::::=====================
••• ====1=-===1=====
==== ==== :1=:::
42. A HALf instruction ~ushes PC , psw to stack,
I X I

lo~d the PS with J4~, and load the p~, w1th
I
power UP address + a (restart address).
t
I
=================:::a=:==========================:========1=====1=====
==== I
43. Res ldent oor microcode.
I
•
X ==== c:£: =====
X

~---

---- ====
---.
X

... --1
I
=:=~i

-_ ... .. ..._-- ===;1
------a==='1 ==== ==== .....
==c=
ca:c
~~!=t!=i:~_-a~~:~~~!:!~~!§!:=a!!~~~!~=;~!=e~_§!_!_~~~!_al~=.(~~!=i=)I--=~
__
I=-:_=
_
_
-ac.-_-=
• ::=a=
.--,.
---..
------------------ ---====/=== .
45. Instruction execution
runs
to completion
X
of
erros.
I
I
'.
.. ... .. ---.. ----..
============================================-=======-=====I:a===I=====
==== ==== =-===;; ---=1---46. vector address ranee llllted to 4 to 374.
I X •
.. - ====1==== ------- ---:=======================_=======a===_======:==========•• ==1=:===1===== ==== C~== ------=~-----=---:--=--~---=----:-=---=--==--:-==-=-=:--c-=--=,=--c=le:-==
--~--- ~- ----~~~--~--

~-re~ardlesl

~~-

::=;;=1:

;:=::

bUS

---~

COMPANY CONfIDENTIAL
Page C-7

HARDWARE OJ'f~R€N:eS •
(rRANSPAR€~r

TR~PS

TO SOfT~ARE)

lnstr":tlons
TRA:£ TRAP
EKternal Vector
tntr.frupt
1 nt erna 1 ~'e=tor
Interrupt
Po_er Fall rrap
WAIf [,000
T~ST Mo~e ReqUest
'~AP

~e1orv

Ht\t,t' lt1fP.f<HUPf

~e~nrv

P~rltv

~rrorS

~.naaement

Fault
8us Error TraDs
rR~p Instruct10ns
flUCE Trao
OVfL TreD

Power Fall Trap
~on501e Bus Request
UNIBUS BUS Request
iUIT [,oop'

COMPANY CONFIDENTIAL
Page C-8

• TR'PS
TO SOfT~ARE)

HA~OWAR~ DIFFER~NCES
(TRANSP~RENr

.
········_··-_···········,········ __.···_-··_-··--·1····
.... -.... ---.-...... I····-···--~-·-----··-···I
.. -...
-.-.~~~!!.-- •.• -.. 1-•••••• !2~!!~~~!!~- ...•. 1•••• ~.!~~!!~!~:~~- .. -.--I ••• -.-.~~~!!~~~:~~ .... --,
prldrltv of internal I Priority Of internal t Priority of internal I Priority of internal t
DroceSSOr traps, ex· I )rOcessor traps, ex· I processor traps, ex·
ex· I
ternal lnterruDtl,
I
ternal interrupts,
I tethal interrupts,
ternal interrupts,
HALl and WAlTa
KALT and WAlTa
t
HA r and WAlla
HALT and
Bus f.rror Trap
I BUs Error Trap
I BUI Error Trap
~emorv Parity ErrorS

COMPANY CONFIDENTIAL
Page C-9

Droce~sor

tr~DS,

W~tTI

APPENDIX 0
WORST CASE REFRESH RATE CALCULATIONS

..=

..-

~
..-

41110

;;

... .-~- 411=
Ills.
III

~& -&

-i§ ~I'II ~I'II
~
~ ~

..'"'"
~~

+
I
I

....
IW

!i:!

-"'"

9 -+

1
a -+
I
I
7 -+

:::
:EC

-....
Z

=c
..-~

>- '"

6 +

I
I

5 +

IWN

==
Cl'Z
IW=:

""en
IW

z""
-CJ.I

III

10<

• > .... >

..-

... =

... ,..

III::&:
_C

III'"

-:IE:

,",c

~V1

>0 VI

CI\~
_c

A..

...,0

...,c

I
I
I

1
1
1

1
1

I
I

II· /B
/1I

1
1

1 +

I
I

§o;

:E"'"
- cr:

<rill

I
I

:Ecr:

, /"

,./

..........

• I'

.---

2 +
I
1

+
I

o
AVERAGE CYCLES PER INSTRUCTION

.-....
.
-... _-...-

.5 Refreshes/instruction
1 Refresh/instruction .
2 Refreshes/instruction
1 Refreshes/instruction

No DMA, No Ready Slips, No tACK's, No LaC
A - Worst Case (all OOP's Souree and Destination Mode 3), l6-bit mode
MHz
B - Worst Case, a-bit mode - 4.5 MHz
C - Average time in 16-bit mode - 2.S MHz
o - Average time in a-bit mode. 2.2 MHz
E - All OOP SDM7, 16-bit mode. 2.S MHz
F - All DOP SCM7, a-bid mode • 2.2 MHz

- 5."

COMPANY CONFIDENTIAL
Pac;e 0-1

AVERAGE REFRESHES PER INSTRUCTION

REFRESHES PER INSTRUCTION

--------------------------------------------------1
DEST Mode
l6-Bit Mode
8-Bit Mode

INSTRUCTIONS

================== =================1=================1==============1
1
1
1
XOR & SOP's
0-4
1
0.5
1
1
1
JMP & JSR
1
1
1
5 - 7
1
1.0
1
2
1
================== =================1=================1==============1
1
l6-Bit Mode
1
8-Bit Mode
1
1-----------------1--------------1
SRC Mode
1
DEST Mode
1 DEST MODE 1
1-----------------1--------------1
1
1
0-4 1 5.7
1 0-4 1 5-7 1
==================1=================1========1========1=======1======1
DOP' s
1
0
4
1
0 • 5 1 1.0
1
1
1
2
1
1
1
1
1
1
1
1
5 - 7
1
1.0 1 1.5
1
2
1
3
1
==================1=================1=================1==============1
1
1
1
1
CMT, TRAP
1
0
4
1
1.5
1
3
1
1

BPT, lOT

5 - 7

0.5

==================1=================1=================1==============1
f = Minimum Operating Frequency (in MHz)

to meet N refreshes in X sec.

A = Average # of cycles/instruction
R = Average # of refreshes/instruction
N 3· A
f = X --R-- + 1
(one cycle = 3 operating frequency periods)
Example:
all DOP's source and destination mode 7, 128 refreshes
every 2 ms., 16 - bit mode
f

= 128 refreshes
2 m sec.

3 periods/cycle • 19 cycles/instruction + 1 period
1.5 refreshes/instruction
refresh

= 2.5 MHz

COMPANY CONFIDENTIAL
Page D-2

APPENDIX E
T-11 INSTRUCTION EXECUTION TIMES IN I/O CYCLES
XOR & SINGLE OPERAND INSTRUCTIONS
=================================

\---------------------------------------8 BIT MODE

1 16 BIT MODE

--------------------------

DEST \
1 MODE 1
1

INSTRUCTIONS

CYCLES REQUIRED

WORD
1 BYTE
INSTRUCTION 1 INSTRUCTION

================1======1============= =============1============
1

CLR(B) ,COM(B),
INC(B) ,DEC(B),
NEG (B) ,ROR(B) ,
ROL (B) ,ASR (B) ,
ASL(B),SWAB,
ADC (B) ,SBC ( B) ,
SXT,MFPS,
XOR

4
6
6
4
8
5
10
8
=============l==========~== ============
1
2
2
2
4
3

6
7

======
o

======~=========

TST(B)

1
3
3

2
6
6

2
4
4

1
1

0
1
2

1
1
1

5
6
7

3
3
4

6
6
8

5
5
7

7.===============1====== =============1============= ============
1 0
1
1
2
1
2
MTPS

I
1

2
2

1
1

================1====== =============1=============1============
NOTES:

COMPANY CONFIDENTIAL
Page E-l

DOUBLE OPERAND INSTRUCTIONS
===========================

****************************************************************

*
*
*

(DOUBLE OPERAND I/O CYCLES) = (SOURCE MODE CYCLES
INCLUDING INSTRUCTION FETCH) + (DESTINATION MODE TIME)

*
*

****************************************************************

SOURCE MODE TIME

I MODE

CYCLES REQUIRED

1I
1---------------------------------------1 16 BIT MODE 1
8 BIT MODE
11 SRC 11
1-------------------------I WORD
I BYTE
INSTRUCTIONS

INSTRUCTION 1 INSTRUCTION

================1======/============= =============1============
I

1 ell
1

MOV ( B) , CMP ( B) ,
ADD,SUB,
BIT(B) ,BIC(B) ,
BIS (B)

1 2

2
4

1
1

2
3
3

1
1
1

3
3
4

6
6
8

5
5
7

5
6
7

================1======1============= =============1=============

NOTES:

1. Source Mode times include instruction fetch,
decode and source operand fetch.

COMPANY CONFIDENTIAL
Page E-2

instruction

DESTINATION MODE TIME

I/O CYCLES REQUIRED

1---------------------------------------1 16 BIT MODE 1
8 BIT MODE

1
1
1-------------------------1 DEST 1
1 WORD
1 BYTE
INSTRUCTIONS
I MODE 1
1 INSTRUCTION 1 INSTRUCTION
================1======1=============1=============1============
1
1
1
1
1 0 1
"
1
0
1
0
1 1 1
2
1
4
1
2
MOV (B) ,ADD,
1 2 1
2
1
4
1
2
SUB,BIC(B) ,
1 3 1
3
1
6
1
4
BIS(B)
1
4
1
2
1
4
1
2
1 5 1
3
1
6
1
4
1 6 1
3
1
6
1
4
1
7
1
4
1
8
1
6
================1======1=============1=============1============
CMP (B) ,BIT (B)

I
1

1
2
3
4

I
1

1
1
2
1

1
1

2
2
4
2

1
I

1
1
3
1

5
6

1
1
1

2
2

1
I
I

1
I

I
I
I

I
1

4
4

I
I

I
1
1

3
3

================1======1=============1=============1============

NOTES:

Destination Mode times include destination operand fetch,
instruction operation and resultant output (except in
Destination Mode 0 and the CMP(B) and BIT(B) instructions
where there is no output) •

COMPANY CONFIDENTIAL
Page E-3

JUMP & SUBROUTINE INSTRUCTIONS

------------------------------

DEST
MODE

CYCLES REQUIRED

1-------------------------------1
1

1
1 16 B IT MODE 1 8 B IT MODE
====================1==========1================1===============
1
1
1
1
1
1
1
1
2
INSTRUCTIONS

1
4
1
1
1
2
1
5
1
2
1
4
1
6
1
2
1
4
171
3
1
6
====================1==========1================1===============
1
1
1
2
1
4
1
2
1
2
1
4
1
3
1
3
1
6
JSR
1
4
1
2
1
4
151
3
1
6
1
6
I
3
1
6
171
4
1
8
====================1==========1================1===============
RTS
1 NA
1
2
1
4
====================1==========1================1===============
SOB
1
NA
I
1
1
2
====================1==========1================1===============
JMP

NOTES:

COMPANY CONFIDENTIAL
Page E-4

BRANCH, TRAP & INTERRUPT INSTRUCTIONS
=====================================

CYCLES REQUIRED

1-------------------------------DEST

1
1

1 MODE 1 16 BIT MODE 1 8 BIT MODE
====================1==========1================1===============
1
1
1
INSTRUCTIONS

BR,BNE,BEQ,
BPL,BMI,BVC
BVS,BCC,BCS,
BGE,BLT,BGT,
BLE ,BHI ,BLOS,
BHIS,BLO

1
1
1

1
1
1
1
1
1
1
1
1
====================1==========1================1===============

EMT,TRAP,
BPT,IOT

RTT

====================1==========1================1===============
RTI
I
NA
1
3
1
5
====================1==========1================1===============
NA

===========~========I==========I================I===============

NOTES:

Trap instructions execution times include instruction
fetch, instruction decode, pushing the PS and PC onto the
stack, loading the PC wi th the contents of the vector
location and loading the PS wi th the contents of the
vector location plus two.

3. Return from interrupt instructions execution times include
instruction fetch, instruction decode and popping the PC
and PS from the stack.

COMPANY CONFIDENTIAL
Page E-S

MISCELL~NEOUS

& CONDITION CODE INSTRUCTIONS

-------------------------------------------

DEST

CYCLES REQUIRED

1-------------------------------1
1

1 MODE 1 16 BIT MODE 1 8 BIT MODE
====================1==========1================1===============
1
1
1
HALT
1
NA
1
5
1
6
====================1==========1================1===============
WAIT
I
NA
I
1 then loop
1
2 then loop
====================1==========1================1===============
RESET
1
NA
1
1
1
2
====================1==========1================1===============
NOP
1 NA
1
1
1
2
====================1==========1================1===============
INSTRUCTIONS

CLC,CLV,CLZ,
CLN,CCC,SEC,
SEV,SEZ,SEN,
SCC

1
I

I
1

1
1

====================1==========1================1===============
1
NA
1
1
1
2
====================1==========1================1===============
MFPT

NOTES:

1. HALT execution times include instruction fetch,
instruction decode, writing the PC into location 4,
writing the PS into location 6, loading the PS with 340
and loading the PC with the RESTART address.
2.

WAIT
execution
times
include
instruction
fetch,
instruction decode, pulsing PI to sample the interrupt
lines and doing a REFRESH cycle if REFRESH is on.
(NOTE:
If no interrupt lines were sensed by the T-ll to be
asserted during the PI pulse, the WAIT instruction will cycle in a 2 micro-instruction loop (if REFRESH
is on the loop will be 2 1/3 micro-instructions max)
pulsing PI.
The looping will continue until an interrupt
line is sensed by the T-ll to be asserted.)

RESET execution times
include instruction fetch,
instruction decode, the assertion of -BCLR and the writing
of DAL<15:0> into the MODE register.

4. NOP execution times include instruction fetch, instruction
decode and idle time.
5.

Condition Code instructions execution times include
instruction fetch, instruction decode and the setting or
resetting of the appropriate status flags in the PS.

COMPANY CONFIDENTIAL
Page E-6