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Document:	DMF32 User's Guide
Order Number:	EK-DMF32-UG
Revision:	003
Pages:	150
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20
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EK-DMF32-UG-003

DMF32

USER’S GUIDE

Prepared by Educational Services
of
Digital Equipment Corporation

OSSN

Third Edition, December 1984

ARG

The reproduction of this material, in part or whole, is strictly prohibited.

For copy information, contact the Educational Services Department,
Digital Equipment Corporation, Bedford, Massachusetts 01730.

Printed in U.S.A.

The information in this document is subject to change without notice

and should not be construed as a commitment by Digital Equipment
Corporation. Digital Equipment Corporation assumes no responsibility
for any errors that may appear in this document.

The following are trademarks of Digital Equipment Corporation:

dlijgliltall I
-

DECtape

Rainbow

DATATRIEVE

DECUS

RSTS

DEC

DECwriter

RSX

DECmate

DIBOL

UNIBUS

DECnet

MASSBUS

VAX

DECset

PDP

VMS

DECsystem-10
DECSYSTEM-20

P/OS

Professional

Work Processor

CONTENTS

CHAPTER 1
1.1

GENERAL DESCRIPTION

INTRODUCTION ..ot
e e e e et e e e e e e e anna e e e aeesnnnnes 1

1.1.1

Asynchronous Multiplexer ..........e

1.1.2

Synchronous Interface................ e 2

1.1.3

Line Printer Interface ......cccocoevveeieriiiiicienneennne,reerr—————— e 3

114
1.2

e eeeaaeeetenn
et eran e eennaens 2

Parallel INterface .......cove e 3
PHYSICAL DESCRIPTION ..ottt
se e
ee e 3

1.2.1

DMF32 Configurations......ccccceeeeiieiiiieiiciiciees cerrrerreenneaenaennens &

1.2.1.1

DMF32-AA Option ........ccceeieieieennne. eeeeeeeeenneeeeeerernieeeeenaren 4

1.21.2

DMF32-AB OpPtion ....cocoeiiiiiiieeticeeee
e
e e e eeeeanes 5

1.2.1.3

DMF32-AC OPtion .cooceeveeicieeiereeeie
e st e e enr e e e e 5

1.2.2
1.3

TESt CONNECIOTS...ccuveeeieee
et teireeeetee st e et e s e enesebeessnneeeneneseennas 5
GENERAL SPECIFICATIONS. ...t 6

1.3.1

ENVIFONMENT ..ot e r e

1.3.2

Power Specifications ..........ccccevveiieiiiicnie

ee ee

ee 6

e, 7

1.3.3

UNIBUS Loads ....... e 7

1.34

DMF32 Functional Parameters.........ccoovuieiiiiiiiiemiiceneiieeeviee e, 7

1.3.5

DMF32 Performance Parameters ..................e rra——aaaa———— 8

1.3.6

Installation Distances.......cccooeveeeeieiiciiieiieeeeee
e,e

CHAPTER 2

a———— 9

INSTALLATION

2.1

SCOPE ...
e et
e e e e nat e e e e e aa e eeaens 11

2.2

UNPACKING AND INSPECTION ... 11

2.3

DEVICE AND VECTOR ADDRESS ASSIGNMENTS..........ceoiieriiienes 11

2.4

INSTALLATION PROCEDURE......ccoiteeeeereeeeeeerereceee 12

2.4.1

M8396 Module Installation ............eeveviiiiiniiiiriniiccreeeeecereeeenen,. 12

242

DMF32 Distribution Panel Installation...........cccccceeiiiiiiieneninnnn. 14

2.4.3

Distribution Panel Installation Procedure...........c.ccooevveeennnnnnnn.e. 14

244

BCO6R Cable Routing.....cc..cccen.......reeeseeamesusesertenrannriresaensarnnsnseens 17

245

Verifying Stand-alone Operation ............ccccceieiiiiriiciiiiiiiiiieeneeeen, 17

246

Communications Equipment Interface Cabling ......................... 19

2.4.7

Distribution Panel Switch Settings ........ccoveeieiiiiiiiin, 20

24.8

Verifying System-Integrated Operation..........cccccvveniiiiiiininnnnnnn. 21

iv.

TABLE OF CONTENTS

CHAPTER 3
3.1

DMF32 DIAGNOSTICS

INTRODUCTION .ot 23

3.1.1

DiagnoStiC SUPEIVISON .....cceuiiiieiiiiiinriiiieirisrrere e se e s e e e e reeeeneas 23

3.1.2

DMF32 CSR Address and Vector Address ........cccceevveeeveennnnee. 24

3.1.3

Hardware Loopback MethodS.......ccocceveevieiieeeeeicere

e 24

3.1.3.1

INternal Wrap ..oe e 24

3.1.3.2

H3248 Single-Line Loopback Connector ...........cccccce........ 24

3.1.3.3

H3249 Staggered Loopback Connector..........ccccevveevnnenee. 25

3.1.34

Local MOAeM ...t eeereaees. 20

3.1.3.5

Programmable Modem................et eenaeera
e e ra e anraan 27

3.14

Self TSt e
aaaees 27

3.1.5

3.2

DMF32 LEVEL 3 DIAGNOSTICS ...R 28

3.2.1

Level 3 Hardware PrerequisSitesS.......ccccvvieiiiiiiiiiiciiiie
e, 28

3.2.2

EVDLB Diagnostic Description.........c.ooeeeviiiiiiiiiiiieceeeeceee 28

3.2.2.1

Loading, Attaching, and Running EVDLB ......................... 28

3.2.3

EVDLC Diagnostic Description........cccccceviiereieiiinenannnnn. rn—— 30

Loading, Attaching, and Running EVDLC ......................... 30

3.2.3.1

3.2.4

EVDLD Diagnostic Description.........cccceevevvvivviinciceneennn.SUUUTRRN .. 30

3.2.4.1

Loading, Attaching, and Running EVDLD......................... 30

3.2.4.2

3.3

EVDLD Event FIags ......coeeriieiiieiiee e 32

DMF32 LEVEL 2R DIAGNOSTICS.......oicerceeeireeeee

e 32

3.3.1

Level 2R Hardware PrerequiSites .....c..ccovvveiiiiiiriiniiciiiii
e 34

3.3.2

EVDLA Diagnostic Bescription .........c.oevviiiiiieiiceiinieccriie. 34

Loading, Attaching, and Running EVDLA .............. UTUUR 34

3.3.2.1

EVDAC Diagnostic Description .........ccccoovieivirmiimiciiienn
e 34

3.3.3

3.3.3.1

Loading, Attaching, and Running EVDAC...................... . 34

CHAPTER 4
4.1

PROGRAMMING

INTRODUCTION ...
e 37

4.1.1

DMF32 CSR 0 ..ot
s e e e e e e e e e eeeeee s eee e e ann e 37

4.1.2

DMF32 CSR 1 Diagnostic Register........ccccccoevveieiiieiiiirieecennne, 39

413

4.2

DMF32 Device Control Status Registers..........ccccccveeevveenrennne.. 40

4.2.1

Synchronous Interface Protocol Support .......ccccceeeevveiereeeennene., 40
Synchronous Interface Baud Rate.........c...coovvveeeiiiiiiiienncennneee, 40

423

Synchronous Interface Device Registers .........cccoceeveeireeneeeenenn. 40

4.2.3.1

Receive Control Status Register ...........cccovvvevrvnniiininnnnnne, 41

4.23.2

Transmit Control Status Register..........ccccceervieniiinnnnnnnn... 41

4233

Miscellaneous RegiSter..........ccocvveveeeeeeecreeeeeeeeeereeeenennn. 42

4.3
4.3.1

SO,

SYNCHRONOUS INTERFACE.......cccoceeivieriierieeeeeeenen, ———— ceerereeen 40

4.2.2

4.2.3.4

reman—

Distribution Panel Switch SettingS........cooevviviiciiceiiinceereee, 27

Data Set Change Flag Register.........cccccovcceiiiiieiiiiciiinninne, 42

SYNCHRONOUS OPERATION .....ocoiiiiiiicccccceeeneeee
ee 42
Synchronous Transmit Operation ..........c.oovvvvevviiviieiieeiieeiiniinnes 42

4.3.1.1

Pretransmission Considerations..........ccccoevveevviiienricennennn. 42

4.31.2

Initiating TransSmMISSION ......c..veiiiiiiiriiiirercee
e, 43

4.31.3

Synchronous Interface Data Transmission....................... 43

4.3.1.4

Synchronous Interface Transmission Errors .................... 43

TABLE OF CONTENTS

4.3.2

Synchronous Receiver Operation ...............ccocevevieeeeeeeeeveennnn.. 44

4.3.2.1

Synchronous Receiver Synchronization................... v 44

43.2.2

Synchronous Interface Data Reception ...........ccccccceuu....... 44
Synchronous Interface Receiver Errors........cccocceeveeun..... 45

4.3.2.3
4.4

4.4.1

SYNCHRONOUS INTERFACE DEVICE REGISTERS.......cc............. 45

4.4.2

Receive Control Status Register..........coceeevveeeeereceoeeeeeeeeenenn. 45
Transmit Control Status Register ..........cccoevvvvvecviveceieeceene 50

443

Miscellaneous Register...............cc.............. e
e e e e ————— 54

444

Data Set Change Flag Register ...........cccceeeeeveevvceeeeeeeeeeennnnn... 56
SYNCHRONOUS INDIRECT REGISTERS ......ooooveeeeeeeeeeeeeeeeeeereeen, 57

4.5
4.5.1

Indirect Register [0] ... 58

4.5.2
453

Indirect Register [1] ..o 62
Indirect Register [2] ... 65

454

Indirect Register [3] .....cccoorieeeeeeeeeeeeee
e,
cee 67

4.5.5

Indirect Register [4] ..o 68

4.5.6

Indirect Register [5] ......cccveeimiieeeecc e, R 70

4.5.7

Indirect Registers [6] and [7] ..ccoooeeeeecieeemiiieieeceeeeeeeeeee 71

4.5.8

4.5.9

Indirect Registers [8] and [9]
....c..ovveeeveemeieeeeeeeeeeeeeee e 71
Indirect Registers [10] and [11] c.coooeeeeeeeieiieceeeeeeeeeeeeeeeaann. T2

4.5.10

Indirect Registers [12] and [13] .ccccovvreeeiieiieecceee e 72

4.5.11

Indirect Register [14] ... 73
Indirect Register [15] ......eueieeii
e eveeennnnnn.
eee T3

4.5.12

4.6
4.6.1
46.1.1

46.1.2
46.2

SYNCHRONOUS INTERFACE PHOTOCOLS ................................... 74
Bit-Oriented Protocol — Transmit Operation..........ccuu.......... e 74
Bit StUffiNg ... ceveranann 74
Bit-Oriented Protocol Transmrt Errors ..., 74
Bit-Oriented Prrotocol — Receive Operation...........ccceeeeunnn..... 75

4.6.2.1

Bit-Oriented Protocol Secondary Station Address........... 75

4.6.2.2

ADCCP Protocol................... ciresebersbrnsanaeseraransrnnransasansannennns 75

4.6.2.3

Bit-Oriented Protocol CRC .............................. 76
Bit-Oriented Protocol Receive Errors.........ccccoeeueeeeeueenn.... 76

4.6.2.4
4.6.3

DDCMP - Receive Operation..........cc.ceeeeeeveeeceeeceeaeeeeeeeeee 76

4.6.3.1

DDCMP Received Message......................... e 76

4.6.3.2

DDCMP Data Streams .......cccceeevueeeeicieiieieeceeeee

4.6.3.3

e 77
DDCMP Receive Synchronization ............ccccceevevvcnneeenn.... 77

4.6.4

DDCMP - Transmit Operation ...........coeeeueeeeeeeeeeeeeereeeeeeeeeeennnnn. 77

4.6.4.1

DDCMP Transmit Errors .......cccccceevvvceeeievccieereeeeeevevveeanen 17
General Byte-Oriented (GEN BYTE) ProtoCo! .........coeoveveeeunennn.. 78

4.6.5
4.6.5.1

4.6.5.2
4.6.5.3
4.7
4.7
.1

GEN BYTE ProtoCol ......cc..eeevuieeieeeiceeeeeeeeeeeee e, 78
GEN BYTE CRC ..ottt 78
Transmit Operation............ooocveerviieeeeceeeec e 78
ASYNCHRONOUS INTERFACE.........oo
et eeeee 78
Asynchronous Device RegiSters ..........c.cccvveeereiereeeicnieeeseeennn. 79

4.7.1.1

Control Status Register...........ccccuveeruunenn.....et ereer———— 79

4.7.1.2

Line Parameter Register..........ccocoueumieieeeeiiiecceceeenn, 79

4.7.1.3

Receive Buffer Register............cccccoeeuvuveennn..... S e 80
Receive Silo Parameter Register............cccccovuuvveeeeeeecnnnnnn.. 80

4.7.1.4

4.7.2
4.7.2.1

4.7.2.2

Asynchronous Device Operation..............cccccoveevevecnveeeeeeennennnnn.. 80
- Asynchronous Transmit Operation................ccocueveeeeenn.n... 80
Asynchronous Receiver Operation.............ccccceeveveennennn... 81

TABLE OF CONTENTS

4.8

ASYNCHRONOUS DEVICE REGISTERS.........ccoiiiiiirriiriierreinnnaes 81

4.8.1
4.8.2
4.8.3
4.8.4
4.9
4.9.1
492
493
494

Control Status Register ... 81
Line Parameter Register..........ooovviiiiiieiiiinicirienccen 84
Receiver Buffer Register .........ccccccviiniiniinnicniciicnnennicnenn.. 86
Receive Silo Parameter RegiSter .........ccccveerveieerveeerercesnenen, 88
ASYNCHRONOUS INDIRECT REGISTERS ......cooveeiciceecee, 89
Indirect Registers [0] Through [7]....ccoooeiiiiriiiiieeee 89
Indirect Registers [8] Through [15]....ccccoviiiiiiii, o1
Indirect Registers [16] Through [23](Read/Write)............. RO 95
Indirect Registers [24] Through [31]....ccooiiiiiiriiies 96

410

RELATIONSHIP BETWEEN MAINTENANCE MODES AND

MODEM SIGNALS... .o
e e e s e e e e s e e e 96

411

LINE PRINTER CONTROLLER......ccooiiiiieiraiiiireeereceiecerecnrceenieenns 99
4.11.1
Line Printer Controller Operation...........cueceeiieiminniienieeeieeneneeee 99
41111
Loading Line Printer CSR and Indirect Registers ............ 99
41112
Line Printing CyCle .........oevieriiiiiiiiiiiniii
s 100
412
LINE PRINTER CSR REGISTER ....ccoiieiiiiieeiieeeeeeececrcerceevennrnee 101
413
LINE PRINTER INDIRECT REGISTERS........ccoiiiiiiiiriieriieeeniis 105
414
PARALLEL INTERFACE (DR) ..cooieiieiiieiieiieeieieceeiecrccrtreereve
s 110
4141
'DR-11-C Functional Mode........ccccccceeiinniiinnnnnnnn. e —————— 110
41411
DR-11-C User Request
Aand B .......cccccvvecicenniineccnnnenn. 110
4.14.2
SO MOE ...vviiiieiieeiiceeieeeeeeeeereeeeeeeeee
e veeercenscencesneneseeseeenees. 110
4.14.21
Writing To and Reading From SilO.........ccoccvviiiiiiiiinnnnn. 110
414.2.2
Silo Request A and B.......cooooriiriiiieiierc 110
4143
DMA MOGE ....coeieeeieerieniietieree
s s e e s s e e e s ea e e e e e e eeeer e e s s ensennananans 111
4.14.3.1
DMA Transfer ...t
eeene 111
4.14.4
Parallel Interface Device Registers.......cccccceevvierivennnnnn. R 112
4.14.41
Parallel Interface Control Status Register ...................... 112
4.14.4.2
Parallel Interface Output Buffer........c.ccoooviiiiiiiiniinninnnn, 116
41443
Parallel Interface Input Buffer..........ccooooveeiiiiiiinnnnnnn, 117
414.4.4
Miscellaneous Register ..., 117
4145
Parallel Interface Indirect Registers.........cccccceeeeiiiniviirieeniicnnnn. 119
415
DIFFERENCES BETWEEN DMF32 AND THE DR11-C................... 120
416
DMF32 DRIVERS AND RECEIVERS ... 121

SYNCHRONOUS 25-PIN CINCH CONNECTOR .............. 123
APPENDIX A
ASYNCHRONOUS 25-PIN CINCH CONNECTOR............ 125
APPENDIX B
PARALLEL INTERFACE/LINE PRINTER SIGNALS ........ 127
APPENDIX C
DMF32 OPTION DESIGNATIONS........ooiiiiniieniienieeen, 129
APPENDIX D
se e e e e s e e e e e 129
INTRODUGCTION ..t
D.1
OPTION DESIGNATION CONVERSION.......coooiiiiiiiiiiiiiries 129
D.2
Factory-Installed System Oplions ... 130
D.2.1
e 130
Field Upgrade OptionS........ccoveiiiiiniiiinniieeens
D.2.2
Base OPtiONS .....ccccvurireiiiereiiisinriirinrree e 130
D.2.2.1
1= -1 1= PP 130
(0710111
D.2.2.2
OPTION CONFIGURATION SUMMARY .......cccccrvmmmniimmineianeieninnn, 130
D.3
- System Option Designations ............cc.coeeeieens criennaanesasesansten 131
D.3.1
Base Option Designations............ccceeennen.e rernr e 131
D.3.2
nsne 132
e
Cabinet Kit DeSignations .........cccovveereeecicinirninnie
D.3.3
DMF32 OPTION CONFIGURATIONS .......cooiiirieirnricenscinnneeeeens. 134
D.4

——

TABLE OF CONTENTS

vii

1-1

DMF32 Overview Block Diagram.........cccceeeeeeviieveeeieeecceeeecnee 1

1-2

DMF32 Components.........ccceeveeviveevieeieceeeeeeeeee, —————————— 4

1-3

DMF32 Test CoNNECLOrs .....cceviieeieeiieeeeeeeeeeeeeeee
e 6

2-1

DMF32 Switch Settings and Jumper Locations......................... 12

2-2

Shielded Bulkhead Type Panel ...............ccooeevveeriernnnnee. crve———— 14

2-3

H9544-SJ Frame Installation ............ccooeeeeeiieeiiiieiiieeecee

2-4

BCOG6R Cable ConNeCtioNS........c.uuviieiieeieeeeeeeieeeeeeeeeeeece. 16

e 15

2-5

DMF32 Distribution Panel Installation................ccceeveeeiieennnnnee.. 17

2-6

Staggered Connector Installation.............c.ccoeeeeveveeiiiceicnnieneen, 18

2-7

DMF32 Distribution Panel...........cccccoovvriiiiiiiiieeieieeveeeee. 19

3-1

Single-Line Connector Installation ...........cccccccevvviiiiiiccicneeeeeen... 25

3-2

Staggered Connector Installation............cccceeeviveeeeccieeeccccine, 26
CSR Device AdAreSSes ....c.cccueeiieeieeeeceiiereeeeeee e 38

4-2

CSR O e 39

4-3

Synchronous Receive CSR
.........cooieiiiieiee

e 46

Synchronous Transmit CSR.........cccceveviiciieie e, 50
4-5

Miscellaneous Register ...........ett

4-6

Data Set Change Flag Register .........ccoevevieveciieieeeiieeee e 56

4-7

Synchronous Indirect Register [0] ...........cc......... errn————————— 58

4-8

Synchronous Indirect Register [1] ......cooovvveeieeeiiiieiiicceeeeeeee. 62

e e e e et

e e e eeeran

aeraaa—a_, 55

4-9

Synchronous Indirect Register [2] .......ccovveeeeeeeiiieceiceeeeeenn. 65

4-10

- Synchronous Indirect Register [3] .......cccoevuivvveeeeeeeeeeeeeeeeenn. 67

4-11

Synchronous Indirect Register [4] ........cccovvvieeeiieeeciiceeee, v 68

4-12

Synchronous Indirect Register [5]......cocooveeiievieeiciiieeeeieeeeen 70

4-13

Synchronous Indirect Register [6] and [7] .......ccccvvvvevevverreerneenn... 71

4-14

Synchronous Indirect Register [8] and [9] .......ccoeevuevvvveeerenennn. 71

4-15

Synchronous Indirect Registers [10] and [11] ...cccovuvvivreeeenenn.. 73

4-16

Synchronous Indirect Registers [12] and [13] ..cccceeeeveecvvneneennn. 73

4-17

Synchronous Indirect Register [14].................. R e 73

4-18

ASYNChronous CSR..........uiicecccceececc
e 82

4-19

Line Parameter Register.........cccccveiiiieee e 84

4-20

Receive Buffer ....... e reeEaereeeeeaeeeeeettaereenn.—ereenaneeeerranetarerans 86

4-21

4-22

Receive Silo Parameter Hegnster. ............................................... 88
Asynchronous Indirect Registers [0] Through [7]...................... 89

4-23

Asynchronous Indirect Registers [8] Through [15]................ .. 92

4-24

Asynchronous Indirect Registers [16] Through [23].................. 95

4-25

Asynchronous Indirect Registers [24] Thmugh [31]........ .......... 96

4-26

Line Printer CSR.......coooiiiiieeeern

4-27

Line Printer Indirect Registers [6]........cccooeviveriiiiiieeieeiieceeeeeee, 109

4-28

Parallel Interface CSR ... 113

4-29

Miscellaneous Register ..........cccceeeiricieiee e 118
DMF32 Drivers and ReCeiVers ......ccovveeveeeveeeeneennnnn ererarenreennas 122

4-30

e 102

)

vii_

TABLE OF CONTENTS
O

Synchronous 25 Pin Cinch Connector........eeeeeieeree—————— 123
Asynchronous 25 Pin Cinch Connector........cccccceeeeeiceninnnnnnee. 125
BCOBR-"* Cable....cccoceeieeeieeeeeeeeee

e 135

DMF32 Distribution Panel.........ccoooeeiiiiiiiiciiiiniiiiceeien,eeeeee 135

H9544-SJ Adaptor Bracket ..........coeuiveeiimiiiiiiiiiniiiiinene 135

TABLES
1-1

DMF32-AA OPtONS ...coeeeeieeceeie et

1-2

DMF32-AB Option Additional Contents.........cocvveeiireeeiiinicinicnnns 5

e r e .5

1-3

Environmental Specifications .........ccccccc........et

1-4

Synchronous Functional Parameters...........coccevvcmineniinnienniinnncnn. 7

——————————— 6

1-5

Asynchronous Functional Parameters..........ccccceeviienieniiniiiininnn. 8

1-6

Parallel Interface Functional Parameters.............cccevviiiiniicennnnnen. 8

1-7

Printer Controller Functional Parameters............ccccoceiiiiiccviiinenen, 8

DMF32 Jumper FUNCLIONS .....ueiiiiiiiiiiee e 13
2-2

VAX Family Installation Manuals.........ccccccvvemrieeriniciiiciniicnnenn. 13

2-3

Level 3 Diagnostics...............eeeeesessesessseseernsraneeeneteertaaeeraeeaaaetaeaans 18

2-5

Common Switch Setups for Asynchronous Lines 0 and 1 ....... 20

2-6

Common Switch Setups for the Synchronous Line................... 20
DMF32 Device Configuration ........cccccceeviieviiiiiininieninnnnnnnn. cereees 21

2-8

Distribution Panel EIA Selection Jumpers.......cccoevvveiiiinieeninnnen. 21

2-9

DMF32 Level 2R Diagnostics.......cccccumemmieeiiiiiiciniennnn. e 21

3-1

Distribution Panel Switch Settings.................. eerernnrreraeeeeeereannaa 27

3-2

DMF32 Level 3 Diagnostic Parameters........c.cccccceeviieniiiniinninnnae 28

3-3

EVDLD Event FIags ....coocoiiieiinimrereneenrreeenerreeeeeeereeese
e e eeneeeeees OO

3-4

DMF32 Level 2R Diagnostic Parameters eererneeaerereneennran————_ 33

4-1

Device SeleCtioN ........oueuiiiiiiiiiiiieeererce
e
e 38
DMF32 Floating VeCIOrS........ccevieiiiiiiiiiiienrcce e 38

4-3

Recommended Cables........cocciiiiiiiiiiiiniiieiieeececeeeircc e 19

4-7

CSR 0 Bit Functions .........cccvvuveviiiieneiereeenenes fvessrersasrermasnancansnncese 39
CSR 1 High Byte FUNCLioONS ........coooviieiiiiiiiiincccennne, 39
Synchronous Receive Control Status Register Functions ........ 46
[0}
1 g F= U o Yo o TP 50
Synchronous Transmit Contm Status Register Functuons ....... 51

4-8

Transmit Clock Source Definitions ...........ccveviiiiiiniiiniinnicniinnn, 54

4-9

Miscellaneous Register Functions ............cccccncennnne.ereerrr——— 55

4-4

4-5
4-6

4-10

Receive Modem SignalS ......ccoiviiiieiiieiieiiimeeeee e 56

4-11

Synchronous Indirect Registers...........ccccvvviiimiieccceiininiiriennnennn, 57

4-12

Indirect Register [0] FUNCiONS........coevemviimieeiiiiniiniiennns ST 59

4-13

Error Control Codes ... ..o 59

4-14

Valid Error Control, Bits Per Character, and

Protocol Combinations ...........eeiiiiiiiiee
4-15

e 60

Protocol Selection.......cooo i 61

SOOI

[

TABLE OF CONTENTS

4-16

Receive Bits Per Character Selection ..........ccccccuuvvennnee. evvnnaan. 61

4-17

Transmit Bits Per Character............. ereeereeere
e an
U 62

4-18

Indirect Register [1] FUNCLIONS ......ccoovrviiiiiieiieeeee
e, 63

4-19

Indirect Register [2] Functions........cccccccveevveeriiiciciiniiececeeeeennen.. 66

4-20

Transmit Baud Rates.......coouuviiiiiiiiiiccceeeeeece
e 67

4-21

Indirect Register [3] FUNCHIONS ..........covvimmiiiiieeiircccsree
e 68

4-22

Indirect Register [4] FUNCHIONS......ccooecviiiiiee

4-23

Asynchronous Control Status Register Functions..................... 82

e, 69

4-24

Line Parameter Register FUNCHIONS ...........oiiiiiiiiiiiiiiiiice 85

4-25

Receiver and Transmit Baud Rates.......cccccccceeeieiiiiiiiiiiiiiinn, 86

4-26

Receiver Buffer Register Functions..................e ereere———————a———— 87

4-27

Receive Silo Parameter Register FUNctions............ccccceveueune.... 88

4-28

Indirect Registers [0] Through [7]Functions............................... 90

4-29

Indirect Registers [8] Through [15]Functions........ccccceeeeeeennnen. 92

4-30

Maintenance Control Function BitS............ccccoiviiriiiiiiiiiiiinnennen. 94

4-31

Relationship Between Maintenance Modes and Modem

SIgNAIS ..o erreee
e e —— 96
4-32

Line Printer Indirect Registers ..........oooeivmmiiecciiieiieneeceeeee, 101

4-33

Line Printer Control Status Register Functions ....................... 102

4-34

Line Printer Indirect Registers Functions ............cccccevrvvuvnnnnnnnn. 106

4-35

Parallel Interface Control Status Register Functions............... 113

4-36

Parallel Interface Miscellaneous Register Functions............... 118

4-37

Parallel Interface Operating MOdes ............cceceevevererreceenveennnes 118

4-38

Parallel Interface Indirect Registers Functions ........................ 119

4-39

DMF32 Drivers/Receivers and Associated Signals ................. 122

C-1

Parallel Interface/Line Printer Signals ............ccocvveiieiciiiiiannnnn. 127

D-1

Option Compatibility Cross Reference .........c.cccoeveeeeeeernneennnnne. 129

D-2

Electrical and Mechanical Interface Type........cccocevieiiecriiennannnn. 131

D-3

Cabinet Kit COMPONENLS .......cccoeueecrieiriiiieeeeeeeeei
e s e s ee e 133

D-4

DMF32 Option Configurations..........cccccceveeiiiriiniinnnennn.SUTRR 134

3-1

Loading, Attaching, and Running EVDLB.........ccccccieiiiiiiinnnnnn. 29

3-2

Loading, Attaching, and Running EVDLC............ccccoieiiiiiriininnns 31

3-3

Loading, Attaching, and Running EVDLD........c.ccccoeeiiiiiinnnnnnn.e. 32
EVDLD Event Flag INStruCtions...........cooiciieiininiiiieceee
e 33

3-5

Loading, Attaching, and Running EVDLA...............eviiiiiiinnninnn. 35

3-6

Loading, Attaching, and Running EVDAC ............cccoviiiiinnnnnn, 36

1.1

INTRODUCTION

The DMF32 is an intelligent VAX family DMA UNIBUS controller that supports a

combination of 1/O devices, including the following (see Figure 1-1):

e Eight asynchvmnous lines
® One synchronous line

¢ One DMA line printer interface
or one enhanced DR11-C functional parallel
1/O port

DMF32

VAX

SYSTEM

UNIBUS

ASYNC | SYNC

8 ASYNC LINES

LINES O & 1

FOR REMOTE

TERMINALS

l MODEM

1 ]

EXTERNAL

ERINTER
—— — —

PARALLEL
INTERFACE

CUSTOMER

EXTERNAL
MODEM

LP32
LINE PRINTER

LINES 2-7

FOR LOCAL

TERMINALS

.
£

M)g![;&;:fiwm

‘

TWORK

COMM

FACILITY
TK-8584

Figure 1-1

DMF32 Overview Block Diagram

GENERAL DESCRIPTION

1.1.1

Asynchronous Multiplexer

The asynchronous multiplexer supports eight transmit and eight receive lines.
Each pair of lines (one transmit and one receive) can be programmed to operate

at one of 16 baud rates ranging from 50 bps to 19.2 Kbps. Both line 0 and line 1

have split-speed capability and full modem control. The asynchronous multiplexer also supports the auto echo function.

Transmission can be selected for DMA or SILO operation. In SILO mode, each
line transmits characters from its own 32-character buffer. These buffers are

loaded under host software control. In DMA mode, a transmit line transmits

characters from the main memory location specified by the buffer address and
character count.
B

All eight lines share a 48-character receive silo. There is a programmable silo
timeout period for the receive silo.

An interrupt can be generated under one of the following conditions:

e Sixteen characters have entered the silo
e The silo has been non-empty for a time greater than a programmable
timeout period. This timeout period can be set to zero.

The asynchronous lines are connected either to data terminal equipment (DTE)

or data communications equipment (DCE) via standard EIA RS-232-C 25-pin
connectors. The signal levels of the asynchronous multiplexer are RS423 compatible (1 second rise time).
1.1.2

Synchronous Interface

The synchronous interface is a single-line DMA communications device with full

modem control (EIA RS-232-C/CCITT-V.28). The signal levels of the synchronous interface are RS423 compatible (1 second rise time). The DMA transfers
are double buffered; that is, both the transmitter and receiver have two sets of

byte count and buffer address registers.
The synchronous interface supports various bit-oriented protocols (SDLC and
HDLC) and byte-oriented protocols (DDCMP). The synchronous line can frame
the messages, generate and check CRC, and DMA these messages to and from
host memory. The host-level software performs all message acknowledgments

and higher level network functions.

GENERAL DESCRIPTION

Running the GEN BYTE protocol (general byte-oriented synchronous) allows

the synchronous interface to implement any byte-oriented protocol. The GEN
BYTE protocol uses a straight transfer of data between main memory and the
synchronous interface. The host-level software handles the protocol-specific
functions.

The synchronous interface has modem control. The modem lines conform to

EIA RS-232-C/CCITT-V.24 specifications for speeds up to 19,200 bits per second. The synchronous interface is connected to DTE or DCE via the standard
25-pin Cinch connector. Direct connection to another synchronous interface
can be done via a null modem cable.

When using the DMF32 crystal-controlled baud rate generator, the synchro-

nous line can transmit at one of sixteen different programmable speeds. With
external clocking, any transmit or receive bit rate up to 19.2 kbps can be used.
The receiver uses an external clock originating from the modem, except during
maintenance testing.

1.1.3

Line Printer Interface

The DMA line printer operates with the LP32 family of printers. This interface

also supports low-level formatting functions.
1.1.4

Parallel Interface

This 16-bit parallel interface is an enhanced DR11-C functional interface. It can

also support SILO mode (half-duplex) or double-buffered DMA (half-duplex).
Since the line printer interface and the parallel interface share hardware, both
interfaces cannot be used concurrently.
1.2 PHYSICAL DESCRIPTION
The DMF32 consists of a single hex-size peripheral controller (SPC) module, an

8.25-inch X 4-inch distribution panel, and three 40-pin shielded BCO6R flat
cables. The three BCO6R cables connect the single hex module to the distribution panel via standard Berg connectors. Refer to Figure 1-2 for the DMF32
components.
~

The distribution panel has eleven Cinch connectors. Eight connectors are for
the eight asynchronous lines, one connector is for the synchronous line, and
two connectors are for the parallel port. The distribution panel also has three
10-position DIP switch packs.

GENERAL DESCRIPTION

- M8396 MODULE

[Jers

L—ll—ll—

Rm/

_ GREEN

LED

BCOBR CABLE

DISTRIBUTION PANEL

@
@
@Asvcuaom_gus EfA

@
@ N
@ 2890080 omF32 DIST. PANEL

FRONT VIEW

REAR VIEW
TK-BGAG
o

Figure 1-2

1.2.1

DMF32 Components

DMF32 Configurations

The DMF32 is available in three different options; each is designated by two

letters (AA, AB, or AC). These options are defined in the following paragraphs.

1.2.1.1 DMF32-AA Option - The DMF32-AA option is used in the VAX-11/730

system packages. Table 1-1 lists the contents of this option.

GENERAL DESCRIPTION

Table 1-1

Quantity

Part Number

M8396

3
1
1
1
1

BCO6R-7
70-18754-00
H3248
EK-DMF32-UG
MP01271

DMF32-AA Options

Description
|

Hex module

40-conductor cable
Distribution panel assembly
Single-line loopback
DMF32 User’s Guide
DMF32 Field Maintenance Print Set

1.2.1.2 DMF32-AB Option - The DMF32-AB option is used in the BA11-KW
expander cabinets. This option is identical to the DMF32-AA except that it has
three BCO6R-10 cables instead of three BCO6R-7, and contains the additional
items listed in Table 1-2.

Table 1-2

DMF32-AB Option Additional Contents

Quantity

Part Number

Description

74-27040-01

H9544-SJ frame, |/O non-shielded

4
4
4

1.2.1.3

90-09700-00
90-06664-00
90-07786-00

Screws, Sems Truss Phillips
Washer, flat SST
Nut, U-nut Retainer (.240 inside diameter)

DMF32-AC Option — This option is identical to the DMF32-AA except

that it has three BCO6R-12 cables instead of three BCO6R-7 cables.
1.2.2

Test Connectors

The H3248 and H3249 test connectors, shown in Figure 1-3, are used with the

DMF32. Only the H3248 test connector is included in the DMF32 options. The
H3248 plugs into the distribution panel to loop back data and modem signals on

a single line. The H3249 test connector connects to
M8396 module via the
three BCO6R cables. This arrangement provides staggered turnaround of the
data and modem lines, testing both the M8396 module and cables.

GENERAL DESCRIPTION

DISTRIBUTION PANEL

@
@
® asvcrroNOUS EIA

@
@
@ BOEBOBN omr32 DIST. PANEL
40

)

s————y

; .

XXX wW

. .

.:
.

H3249 STAGGERED

TEST CONNECTOR

OF DISTRIBUTION

REAR VIEW

PANEL)

FRONT VIEW

H3248 SINGLE LINE

TEST CONNECTOR

(PLUGS INTO J4-J12 OR

END OF A BC22 CABLE

TK-B645

Figure 1-3

1.3

DMF32 Test Connectors

GENERAL SPECIFICATIONS

This section provides the information on the necessary environment, power
specifications, device functional specifications, and performance parameters.
1.3.1

Environment

Table 1-3 lists the environment specifications for the DMF32.

Table 1-3

Environment

Environmental Specifications

Specification
RN

Class B Environment

10C (50°F) to 40C (104°F)

Operating Temperature

Where maximum temperature is reduced 1.8°C per
1000 meters (1°F per 1000 feet) of altitude

Relative Humidity

10% to 90% with a maximum wet bulb of 28°C (82°F)
and a minimum dewpoint of 2°C (36°F)

Cooling

11 cubic feet per minute

Heat Dissipation

175 BTU per hour

[

1.3.2

Power Specifications

The SPC slot the DMF32 is plugged into provides the power for the DMF32.
The electrical requirements are as follows:

8.0 amperes @ +5 Vdc
0.5 amperes @ +15 Vdc
0.5 amperes @ —15 Vdc
1.3.3

UNIBUS Loads

The DMF32is equivalent to 1 dc UNIBUS load.
The DMF32 is equivalent to 6 ac UNIBUS loads broken down as follows:

1.3.4

MSYN

2.3

ac loads

SSYN

2.2

ac loads

BBSYN

5.5

ac loads

DMF32 Functional Parameters

Tables 1-4 through 1-7 list the functional parameters for the devices of the
DMF32.

TWM@ 1"'“

sYflch NOUs F

‘

rarameiers

Parameter

Description

DMA Transfer

Double-Buffered

Protocols Supported

DDCMP, BI-SYNC, HDLC, GEN BYTE

Protocol Functions

Bit stuffing, bit removal, cyclic redundancy
check generation and mwgmtmn framing
messages

Modem Lines

EIA RS-232-C/CCITT-V.24

Data Rates

800, 1200, 1760 2152, 2400, 4800,9600 and

19200 bits per second using mmmauy generated transmit clock

GENERAL DESCRIPTION

Table 1-5

Asynchronous Functional Parameters

Parameter

Description

Operating Mode

Full-duplex or half-duplex

Data Format

Asynchronous, serial by bit, one start bit, and 1 or 2

stop bits provided by the hardware under program
control.

Character Size

5, 6, 7, or 8 bits, program-selectable. (Does not
include the parity bit.)

Parity

Parity is program-selectable. There can be odd,
even, or no parity. If parity is selected, a parity bit is
added to the character in the MSB position.

Order of Bits

Transmission/reception low-order bit first

Data Rates

50, 75, 110, 134.5, 150, 300, 600, 1200, 1800, 2000,
2400, 3600, 4800, 7200, 9600, and 19200 bits per
second

Split Speed

Line 0 and line 1 only

Full Modem Control

Line 0 and line 1 only

Asynchronous Lines

RS-232-C compatible

Table 1-6

Parallel Interface Functional Parameters

Parameter

Data Input

Description

16 bits parallel in

Data Output

16 bits parallel out

Electrical Signals

Similar to the DR11-C

Table 1-7

Printer Controller Functional Parameters

Parameter

Description

Printer Supported

LP25, LP26, LP27, LPO7

Formatting Capabilities

Tab expansion, lower case to upper case conversion, line wrap, ff to If conversion

1.3.5

DMF32 Performance Parameters

Each of the eight asynchronous lines may transmit and receive at a maximum

speed of 19,200 bits per second. The synchronous line may transmit and
receive at a maximum speed of 19,200 bits per second. However, all of these
lines may not operate at their maximum speed concurrently.

GENERAL DESCRIPTION

1.3.6

Installation Distances

The recommended distance from the DMF32 to the RS-232-C/CCITT-V.24
terminal or modem is 15 meters (50 feet) at up to 9600 bps with a BC22 or

similar cable. Operation which exceeds 50 feet does not meet the distances

recommended in RS-232-C/CCITT-V.24. Operation is often possible at longer

distances, depending on the terminal equipment, type of cable, speed of opera-

tion, and electrical environment. For these reasons, DIGITAL cannot guarantee
error-free operation at distances greater than 15 meters (50 feet).

The DMF32 can be connected to local DIGITAL terminals (and most other terminals) at distances greater than 50 feet with acceptable results if the terminal and

computer are in the same building, in a modern office environment. A shielded
twisted pair cable (Belden 8777 or equivalent) is recommended and used in the

BC22D null modem cable.

NOTE
The ground potential difference between the DMF32 and the terminal

must not exceed two volts. This condition limits operation to within a single building served by one ac power service.

INSTA
2.1

SCOPE

\TION

This chapter describes the procedures for unpacking, installing, and checking

out the DMF32.

NOTE
-

Unless otherwise indicated, all numbers in this manual that refer to addresses

Or data are in hexadecimal format.

2.2

UNPACKING AND INSPECTION

The DMF32 is packed according to commercial packing practices. Remove all
packing materials and check the equipment against the shipping list. Table 1-1

lists the items contained in the DMF32 options. Inspect all items and carefully
check the module for cracks, loose components, and breaks in the etched
paths. Report damages or missing items to the shipper immediately and inform

the DIGITAL representative.

The DMF32’s device addresses are mw

M fmm 'th@ flmatmg address space of

the UNIBUS input/output (I/O) page. The E75 switch pack on the DMF32
selects the first DMF32 CSR address. The DMF32 calculates the other DMF32

CSR addresses from the first address.

When there are no floating devices before the DMF32, the first floating address

space for a DMF32 is 760340 (FEOEO hex). The second floating address space
for a DMF32 is 760400 (FE100 hex). The third floating address space for a

DMF32 is 760440 (FE120 hex). When operating under VMS, the actual
address(es) can be determined by using the SYSGEN utility. Refer to the VAX/

VMS Guide to Writing a Device Driver (AA-H499B-TE) for the procedure to
determine CSR address assignments.
There are no swstchas on the DMF32 for mtmrwpt wctms, At autoconfigure

time, the operating systemloads the

value

of the base
vector into the DMF32.

The DMF32 ca&culmm the o ;mr DMF32 mcmm from tmg base vector.

INSTALLATION

M8396

SWITCH E77

SWITCH E75

W3 W6

W5 w4

SWITCH PACK E77

SWITCH PACK E75
9

LSELF TEST

]

ON — DMA SELF TEST
FAILS — JUMPS TO

INIT

SPECIFIC ERROR LOCATION
(NORMAL OPERATION)
OFF — DMA SELF TEST

UNIBUS ADDRESS

ON — UNIBUS INIT

(NORMAL OPERATION)

OFF — FORCES INIT

SINGLE STEP

OFF — RUN MODE
(NORMAL OPERATION)
ON — SINGLE STEP MODE

FAILS — SELF TEST LOOPS

SELF TEST
ON — PERFORM DMA
SELF TEST
OFF — DISABLES DMA
SELF TEST
~

11
2

ADDRESS | BIT
RANGE [ SW# |

12
1

760340
760400
760440
| 760500

ON
ON
ON
ON

760640
760700

ON
ON_|
ON | ON

10
3

9
4

| ON | ON | ON
| ON | ON | ON
ON | ON
| ON
| ON | ON | ON

8
5

7
6

6
7

DEVICE

3
PRIORITY | Sw# | 2
oN T OFF
5
TTON
oFF
6

lo
g8
7
6
5
4
ON
TOFF | OFF | OFF| ON | ON_|
T7oN T ON | ON | OFF | OFF | OFF

5
8

| ON | OFF | OFF | OFF
| OFF| ON | ON | ON
| OFF| ON | ON | OFF
| OFF | ON | OFF | ON |

ON | ON | ON| ON | OFF | ON | OFF | OFF|
ON | ON | ON | ON | OFF | OFF | ON | ON

760540
760600

ON | ON |

| 760740

ON_|
ON

ON [ ON | ON

761000

ON| OFF | OFF | ON | OFF
ON | OFF | OFF | OFF | ON

ON | OFF | OFF | OFF | OFF
OFF|

ON | ON | ON | ON

TR B8589

Figure 2-1

2.4

DMF32 Switch Settings and Jumper Locations

INSTALLATION PROCEDURE
J———

2.4.1 M8396 Module Installation
To install the M8396, perform the following steps.

1. Set the switches on the E77 switch pack to the correct priority level; also
set switch 1 (E77) to ON and switch 10 (E77) to OFF. Refer to Figure 2-1
for the switch settings. Also confirm that all eight jumpers are installed on
the DMF32. Table 2-1 lists the DMF32 jumper functions, and Figure 2-1
shows the jumper locations.

2 Set the switches on E75 for the DMF32 CSR address. Refer to Section
2.3 and Figure 2-1 for the correct E75 switch settings.

INSTALLATION

Table 2-1

DMF32 Jumper Functions

Jumper

Name

UNIBUSINIT

Function
|

Out - Disables UNIBUS Init
In - Enables UNIBUS Init

SYNC DSR

Always installed

RXDRTN

Always installed

DSR RTN

Always installed

DCETX CLKRTN

| Always installed

DCE RXCLKRTN

Always installed

ASYNC 0 DSR

Always installed

ASYNC1DSR

Always installed

3. Set switch 1, the three-position toggle switch on the M8396 module, to
the CENTER position. Refer to Figure 2-1 for the location of S1.
4. The DMF32 can be installed into any slot that provides 8 amperes at +5V

and 0.5 amperes at +15V and —15V. It is recommended that no more than
three DMF32 units be installed per DD11-DK backplane and that 2-foot

UNIBUS cables (M9202) be used to interconnect backplanes within the

same box. Refer to the appropriate VAX-11 installation manual for the

location of SPC slots into which the DMF32 can be installed. Table 2-2
lists the VAX family installation manuals.

5. For each slot in the backplane where a DMF32 is to be installed, remove

the NPR jumper from pins CA1 to CB1 on the backplane.

CAUTION
Do not insert or remove the M8396 module with power ON. Insert and
remove the module slowly and carefully to avoid catching components

on the card guides or changing the switch settings.
Table 2-2

VAX Family Installation Manuals

VAX System
Number

Title

Document

VAX-11/780

VAX-11/780 Installation Manual

EK-SI780-IN

VAX-11/750

VAX-11/750 Installation and
Acceptance Manual

EK-SI750-IN

VAX-11/730

VAX-11/730 Installation Guide

EK-SI1730-IN

INSTALLATION
O

2.4.2

DMF32 Distribution Panel Installation

The DMF32 distribution panel is mounted in either a H9544-SJ mounting frame
or a shielded bulkhead panel. To mount the distribution panel into the frame
opening, position the distribution panel at an angle so that the lip of the distribution panel is behind the frame. The distribution panel is secured to the frame by
eight screws.

The BCO6R-XX cables are connected from M8396 J1 to distribution panel J1, J2
to J2, and J3 to J3. To connect the cables in this way, the cables for J1 and J3
are crossed over. When connecting each cable, make sure that the cable’s rib
side is facing up and the red strip is on the correct side.

2.4.3 Distribution Panel inatallation Procedure
1. Determine if the system/expander cabinet has a shielded bulkhead type
panel included as part of the cabinet. If the system/expander cabinet

DOES contain a shielded bulkhead type panel, continue with Step 2. If
system/expander cabinet DOES NOT contain a shielded bulkhead type
panel, proceed to Step 4.
e

2. Remove the four 2 inch plates from the bulkhead panel to enable mounting
the DMF32 distribution panel (refer to Figure 2-2).

REMOVE 4 PLATES

o N o\L /O
\

o\x O o) /o

—————
N
A
.
Y

m—
2

SHIELDED BULKHEAD TYPE PANEL

SPACE FOR SECOND DMF32
TH-H647

Figure 2-2

Shielded Bulkhead Type Panel

INSTALLATION

3. Discard the H9544-SJ ‘“‘picture frame’’ (see Figure 2-3) from the DMF32'AB option package, since the frame is not used with the

system/expander

cabinets that contain the shielded bulkhead type frame. Now proceed to

Step 7.
4. Remove the H9544-SJ picture frame from the DMF32-AB option package.
Refer to Figure 2-3 to identify the frame.

5. Align the H9544-SJ frame on the cabinet vertical rails in the desired location. Mark the rail holes for reference, then install the U-nuts supplied with

the option (see Figure 2-3).
6. Mount the H9544-SJ frame to the vertical rails of the cabinet with the
screws and washers supplied.

oy
NM‘!\«

CABINET
RAIL

TE-9833

Figure 2-3

H9544-SJ Frame Installation

INSTALLATION

7. Install the BCO6R-XX cables, if these cables have not yet been installed.

The BCO6R-XX cables are connected from the M8396 module to the

DMF32 distribution panel: J1 to J1, J2 to J2, and J3 to J3. To make these

connections, cables from J1 and J3 must be crossed (see Figure 2-4).
Refer to the proper VAX-11 installation manual for the proper cable routing. Table 2-2 list the VAX-11 installation manuals.

Connect the BCO6R-XX cables to J1, J2, and J3 of the M8396 module.
Pull the ends of the three BCO6R-XX cables through the H9544-SJ/
shielded frame bulkhead opening that the DMF32 distribution panel is to
be mounted in.

CAUTION
Connecting the BCO6R-XX cables incorrectly can cause damage to the
parallel port on the M8396.

M8396 MODULE

DISTRIBUTION

RIB SIDE UP

PANEL

3| o1

RED STRIPE

TK-8585

Figure 2-4

10.

BCO6R Cable Connections

Connect the three BCOBR-XX cables to the distribution panel, making sure
that the cable’s rib side is up and the red strip is on the correct side (see
Figure 2-4).

11. Position the distribution panel at an angle so that the lip of the distribution

panel is behind the frame (see Figure 2-5).
12. Secure the distribution panel to the frame with the eight capture screws

(part of the distribution panel).

INSTALLATION

2.4.4

BCO6R Cable Routing

Refer to the appropriate VAX-11 installation manual for the BCO6R cable rout-

ing. Table 2-2 lists the appropriate VAX family installation manuals.

»Y

/ /|

.
/

‘

H9544-8J

FRAME

/
SYNC PORT EIA

PARALLEL IN

LP32 OR PARALLEL QUT

t.”.:“.:":::”.‘.'..‘.‘.‘.‘m 3(}0{?” ............................. ?Q

DISTRIBUTION
P ANEL

Ltp

@
Tr-8648

Figure 2-5

DMF32 Distribution Panel Installation

2.4.5

Verifying Standalone Operation

Run the Level 3 diagnostics with the H3249 staggered turnaround connector to

verify the standalone operation of the DMF32. To verify the standalone operation, perform the following steps.
1. Connect the staggered turnaround connector (see Figure 2-6).

2. Run the Level 3 diagnostics listed in Table 2-3.
NOTE
When the system is powered up, the green LED (D1) on the M8396 board

should be on. This means that the DMF32 microcode is running.
3. Disconnect the H3249 staggered turnaround connector. Connect the
three BCO6R cables to the distribution panel as shown in Figure 2-6.

INSTALLATION

DISTRIBUTION PANEL

(BACK SIDE — VIEW)

RIB SIDE
OF CABLE UPe=
RED EDGE
TO LEFT

FROM J1 OF DMF32
FROM J2 OF DMF32
FROM J3 OF DMF32

STEP 1 — DISCONNECT THE THREE DMF32 CABLES FROM
BACK SIDE OF THE DISTRIBUTION PANEL

PO,

H3249

STAGGERED WRAP
Y

RiB SIDE
OF CABLE UP
RED EDGE

TO LEFT

FROM J1 OF DMF32

FROM J2 OF DMF32
FROM J3 OF DMF32

STEP 2 — CONNECT THE THREE DMF32 CABLES
TO THE STAGGERED WRAP
TR 8586

Figure 2-6

Staggered Connector Installation

Table 2-3

Level 3 Diagnostics

Diagnostic

Section Tested

Operating Instruction

EVDLB

Synchronous port

| Section 3.2.2

EVDLC

Asynchronous port

Section 3.2.3

|
OB

EVDLD

Parallel port

Section 3.2.4

INSTALLATION

2.4.6

Communications Equipment Interface Cabling

Connect the cablesfmm thedisa ~”butwnpanel t

printers, terminals, etc. Fig

panel. Table 2-4 hsm tm rmmm@n dedcmbmfi

SWITCH 1

SWITCH 3
SWITCH 2
J5

O
PARALLELIN _

LP32OR PARALLEL OUT

TR BE44

Figure 2-7

DMF32 Distribution Panel

Table 2-4

Recommend

Cmbm

BC22E
BC22F

BC27A*

LP25, LP26

BC27B

LPO7

* The BC27A cable or the BC27B cable is provided with the LP32 option.

INSTALLATION

2.4.7

Distribution Panel Switch Settings

Set the switches of the three switch packs on the distribution panel. Refer to

Figure 2-7 for the switch pack locations. Table 2-5 lists the switch settings for
the asynchronous line 0 (switch 1) and asynchronous line 1 (switch 2). Table 2-6
lists the switch settings for the synchronous line (switch 3). Table 2-7 lists the

switch settings (switch 3) for the DMF32 device configurations. Table 2-8 shows
the functions of jumpers W1 and W2 on the distribution panel. Both jumpers are
normally installed.

Table 2-5

Common Switch Setups for Asynchronous Lines 0 and 1

Switch Packs
1and 2

Local
Terminal

Modems and H3248
Single-Line Connector

Switch 1

OFF

Switch 2

Switch 3

OFF

Switch 4

Switch 5

Switch 6

Switch 7

Switch 8

OFF

Switch 9

Switch 10

Table 2-6

Common Switch Set-ups for the Synchronous Line

Switch Pack 3

Modems and H3248 Single
Line Loopback Connector

Switch 1

Switch 2

Switch 3

Switches 6-10

Not used

INSTALLATION

Table 2-7

DMF32 Device Configuration

Switch Pack 3

Switch 4 ON

Switch 5 ON

Asynchronous

Switch 4 OFF

Switch 5 ON

Asynchronous, LP32

Switch 4 ON

Switch 5 OFF

Asynchronous, parallel

Switch 4 OFF

Switch 5 OFF

—
L

Active Device

interface, synchronous

Asynchronous, LP32,
synchronous

Table 2-8

Distribution Panel EIA Selection Jumpers

Jumper Wi

JumperW2

In or Out

Out

Function
Signal ground connected directly to

frame ground

Signal

ground

connected

frame

ground through 100-ohm resistor

Out

Signal ground isolated from frame

ground

2.4.8 Verifying System-integrated Operation
To verify system-integrated operation, run the DMF32 Level 2R diagnostics as

follows:

1. Place all modems into loopback mode.

|
-

2. If modem loopback mode is not available, install a H3248 single-line loopback connector on one of the asynchronous connectors, and install a
H3248 single-line loopback connector on the synchronous connector.

3. Run the DMF32 Level 2R diagnostics listed in Table 2-9.
Table 2-9

DMF32 Level 2R Diagnostics

Diagnostic

Section Tested

Operating Instruction

EVDLA

Synchronous port

3.3.2

EVDAC

Asynchronous port

3.3.3

INSTALLATION

Return all modems to the normal mode of operation.
Disconnect the H3248 single-line connector and reconnect any disconnected cables.

Set the three switch packs on the distribution panel for normal mode of

—

operation. Refer to Tables 2-5, 2-6, and 2-7 for the switch settings.

The attached devices can be verified by running the following user-level
diagnostics.

EVAAA - Line Printer Diagnostic
EVTAA - Terminal Diagnostic

EVTBA - Terminal Exerciser
EVDLF - Data Link Test

R
—

DMF32 DIAGNOSTICS
3.1

INTRODUCTION

This chapter describes using the DMF32 diagnostics. The DMF32 is supported
by both Level 3 and Level 2R diagnostics. The Level 3 diagnostics are standalone diagnostics that run under the Diagnostic Supervisor using direct 1/O.
There are three Level 3 diagnostics: EVDLB, EVDLC, and EVDLD. These diagnostics verify the functionality of the DMF32 as follows:
EVDLB-verifies the synchronous interface
EVDLC-verifies the asynchronous multiplexer
EVDLD-verifies the parallel interface

The Level 2R diagnostics enable fault isolation to the option level while running
under VMS. Various loopback methods can be used at either the distribution

panel connector, modem cable, local modem, or remote modem. These various
loopback methods can isolate the fault to a specific component of the network.

Also, the Level 2R diagnostics can be used to provide a complete link between
the DMF32 and another DMF32 or similar device for end-to-end function
verification.

The Level 2R diagnostics, running under the Diagnostic Supervisor, use the
QIO interface of the VMS device driver. There are two DMF32 Level 2R diagnostics: EVDAC and EVDLA. EVDAC verifies the functionality of the asynchronous multiplexer, and EVDLA verifies the functionality of the synchronous
interface.

3.1.1

Diagnostic Supervisor

Both Level 3 and Level 2R diagnostics run under the Diagnostic Supervisor.
Loading and using the Diagnostic Supervisor are described in both the
' VAX-11/730 Diagnostic System Overview Manual (EK-DS730-UG) and the VAX
Diagnostic System User’s Guide (EK-VX11D-UG).

DMF32 DIAGNOSTICS

3.1.2 DMF32 CSR Address and Vector Address
The DMF32 CSR address 760340 is used as an example address in the following diagnostic procedures. The actual address depends on the switch settings

of E77 on the DMF32.

The vector address is used as an example address. The actual address is float-

ing; thus the vector address depends on the UNIBUS configuration.

When running under VMS, the actual CSR address and vector address can be

determined. Use the VMS utility SYSGEN to determine the actual addresses.

BRI

om0

3.1.3

Hardware Loopback Methods

There are five loopback methods that can be used in running the DMF32 diagnostics. These loopback methods are sometimes referred to as “wraps’”. The

five loopback methods are as follows:
® [nternal wrap

H3248 single-line loopback connector

H3249 staggered loopback connector

Local modem
Programmable modem

[r—

3.1.3.1

Internal Wrap - The internal wrap enables the data to be internally
looped within the DMF32. No external loopback connector is needed with the

pr——

internal wrap. This wrap tests the DMF32’s functionality (except the drivers, the

receivers, the cables from the DMF32 to the distribution panel, and the distribu-

tion panel).

3.1.3.2

H3248 Single-Line Loopback Connector - The H3248 single-line loop-

back connector can be used when running the synchronous or asynchronous
diagnostics. When the H3248 is used, the functionality of the drivers, receivers,
cables from the DMF32 to the distribution panel, and the distribution panel are

verified. The H3248 single-line loopback connector is connected to the line that

is to be tested. Figure 3-1 shows how the H3248 single-line loopback connector

is connected.

DMF32 DIAGNOSTICS

DISTRIBUTION PANEL

@
@
@ SH00020 omF32 DIST. PANEL

O Qooo

00 00

{EQQE} BEARsES

@
@
@ASYCHRONOUS ELA

H3248 SINGLE LINE
TEST CONNECTOR
TR-8E61

Figure 3-1

3.1.3.3

Single-Line Connector Installation

H3249 Staggered Loopback Connector - The H3249 staggered loop-

back connector can be used with any of the diagnostics, except EVDAC. This
loopback connector is used to test the functionality of the DMF32 up to the distribution panel (exclusive of the distribution panel). The H3249 staggered loopback connector is required to test specific asynchronous multiple functions and
to loop back the parallel port. Figure 3-2 shows how the H3249 staggered loopback connector is connected.

The dip switch pack on the H3249 staggered loopback connector is used for the
following purpose. Switch 1 (H3249) is equivalent to switch 4 of SW-3 (distribution panel), and switch 2 (H3249) is equivalent to switch 5 of SW-3 (distribution
panel). Both switches 3 and 4 (H3249) are not used. Refer to Table 2-7 for the
equivalent switch positions of switches 1 and 2 (H3249).
The H3249 staggered loopback connector is part of each spares kit.

DMF32 DIAGNOSTICS
T,

DISTRIBUTION PANEL

(BACK SIDE — VIEW)
s

L 1

1 ]

‘!|llill

RIB SIDE

THREE DMF32

‘
OF CABLE uP wrm

cABLES

TO LEFT
FROM J1 OF DMF32
FROM J2 OF DMF32
FROM J3 OF DMF32

STEP 1 — DISCONNECT THE THREE DMF32 CABLES FROM

AR,

BACK SIDE OF THE DISTRIBUTION PANEL

H3249
STAGGERED WRAP
Ll

L]
AR,

RIB SIDE

OF CABLE upP
RED EDGE

TO LEFT
SRR

FROM J1 OF DMF32

FROM J2 OF DMF32

FROM J3 OF DMF32

STEP 2 — CONNECT THE THREE DMF32 CABLES
TO THE STAGGERED WRAP
TH-BERE

Figure 3-2

Staggered Connector Installation

DMF32 DIAGNOSTICS

3.1.3.4

Local Modem - Local modem is used when a modem is manually

selected for analog (local) loopback testing. Any modem that can internally loop
back data may be selected.
3.1.3.5

Programmable Modem - When a programmable modem is used, no

manual intervention is required for local loopback. A programmable modem is

any device that, whenever the diagnostics assert User TX (pin 18), provides a
loopback path between the transmit data and the receive data.

3.1.4

Distribution Panel Switch Settings

When asynchronous or synchronous diagnostics are run with the H3248

attached, the switches on the distribution panel must be set as listed in Table

3-1.

3.1.5 Self Test
After each power-up, the DMF32 performs a self test. The first test of the
EVDLB diagnostic verifies if this self test has been completed satisfactorily. The

O RN

- self test checks the following hardware elements:
2901 ALU can perform computations correctly.

2901 A and B registers can be addressed properly.

Condition codes can be set properly.
The local store RAM is operational.

The micro PC stack functions to four levels of the subroutine call correctly.

. The UNIBUS slave trap hardware functions correctly.

. The UNIBUS master I/O addressing and data transfers function correctly.

Table 3-1

Distribution Panel Switch Settings

Asynchronous Diagnostic
Switches S1 and S2

Synchronous Diagnostic
Switch S3

Switch

State

Switch

State

1
2
3
4
5
6
7
8
9
10

OFF
ON
OFF
ON
ON
ON
ON
OFF
ON
ON

1
2
3
4
5
6
7
8
9
10

ON
ON
ON
See Table 2-7
See Table 2-7
Not used
Not used
Not used
Not used
Not used

DMF32 DIAGNOSTICS

3.2

DMF32 LEVEL 3 DIAGNOSTICS

There are three Level 3 diagnostics used to support the DMF32: EVDLB,

EVDLC, and EVDLD. These diagnostics operate under the VAX Diagnostic

Supervisor (DS). Table 3-2 lists some of the parameters of these diagnostics.

3.2.1

Level 3 Hardware Prerequisites

The following must be functional before the Level 3 diagnostics may be used.
e VAX-11 CPU
e Memory (256 KB minimum)

e UNIBUS adapter (DW730, DW750, or DW780, as applicable)
e Green LED on the DMF32 must be illuminated
3.2.2

EVDLB Diagnostic Description

The EVDLB diagnostic tests the synchronous port only; it ignores devices on

the asynchronous and parallel ports. The default section of the EVDLB diagnostic provides internal loopback testing (no external loopback connector is

required). An external connector (single-line loopback connector or the H3249

staggered loopback connector) can be used to verify the complete functionality
of the synchronous interface.
The manual section of the EVDLB diagnostic provides for external loopback
testing using the local modem or the remote modem as the rloopback device.

Using the remote modem verifies the functionality of the communications

facilities.

3.2.2.1

Loading, Attaching, and Running EVDLB - After the Diagnostic

Supervisor is loaded, the operating instructions in Example 3-1 can be used for

pr—

the EVDLB diagnostic. The underlined portions are what the user enters into the
system.

Table 3-2

Diagnostic

DMF32 Level 3 Diagnostic Parameters

EVDLB

EVDLC

EVDLD

Section

Synchronous port

Asynchronous port

Parallel port

Tested

(DMF32S)

(DMF32A)

(DMF32P)

‘Generic Device

XGAO

TXA

VAX Diagnostic

6.6 or later

LCA
6.6 or later

Supervisor

Version

Running Time

o minute

3.00 minutes

(quick flag

clear)

40 seconds

with

H3249 or
LP on port

0.5 minutes

25 seconds

(quick flag set)

with nothing on
the port

DMF32 DIAGNOSTICS

DIAGNOSTIC

SUPERVISOR.

ZZ-ENSAA-6.6-XxXX

DS> LOAD EVDLB

hh:mm:ss.ss

;

Loads synchronous port diagnostic

DW73@

HUB

DW@

;

Attaches

UBA

11/730

DW750

HUB

DW@

;

Attaches

UBA

11/75¢0

DS> ATTACH

DW780

SBI

DW@

Attaches

UBA

11/780

DS> ATTACH

DMF325

;

Attaches

DMF32

-8

DS> ATTACH

dd-mm-yyyy

The

option

linked

The

option

named

XGA@

DS> ATTACH
or

DEVICE

LINK?

DW@

DEVICE

NAME?

XGAQ

CSR?

el]

760340

bl ] -g

NONE

The CSR address is
= 760000-777776)

Vector
BR

NONE

level

UBA

(range

300-766)
5

5-6)

external

loopback
connected

H3248

connector is connected
External modem connected

TMy

MODEM

Selects
be

the

WRAP

XGAQ

(range

port

the

760340

connector

-y

DS> SEL

300

interrupt

(range

EXTERNAL WRAP?

wyy

BR?

300

VECTOR?

synchronous

H3249

synchronous

loopback

port

run

If UNIBUS Init jumper W1l has been removed, event flag 2 must be

set

before

DS)

SET

running

EVENT

the

EVDLB

diagnostic.

;

Sets

event

flag

NOTE

To
run
EVDLB,
the
S3 switches on the
distribution panel must be set (refer to
Section 3.1.4).

DS> START

Example 3-1

;

Runs

the

diagnostic

Loading, Attaching, and Running EVDLB

DMF32 DIAGNOSTICS
O

3.2.3

EVDLC Diagnostic Description

The EVDLC diagnostic tests the asynchronous port only; it ignores devices on
the synchronous and parallel ports. This diagnostic performs both DMA and
SILO mode testing with either an internal or external loopback connector con-

nected. The EVDLC diagnostic has two sections: default and manual
intervention.

The default section provides for internal loopback testing when no external
loopback connector is used. Also, when an H3248 single-line loopback connector ora programmable modem is used, the default section provides an external
loopback path for all the modem signals. Using the H3249 staggered loopback
connector provides complete functional testing of the asynchronous device.
The default parameters are as follows:
@

8 bits per character

1 stop bit

Parity disabled

ARG

Baud rate selected from attach sequence

The manual section provides for external loopback testing when a nonprogrammable modem or a remote modem is used as the loopback device. Using the
remote modem verifies the communications facilities.
S

3.2.3.1 Loading, Attaching, and Running EVDLC - After the Diagnostic
Supervisor is loaded, the operating instructions in Example 3-2 can be used for
the EVDLC diagnostic. The underlined portions are what the user enters into the

system.

3.2.4

EVDLD DIAGNOSTIC DESCRIPTION

The EVDLD diagnostic tests the DMF32 parallel port only; it ignores the devices
on the synchronous and asynchronous ports. This diagnostic tests both the
parallel interface and line printer controller functions of the DMF32. To fully test
the DMF32 line printer logic, a line printer must be attached to the line printer
port. To fully test the DMF32 parallel interface logic, an H3249 loopback connector must be attached to the J2 and J3 connectors.
Testing the parallel port with the H3249 loopback connector is preferred since
this is the only way that the parallel interface is completely tested. When neither
a line printer or H3249 staggered loopback connector is attached to the parallel
port, only the control and status register tests are performed. The diagnostic
CSR low byte is used to loop the data that would normally be transferred to the
printer. This tests the format functions without an attached printer.

3.2.4.1 Loading, Attaching, and Running EVDLD - After the Diagnostic
Supervisor is loaded, the operating instructions in Example 3-3 can be used for
the EVDLD diagnostic. The underlined portions are what the user enters into the
system.

ey,

DMF32 DIAGNOSTICS

DIAGNOSTIC

SUPERVISOR.

ZZ-ENSAA-6.6-xxx

dd-mm-yyyy

hh:mm:ss.ss

; Loads asynchronous port diagnostic

DS> LOAD EVDLC
DS> ATTACH DW730

HUB

DW@

;

Attaches

UBA

11/730

HUB DW@

;

Attaches

UBA

11/750

;

Attaches

UBA

11/780

DS> ATTACH DW750
or

DW@

DS> ATTACH DMF32A

;

diagnostic

Option is linked to the UBA

TXA

A-F)

760340

The

-y

CSR?

Attaches the asynchronous

;

DEVICE LINK? DW@
DEVICE NAME?

SBI

DS> ATTACH DW780

300

377

5-6)

(range

wmy
R

g
e
wmy

determines the line speed

remote

This

and

OWE

tests.

Baud

loopback

(range =

Baud rate that is to be used
wrap

(manual)

rates

that

can

for the

modem

test

selected

are

15@,

11¢, 135,

bit

parameter

the single-line loopback

test.

1200,

1800,

2000,

2400,

3600,

4806,

7200,

9600,

19200

4800,

INTERNAL -~ Data loopback path is
internal to the DMF32
H3248

300, 600,

s¢, 75,

INTERNAL

interrupt level

Single-line

L
b

_y WE omg WE wyy WE wyy WE wmgy g

the

loopback

is connected at

connector

WRAP TYPE?

300

(range

external

9600

760340

600-377)

BAUD RATE?

(range

All lines to be tested (octal
map of lines to be tested)
bit 0 = line @
~
bit 1 = line 1, etc.
(range =

b
1]

LINES?

Vector address
300-766)

TXA

ACTIVE

named

BR? 5

The CSR address
760000-777776)

VECTOR?

option

distribution

panel

loopback

- Staggered
connector

used

LOCAL MODEM - A modem manually
selected

TXA

MODEM

testing

modem

YES - Jumper W1l installed on DMF32
NO

- No

Select

jumper

the

device

run

NOTE

The
S1
and
s2
switches
distribution panel must be set
Section

3.1.4)

that

(local)

loopback test mode when
EIA pin 18 is asserted

-y

DS> SEL

analog

selects analog

e
¥

UNIBUS INIT JUMPER? YES

PROGRAMMABLE

for

loopback

(local)

before

running

the

(refer
EVDLC.

DS> START

;

Example 3-2

Loading, Attaching, and Running EVDLC

Starts

running

the

program

DMF32 DIAGNOSTICS
O

DIAGNOSTIC
DS> LOAD

SUPERVISOR.

ZZ-ENSAA-6.6-XXX

EVDLD

DS> ATTACH

dd-mm-yyyy

;

Loads

the

hh:mm:ss.ss

parallel

port

DW73¢

HUB

DW@

;

Attaches

UBA

11/730

DW750

HUB

DW@

;

Attaches

UBA

11/750

DW780

SBI

DW@

;

Attaches

UBA

11/780

DS>

ATTACH
or

DS> ATTACH

DEVICE

DMF32P

LINK?

NAME?

DW@

LCA

Attaches

diagnostic

;

The

option

the

UBA

The

option

;

The

CSR

CSR> 760340

;

DS> ATTACH

300

BR? 5

PORT

DEVICE?

OTHER

parallel

SO,

linked

named

address

Vector

address

(range

;

(range

OTHER

—

LCA
760340
G

300

300-776)

interrupt

level

H3249

5-6)

760060-777776)

;

port

(range

VECTOR?

the

Other

than

wp UE

ws M

wy WE

WRAP

printer

H3249

line

loopback

connector

connected

Example 3-3

Line

DS> START

connector

connected

Select

LCA

loopback

printer 1is
connected

DS> SEL

staggered

Start

the

parallel

port

run

running

the

program

Loading, Attaching, and Running EVDLD
RS

3.2.4.2

EVDLD Event Flags - The EVDLD diagnostic uses three event flags:

EV3, EV4, and EV5. The EV3 flag indicates to the diagnostic whether DMF32

jumper W1 has been removed. The EV4 and EV5 flags control the buffer type

error message printouts. Refer to Table 3-3 for the EVDLD event flags. Example
3-4 shows EVDLD Event Flag instructions.
O

3.3

DMF32 LEVEL 2R DIAGNOSTICS

There are two Level 2R diagnostics used to support the DMF32: EVDLA and
EVDAC. Both operate under the VAX Diagnostic Supervisor (DS) with VMS.
Table 3-4 lists some of the parameters for these diagnostics.

DMF32 DIAGNOSTICS

Table 3-3

EVDLD Event Flags

Event
Flag

State

EV3

EV4

EV5

Clear

UNIBUS Init will
affect the DMF32

Only first eight
errors in a buffer
are displayed

No effect

All errors in the
buffer
are
displayed

Entire
buffer
s
dumped regardless

(jumper

installed)

UNIBUS Init will

Set

not
affect
the
DMF32 (jumper
W1 removed)

of whether the data
is erroneous or not
(EV4 need to be set
EV5

when

DS> SET EVENT 4,5

: Sets event flags 4 and 5

DS> SHOW EVENTS

;
;

DS> CLEAR EVENTS 4,5

; Clears event flags 4 and 5

Example 3-4

Shows all event
currently set

flags

that

are

EVDLD Event Flag Instructions

Table 3-4 DMF32 Level 2R Diagnostic Parameters
-

Diagnostic

EVDLA

EVDAC

Section Tested

Synchronous port

Asynchronous
port

Generic Device

XGAO

VMS Release

3A or later

VAX Diagnostic

6.6 or later

Supervisor Version

TXA

set)

DMF32 DIAGNOSTICS

3.3.1

Level 2R Hardware Prerequisites

~ The following must be functional before the Level 2R diagnostics may be used.
VAX-11 CPU
Memory (128 KB minimum)

UNIBUS adapter (DW730, DW750, or DW780, as applicable)
Green LED on the DMF32 must be illuminated
3.3.2

EVDLA Diagnostic Description

The EVDLA provides integrity testing and fault detection for the synchronous

device while operating under VMS. The operating system (VMS) produces the
error reports, which identify the failing functional area of the synchronous
device, and the status reports of the synchronous device.

3.3.2.1 Loading, Attaching, and Running EVDLA - The instructions in
Example 3-5 are used to load, attach, and run EVDLA. It is assumed that VMS is
already loaded. Again, user input is underlined.
3.3.3

EVDAC Diagnostic Description

oo,

The EVDAC diagnostic tests the functionality of the asynchronous multiplexer
while operating under VMS. This diagnostic has two selectable sections: default
and link.

The default section is used for all normal testing. The link section is used for link
testing. The EVDAC diagnostic exercises a DMF32 that is linked to another
DMF32 (even in the same system) which is also running EVDAC.
3.3.3.1

Loading, Attaching, and Running EVDAC - The instructions in
Example 3-6 are used to load, attach, and run EVDAC. It is assumed that VMS

is already loaded.
R

DMF32 DIAGNOSTICS

$ RUN ENSAA

Start supervisor (11/788 = ESSAA,
11/750 = ECSAA, 11/730 = ENSAA)

¥
"

DIAGNOSTIC

SUPERVISOR.

DS> ATTACH DW788

SBI

DWg

HUB

DW@

the

Attaches

]

UBA on

09:40:14.890
SBI

the

VAX-11/780

DS> ATTACH DW750

8-FEB-1982

ZZ-ENSAA-6.6-XXX

For

VAX-11/750 testing
VAX-11/730

VECTOR?

BR?

TYPE?

NONE

.y my

named XGA#

The CSR address is 760340
760000-777776)

Vector address
300-776)

5-6)

NONE

- No

WRAP

interrupt

connector

DS>START/SECTION:CABLE
or

MODEM
DS> START/SECTION:

connected

Select

the

synchronous

port

Start running EVDLA without either
an external loopback connector or
a

WS
We

modem

backloop

MODEM - External modem

External

backloop

DS> START

external

(range =

modem

loopback connector

XGAQ

is 5

level

connector

(range =

308

(range =

External

DS> SEL

(range =

The option

WRAP

300

linked

760340

A-F)

CSR?

the UBA

option

DEVICE NAME? XGA#

The

synchronous

LINK? DW@

program

DEVICE

Attaches the
diagnostic

testing

EVDLA

the

DS> ATTACH DMF32S

Loads

EVDLA

For

DS> LOAD

HUB DW#

DS> ATTACH DW730

LTM

connected

External modem is connected

’

Example 3-5 Loading, Attaching, and Running EVDLA

36 DMF32 DIAGNOSTICS
R,

S ALLOCATE TXA(N)

S RUN ENSAA

Start
¥

SUPERVISOR.

DS> ATTACH DW780

SBI

DWO

DS> ATTACH

DW750

HUB

DWO

DW730

HUB

DWQ

supervisor

11/750 = ECSAA,

ZZ-ENSAA-6.6-xxx
gy

DIAGNOSTIC

Allocate all lines to be tested

8-FEB-1982

ESSAA

09:40:14.80

UBA on the

the

Attaches

(11/780

11/730 = ENSAA)

VAX-11/780
For VAX-11/750

testing

For

testing

SBI
—————

DMF32A

DEVICE

LINK?

DW0

DEVICE

NAME?

TXA

bt]

Attaches

ATTACH

program

EVDAC

the

Loads

diagnostic

DS>

EVDAC

DS> LOAD

VAX-11/730

The

DS> ATTACH

the

The option

is named TXA

A-F)

option

asynchronous

linked

the

UBA

(range

CSR? 760340

The

CSR address

760340

(range

760000~-777776)
R~

300

VECTOR?

Vector address
300-776)

300

level

(range

377

LINES?

5-6)

All

9600

bit

Baud

RATE?

lines

external

WS
wgy
S

@-7

(octal bit map of
tested)
bit ¢ = line 0,
0oB-377)

wgy

BAUD

interrupt

ACTIVE

wmy

P—

BR?

line

rate that

that
116,

wrap

(range

to be used

tests.

Baud

can be selected are
135, 150, 300, 609,

2000,
19200

2400,

3600,

tested

lines

etc.

4800,

rates

50,

75,

1200, 1800
7200, 9600,

TYPE?

INTERNAL

INTERNAL
WE wma

LOCAL

MODEM

Modem

TXA

YES

with

wrap

the

internal
’

wgy

PROGRAMMABLE MODEM - A modem which
diagnostics can set to internal
wrap

WME s

DS> SEL

JUMPER?

panel

Transmit

setting
Modem

the

User

signals

INIT

wrap

Jumper on DMF32 module
inhibits UNIBUS Inits

k1 *

UNIBUS

internally at

distribution

H3248

- Wrapped
the UART
Single-line

WRAP

Selects

that

Example 3-6

DS> START

Start

the

asynchronous

port

run
program

running

Loading, Attaching, and Running EVDAC
Y,

PROGRAMMING
4.1

INTRODUCTION

The DMF32 consists of four distinct devices. Each device is programmed
independent of the other three devices, since each device contains its own set
of registers. There are only two registers that are common to the DMF32: CSR
0 and CSR 1.

411

DMF32 CSR 0

The operating system uses CSR 0 at AUTOCONFIGURE time. CSR 0 contains
a 4-bit code (see Table 4-1) that indicates to the operating system which three
of the four devices are available for operation. The parallel interface (DR) and
the line printer controller (LP) cannot operate concurrently.

The DMF32 uses two dip switches to select the desired devices: switches 4
and 5 on switch pack 3 on the distribution panel. Refer to Table 2-7 for the valid
switch setting combinations. These two switches, which are read by the
DMF32, should be set before power up, since the microcode samples these
switches only once after power up.

After power up, the program can write to CSR 0 bits (15:12) to change the
device code to another valid combination. For example, to switch a diagnostic
program from DR to LP or LP to DR without human intervention, execute a
WRITE WORD (MOVW) instruction to CSR 0 bits (15:0). The WRITE WORD
overwrites the base interrupt vector which occupies the low byte of CSR 0. To
load the interrupt vector (CSR 0 high byte) without affecting the CSR 0 high
byte (device available bits), execute a BYTE output instruction (MOVB). This
MOVB instruction loads the low byte of CSR 0, regardless of whether the high
or low byte is accessed.

The floating CSR addresses for the four devices (synchronous, asynchronous,

parallel interface [DR], and line printer controller [LP]) on the DMF32 board
reside in a contiguous block of sixteen words. Eight switches on the DMF32
board determine the starting address of the block. These locations can only be
accessed by words. The sixteen words are allocated to the devices as shown
in Figure 4-1.

Also at AUTOCONFIGURE time, the operating system loads the value of the
first interrupt vector into CSR 0. There are no switches on the DMF32 for
interrupt vectors. The DMF32 determines the value of the other seven interrupt
vectors as contiguous with a greater value than the first vector in CSR 0. Table
4-2 lists the vectors.

PROGRAMMING
A

BYTE ADDRESS

]

COMBO.CSR [1:0] <15:0>

BASE

{OCTAL
0

BASE

{(HEX)

SYNC.CSR [3:0] <15:0>

ASYNC.CSR [3:0] <15:0>

BASE +

BASE

LP.CSR [1:0] <185:0>

DR.CSR [3:0] <15:0>

MKVBA-2855

Figure 4-1

CSR Device Addresses

Table 4-1

Device Selection

Device Code

Selected Device

1000

Async only

1010

Async and line printer

1101

Async, sync, and parallel interface

1110

Table 4-2

Async, sync, and line printer

DMF32 Floating Vectors
T

Vector
Number

Vector

—

Vector Value (Octal)
e

Synchronous

Base (CSR 0 bits (7:0))

interface receive
1

Synchronous
interface transmit

Base + 4

Parallel interface
vector A

Base + 10

Parallel interface

Base + 14

vector B

Asynchronous multiplexer
receive

Base + 20

Asynchronous multiplexer
transmit

Base + 24

Line printer controller

Base + 30

Not used

Base + 34

PROGRAMMING

Figure 4-2 shows the bit configurations for CSR 0; Table 4-3 defines the CSR 0
bit functions.
12

11
NOT
USED

DEVICE CODE

BITS

VECTOR O
MKWB4-2675

Figure 4-2

CSR 0
Table 4-3

Bit

Title

(15:12)

- Device code

CSR 0 Bit Functions

Function

These bits select between parallel interface

or line printer operation (defined in Table 43).

Not used

(11:8)

Interrupt

(7:0)

Vector

Reserved for future use (always written and

read as zeros).

Contains the first interrupt vector

(read/write).

* Example: To load an interrupt vector address in bits (07:00), for an address of
300 (octal), you must load 60 (octal) because the least significant bits are not
used in the interrupt vector address.

4.1.2

DMF32 CSR 1 Diagnostic Register

CSR 1 is used for diagnostic purposes. What is loaded into the high byte of
CSR 1 determines the function performed. Table 4-4 lists the different
|

functions.

Reading CSR 1 clears the low byte of CSR 1. This low byte is used in LP
maintenance mode.
Table 4-4
CSR 1 High Byte

(HEX) Contents

green LED on the DMF32 to go off, and inhibits
microcode execution. In this state, DMF32 registers cannot be accessed. To restart execution,
UNIBUS signals DC LO or INIT must be asserted.

Starts execution at location 0000. Location 0000 is

Diagnostic Function

Forces a parity error. A parity error causes the

CSR 1 High Byte Functions

where execution begins after a UNIBUS DC LO or
INIT. This feature allows program controlled initiation of the powerup self test.

CSR 1 high byte contains the microcode REV level.

To read the REV level number, 2A (hex) must be
written to CSR 1 bits (15:8), then a read of CSR 1
bits (15:8) will obtain the REV level. The number is
stored in BCD and there are two digits in the byte.

The self test has successfully completed.

PROGRAMMING

4.1.3

DMF32 Device Control Status Registers

The floating control status registers of the four devices (synchronous interface,

asynchronous multiplexer, line print controller, and parallel interface) reside in

a contiguous block of 16 words. A dip switch pack (E77) on the DMF32 determines the starting address of the block. These registers can only be accessed
by word, except for the register used to access a transmit silo of an asynchronous line, and the parallel interface output buffer when in DR11-C functional
mode. Access by word means that the instruction that operates on the register
causes a data out (DATO) rather than a data out byte (DATOB) UNIBUS cycle.

The DMF32 ignores the least significant UNIBUS address bit on registers that

are word-access only, and therefore treats a DATOB as a DATO for these
registers.

4.2

SYNCHRONOUS INTERFACE

The synchronous interface is a serial line that transfers data from main memory directly (DMA). Since the DMF32 stores the UNIBUS addresses and byte
counts, each 16-bit transfer (two character) to and from main memory requires

only one memory reference. Both the transmitter and receiver have two sets of

byte count registers and buffer address registers. After one message has been

transferred between the main memory and synchronous interface, the second
message can start immediately even if the CPU has not been notified of com-

pletion of the first message. BR level interrupts signal the completion of transfers, modem status changes, and error conditions.
R

4.2.1

Synchronous Interface Protocol Support

The synchronous interface supports both bit-oriented protocols (SDLC and
HDLC) and byte-oriented protocols (DDCMP). The synchronous interface per-

forms bit stuffing, bit removal, and control character generation and recognition. The program loads registers in the DMF32 to specify the protocol, error

control, and the number of bits per character.
Byte-oriented protocols not supported by the synchronous interface may be
implemented by running the general byte-oriented synchronous (GEN BYTE)
protocol. This protocol is not really a protocol, but implements a straight trans-

fer of data between main memory and the synchronous interface. In this way,

the software can perform protocol-specific functions.
4.2.2

Synchronous Interface Baud Rate

Using the crystal controlled baud rate generator, the synchronous line can be
programmed to transmit at one of eight different speeds up to 19,200 bps. Any
transmit or receive bit rate up to 19,200 bps can be used with external clocking.

The receiver uses an external clock input from the modem, except during maintenance testing.

4.2.3

Synchronous Interface Device Registers

The synchronous interface uses four device registers and 16 indirect registers.
The four device registers are as follows:

e Receive control status register
e Transmit control status register

PROGRAMMING

e Miscellaneous register

e Data set change flag register

4.2.3.1 Receive Control Status Register — The receive control status register

enables the following:

—-—

¢ The receiver

e The match character (GEN BYTE)

¢ The receive interrupt

e The local loop (maintenance testing)

e Strip sync
It also indicates the following:

e The selected receive buffer address register

e The receiver is active

e The received message has been transferred to the secondary receive

buffer

¢ Residual bit count does not equal zero (HDLC, SDLC)

e |f the DMF32 is either a primary or secondary station (HDLC, SDLC), or a
control station, or tributary station (DDCMP)

e A receive error

The received message has been transferred to the primary receive buffer

4.2.3.2 Transmit Control Status Register — The transmit control status register enables the following:

e NPR request (primary and secondary)

¢ Interrupt request when the data set change bit is set

¢ Interrupt request when either transmit done primary, transmit done secon-

dary, or transmit error bit is set

It also indicates the following:

e The selected transmit buffer address register and character count
registers

¢ The transition of any of the data set change bits
e The message from secondary data buffer has been transferred to the synchronous interface

e Transmit error

PROGRAMMING

* The message from primary data buffer has been transferred to the syn-

chronous interface

The transmit control status register controls the state of the serial line when a
transmit underrun occurs and selects the transmit clock source.
O

4.2.3.3

Miscellaneous Register - The miscellaneous register performs the
following:

e Selects one of the 16 indirect registers
¢ |nitiates a Master Reset

4.2.3.4

Data Set Change Flag Register — The data set change flag register

indicates which of the following receive modem signals have changed:

e Carrier detect
e Ring indicator

e Data set ready

e Clear to send
e User receive

4.3

SYNCHRONOUS OPERATION

The synchronous interface is ready for operation after the following is performed. The program loads the interrupt vectors into the first CSR of the

DMF32. Next, the powerup Master Reset is performed. After a Master Reset (or

DC LO or INIT), the transmitter and receiver are disabled and the transmitter is
held marking. The protocol parameter register (indirect register [0] bits (7:0))
and transmit/receive BPC (bits per character) registers (indirect register [0] bits

(15:8)) should now be loaded by the program; the Master Reset should also be

set. After the Master Reset bit clears, the program should load any parameter(s)
and enables the transmitter and receiver.

4.3.1

Synchronous Transmit Operation

For byte-oriented protocols, the program should load both the sync register

(indirect register [3] bits (15:8)) and the number-of-syncs register (indirect regis-

ter [3] bits (7:0)). The sync register contains the character used for the transmit
and receive synchronization. The number-of-syncs register contains the number of sync characters to be transmitted prior to the message. For bit-oriented
protocols, the standard ‘“‘flag” character is used for transmit and receive
synchronization.

RSN

4.3.1.1

Pretransmission Considerations — Before data is transmitted from a
buffer, the following is performed. The program sets the primary/secondary bit

(transmit CSR bit (2)) to indicate whether the primary buffer address register
(indirect register [10]) or secondary buffer address register (indirect register
[12]), and the character count register (indirect register [11] or [13]) are to be

used. Next, the program loads the appropriate buffer address and character
count registers. If there is more than one message to be transmitted, both the
primary and secondary registers are loaded. A buffer transfer can start and finish on any byte boundary. A pair of word aligned bytes are direct memory
accessed two bytes at a time via the UNIBUS.
«

PROGRAMMING

4.3.1.2 Initiating Transmission — Assume the primary character count and
buffer address registers are active. After loading these registers, the transmit

enable bit should be set to start the DMA transfer of characters from main mem-

ory to the synchronous interface. Setting the transmit enable bit clears all transmit error bits. Loading the primary or secondary character count register clears
the transmit done primary bit or the transmit done secondary bit respectively.
4.3.1.3 Synchronous Interface Data Transmission — The synchronous interface acts on the bytes to be transmitted according to the specific protocol used.
After a successful DMA transfer and message transmission, the transmit done
primary bit is set. If the transmit interrupt enable bit is active, setting the transmit done primary bit causes an interrupt to the transmit vector.

If the message is aborted due to an error condition, the transmit error bit is set,

while the transmit enable bit is cleared. The transmit primary/secondary bit
always changes to one state. The transmit primary/secondary bit is changed to

one state to indicate that the secondary character count and buffer address registers are now active.

If transmit done secondary bit is set, then the synchronous interface becomes
idle (transmit enable bit does not clear) and waits for transmit done secondary
bit to be cleared by the software loading the secondary character count register.
If the transmit done secondary bit is clear, the secondary buffer processing
begins.

While the secondary buffer data is being transferred to the synchronous interface to be transmitted, the program should service the transmit done primary
interrupt. If there is another message to be transmitted, the primary buffer
address should be loaded with the address of the message buffer; then the primary character count register should be loaded with the message size in bytes. Loading the primary character count register clears the transmit done primary

bit. This double buffering scheme results in high message throughput without
any stringent requirements on interrupt latency. The CPU has a full message

“transmission time to service an interrupt.

4.3.1.4 Synchronous Interface Transmission Errors - Transmit error conditions abort the transmitted message. Aborting the transmitted message sets
the done bit pointed to by the transmit primary/secondary bit. The transmit
|
error bit is set and the transmit enable bit is cleared.
The transmit error bits (2:0) (indirect register [2]) indicate the cause of the
transmitted error. The following are transmit errors:
e Transmit underrun error. The synchronous interface could not get and

process characters fast enough to sustain the baud rate.

PROGRAMMING

e DMA error. The synchronous interface UNIBUS controller did not receive
a SSYN at least 32 us after issuing a MSYN.
SR

e Transmit message length error. The character count indicates a buffer

length too small for the message of the particular protocol. This error may

be detected before transmission begins (for example, SDLC frame under
four characters).

4.3.2

Synchronous Receiver Operation

After a Master Reset or INIT, the synchronous receiver is disabled. To receive

messages, the program sets the receive primary/secondary bit (receive CSR
bit (2)) to indicate whether the primary or secondary buffer address register
(indirect register [6] or [8]), primary or secondary count register (indirect regis-

ter [7] or [9]) are to be used. The program loads the appropriate receive buffer
address and receive character count register (both primary and secondary
registers can be loaded). Loading the primary or secondary character count
A

registers clears the primary or secondary done bit, respectively. A receive

buffer can start and finish on any byte boundary. A pair of word-aligned bytes

are transferred two at a time.
4.3.2.1

Synchronous Receiver Synchronization - Assume the primary char-

acter count and buffer address registers are active. After loading these registers, the receiver enable bit should be set to search for character synchroniza-

tion. For byte-oriented protocols, receiving two successive sync characters (the

—

character programmed in sync register bits (7:0)) causes synchronization. Bitoriented protocols are synchronized when a ‘‘flag’’ character signals the beginning of a frame. Setting receiver enable bits clears all the receive error bits.
A

4.3.2.2 Synchronous Interface Data Reception - The way the synchronous

interface acts upon the received bytes depends upon the specific protocol

used. After a successful DMA transfer and message reception, the receive

done bit is set. If the receive interrupt enable bit is active, setting the receive
done primary bit causes an interrupt to the receive vector. If the message is
aborted due to an error condition, the receive error bit is set, and the receive
enable bit is cleared.
After the receive done primary bit or the error bit is set, the receive prima-

ry/secondary bit changes to a one to indicate that the secondary character

count and buffer address registers are now active. If the receive done secondary bit is set, the synchronous interface becomes idle (receive enable bit
o

remains set) and no more messages are received. When the receive done

secondary bit and receive error bit are both clear, the received message is

loaded into the secondary buffer.
A

While the receive data is being transferred to the synchronous interface and
then to the secondary buffer in main memory, the program should service the

receive done primary interrupt. As part of this service, the primary buffer

address register should be loaded with the buffer address of the message, and
the primary character count register should be loaded (clearing the receive

done primary bit) with the maximum possible message size in bytes.

PROGRAMMING

4.3.2.3

Synchronous Interface Receiver Errors - Receive error conditions

abort received messages. An aborted receive message sets the receive error

bit. Receive error bits (7:0) indicate the cause of the receive error. The possible
receive error conditions are as follows:
e

Receive overrun error (The synchronous interface could not process and

transfer the received characters to main memory fast enough. This would
result if the synchronous interface was operating at too high a baud rate.)
e DMA error (The synchronous interface UNIBUS controller did not receive

SSYN at least 32 us after issuing a MSYN.)
e Receive block check error

e Receive VRC error
e Receive abort character
e Receive overflow (The received message is too big for the buffer space

allocated to it.)

An error condition that aborts a receive message changes the state of the

receive primary/secondary bit and clears the receive enable bit.

4.4

SYNCHRONOUS INTERFACE DEVICE REGISTERS

The synchronous interface uses four device registers and 16 indirect registers.
The four device registers are as follows:
Receive control status register
Transmit control status register
Miscellaneous register

Data set change flag register
4.4.1

Receive Control Status Register

The receive control status register has an address of base +4. Read/modify/

write UNIBUS cycles are allowed. Access is by word only.

Figure 4-3 shows the bit format of the receive control status register. Table 4-5
describes the functions of the receive control status register.

PROGRAMMING

OB,

UNUSED
BITS

RECEIVER

|PRIMARY/ | RECEIVE

DONE

SECONDARY| RESIDUAL

[STATION

PRIMARY
i

SECONDARY

INTERNAL | RECEIVER |UNUSED BIT|RECEIVE
LOOP

ACTIVE

RECEIVE

RESIDUAL

ENABLE

PRIMARY

RECEIVER

DONE

RECEIVER

| ENABLE

UNUSED BIT

INTERRUPT

RECEIVE

ERROR

PRIMARY/

SECONDARY

RECEIVE

MATCH

SECONDARY

Figure 4-3

Synchronous Receive CSR
I

Table 4-5

Synchronous Receive Control Status Register Functions

Bits

Title

Function

(0)

Receiver Enable

When set, this bit enables processing of the
receiver serial input data. When the receiver
enable bit becomes asserted, the receiver is
enabled to search for synchronization provided that the done bit pointed to by the
transmit primary/secondary bit is clear.
When the receiver enable bit is cleared, the

receiver logic is disabled.

[

The transition of the receiver enable bit from

a zero to a one state clears the receive error
bits. Only the program can change the state
of the receiver enable bit from a zero to a

one.

f
A

The receiver enable bit is read/write and is
cleared by:

Unused Bit

(2)

Receive
Primary/

Master Reset or INIT.

setting either receiver abort, receiver
DMA error, receiver overrun, receiver
VRC, receiver overflow, or receiver
BCC error.

Secondary

This bit indicates which receive buffer
address register is being used (primary
receive buffer address register bits (17:0) or
secondary receive buffer address register
bits (17:0)). It also indicates which receive
character count register (primary receive
character count register bits (13:0) or secondary receive character count register bits
{(13:0)) will be used.

PROGRAMMING

Table 4-5

Synchronous Receive Control Status
Register Functions (Cont)

Bits

Title

Function
A zero state indicates that the primary‘ registers are active; a one state indicates that the

|
s

secondary registers are active. When the

NPR transfer of received data is terminated

.
-

primary/secondary bit changes state to indi-

cate the new active receive buffer. However,
if the new buffer’s receiver done bit is not

clear, the receiver becomes idle until the

done bit is cleared. If the new buffer’'s done
bit is not clear, it means the CPU has not yet
processed the previous message in this new
buffer. The done bit is cleared by software

loading the character count register.

This bit is read/write and is cleared by a

{3)

(successfully or unsuccessfully), the receive

Master Reset or INIT.

Match

Receive

This bit is used only when running the GEN
BYTE protocol. When this bit is set, the char-

Character

acter stored in the match character register

bits (7:0) is used as the match character for

—

generating an interrupt. All received charac-

ters in the message are compared with the

characters stored in the match character

is found, a

receive

interrupt is

ters continue to be received and direct mem-

—

ory

|
i

a match

posted informing the driver that the special
character has arrived. Finding a match only
causes an interrupt. After the match, characaccessed.

There

may

multiple

matches and corresponding interrupts in a
message.

This bit is read/write, and is cleared by a
Master Reset or INIT.

(4)

(5)

Unused Bit

Receiver

Interrupt
Enable

This bit is always read as zero.

When set, bit (5) enables interrupt requests

to the receive vector if the receive done pri-

mary bit (receive CSR bit {15)), receive done
secondary bit (receive CSR bit (7), or receive
error bit (receive CSR bit (14)) is set.

This bit is read/write and is cleared by a
Master Reset or INIT.

(6)

—

Receiver

Active

When set, this bit indicates that the synchro-

nous interface is processing a message. The -

synchronous interface clears this bit upon
completion of the message transfer.
This bit is read-only and is cleared by a

Master Reset, an INIT, or the negation of the

receive enable bit (receive CSR bit (0)).

PROGRAMMING

Table 4-5

Bits

(7)

Synchronous Receive Control Status
Register Functions (Cont)

Title

Function

Receiver Done

This bit is set after the synchronous interface has received a message. Since the
DMF32 has some on-board buffering, the
receiver done secondary bit may be set
while the DMF32 still contains characters to
be direct memory accessed. However, if the
receiver interrupt enable bit is set, an interrupt to the receive vector is posted only after
all the characters have been direct memory
accessed to main memory.

Secondary

This bit is read-only and is cleared by loading the secondary receive character count
register bits (13:0). A Master Reset or INIT
sets this bit.

(8)

Internal Loop

Bit (8) generates a local loop for use in maintenance testing (refer to Table 4-6).

{(10:9)

Unused Bits

These two bits are always read as zeroes.

(11)

Receive
Residual

This bit is used for bit-oriented protocols
only. The receive residual secondary bit is
set whenever the residual bit count (secon-

Secondary

~ dary bits (2:0)) does not equal zero. After the
receiver done secondary bit is set, the

receiver residual secondary bit should be
inspected. If the receiver residual secondary

bit is clear, then all of the bits in the last
character are part of the message. However,
if the receiver residual secondary bit is set,
then only some of the bits in the last character are part of the message. The residual bit
count bits (2:0) need to be inspected to
determine how many bits are part of the
message.

Receive residual secondary bit is read only,
and is cleared by either a Master Reset,
INIT, or by writing to the secondary receive
character count register.

(12)

Receive
Residual
Primary

This bit is used for bit-oriented protocol only.
The receive residual primary bit is set when-

ever the residual bit count (bits (2:0)) does
not equal zero. After the done primary bit is
set, the receive residual primary bit should
be inspected. If the receive residual primary
bit is clear, then all of the bits in the last
character are part of the message. However,
if receive residual primary bit is set, only
some of the bits in the iast character are part

of the message. The residual bit (bits (2:0))
needs to be inspected to determine how
many bits are part of the message.

The receive residual primary bit is read only
and is cleared by either a Master Reset,
INIT, or by writing to the primary receive
character count register.

PROGRAMMING

Table 4-5
—

Synchronous Receive Control Status
Register Functions (Cont)

Bits
(13)

Title

Function

Primary/

For SDLC and HDLC protocol: When bit (13)

Secondary

is clear, the synchronous interface acts as

Station

primary station. If this bit is set, the synchro-

nous interface acts as a secondary station.

For DDCMP protocol: When bit (13) is clear,

the synchronous interface acts as a control

station. If this bit is set, the synchronous

interface acts as a tributary station.

This bit is read/write and is cleared by a

Master Reset or INIT.

“

(14)

Receive Error

Bit (14) is the inclusive OR of all the error
bits in the receiver error register. Setting the

receive error bit clears the receive enable

bit, and also causes an interrupt to the

receive vector if the receive interrupt enable

bit is set.

This

bit

read-only

and

cleared

Master Reset, an INIT, or by reading receiv-

)

(15)

Receiver Done

error

(indirect

[1]

bits

This bit is set after the synchronous inter-

Primary

face has received a message. Since the

DMF32

has

some

on-board

buffering,

the

receiver done primary bit may be set while

the DMF32 still contains characters to be
direct memory accessed. However, if the

receiver interrupt enable bit is set, an interrupt to the receive vector is posted only after

all the characters have been direct memory
accessed to main memory.
This bit is read-only and is cleared by load-

.
—

ing the primary receive character count reg-

ister (primary receive character count bits
|

(13:0)). A Master Reset or INIT sets this bit.

PROGRAMMING

Table 4-6

Internal Loop.
S,

Definition

State

Bit (8)

No internal loop. The transmitter serial output is connected to EIA RS-232-C circuit BA,
Transmitted Data. The receiver serial input is
connected to EIA RA-232-C circuit BB,

Received Data.

Use internal loop. The transmitter serial output is connected to the receiver serial input.
EIA RS-232-C circuit BA, Transmitted Data
is held marking, while EIA RA-232-C circuit
BB, Received Data, is ignored. The receiver
uses the selected transmit clock.

This bit is read/write and is cleared by a
Master Reset or INIT.

4.4.2

Transmit Control Status Register

The transmit control status register has an address of base +6. Read/modify/
write UNIBUS cycles are allowed. Access is by word only.

Figure 4-4 shows the bit format of the transmit control status register. Table

4-7 describes the functions of the transmit control status register.

UNUSED BITS

TRANSMIT
ERROR

TRANSMIT
DONE
PRIMARY

TRANSMIT | DATASET |DATASET

|TRANSMIT | TRANSMIT

SOURCE

SECONDARY

CLOCK

INVERT
RX
CLOCK

CHANGE

|INTERRUPT |PRIMARY/
ENABLE

TRANSMIT
TRANSMIT
DONE
INTERRUPT
SECONDARY ENABLE

IDLE

| ENABLE

UNUSED BIT

TK-8676
TRy,

Figure 4-4

Synchronous Transmit CSR
R

PROGRAMMING

Table 4-7

Synchronous Transmit Control

Status Register Functions

s
b

Bits

Title

Function

(0)

Transmit
Enable

the done bit pointed to by the transmit prima-

When set, this bit enables character transmission if

ry/secondary is clear. The primary or secondary

done bit is automatically cleared when the

software loads the primary or secondary character

count register, respectively.

The transition of transmit NPR enable bit from zero

the middle of message transmission, the following

to one clears the transmit error bits. For any protocol, if the software clears the transmit enable bit in

happens:

‘

The transmit error bit sets

The active done bit sets

Aninterrupt is generated (if the transmit inter-

rupt enable bit is set)

None of the bits in the transmit error register

bits (7:0) are set

The transmit NPR enable bit is read/write and is
|
cleared by the following:
e
e

o
-

p—

on
|

Performing a Master Reset or INIT.
Setting transmitter DMA error bit, transmit

underrun bit, or transmit character length bit.

(1)

Unused Bit

This bit is always read as a zero.

(2)

Transmit

This bit indicates which of the transmit buffer

Primary/

Secondary

address registers (indirect register [10] or indirect
register [12]) and transmit character count regis-

ters (indirect register [11] or indirect register [13])
are being used or are to be used. A zero bit indicates that the primary registers are active; a one

bit indicates that the secondary registers are
active. When the NPR transfer of transmitted data
is terminated (successfully or unsuccessfully), then

the transmit primary/secondary bit changes state,
which indicates the new active transmit buffer. Bit

(2) is read/write and is cleared (indicating primary
registers active) by a Master Reset or INIT.

PROGRAMMING

Table 4-7

Bits

Title

(3)

Idie

Synchronous Transmit Control Status
Register Functions (Cont)

—

Function

Bit (3) controls the state of the serial line between

—

messages. For byte-oriented protocols, the serial

line sends sync characters, or marks, depending

on whether the idle bit equals 0 or 1, respectively.
For bit-oriented protocols, the serial line marks or

transmits flag characters, depending on whether
the idle bit equals 0 or 1, respectively.

—

If the transmit enable bit (synchronous CSR bit (0))
is cleared by software immediately after a message has been successfully transmitted, the line
may mark until the transmit bit is set again, independent of the idle bit.

—

This bit is read/write and is cleared by a Master
Reset or INIT.

(4)

Data Set
Interrupt
Enable

—
|

”W“"f

When set, this bit enables interrupt requests to be
made to the transmit vector if the data set change
bit (synchronous transmit CSR bit (6)) is set.

—

The data set interrupt enable bit is read/write and
is cleared by a Master Reset or INIT.

(5)

Transmit
Interrupt

Enable

When set, this bit enables the interrupt requests to

the transmit vector if either the transmit done pri-

—

mary bit (transmit CSR bit (15)), transmit done secondary bit (transmit CSR bit (7)) or transmit error
bit (transmit CSR bit (14)) becomes set.

Bit (5) is read/write and is cleared by a Master

{6)

Data Set
Change

Reset or INIT.

Bit (6) is set by the ON-to-OFF or OFF-to-ON transition of any of the following bits:

—

Ring indicator

Carrier detect

Data set ready

e
)

(Clear to send
User receive

—
|

If the data set interrupt enable bit (transmit CSR bit

(4)) is set, setting data set change bit (transmit
CSR bit (6)) causes an interrupt request to the

transmit vector.

The program may read the data set change flag
register to determine which modem lines have
changed.

Bit (6) is read-only; it is cleared by reading the

—

modem receive register (indirect register [4]) and

by a Master Reset or an INIT.

—

PROGRAMMING

Table 4-7

Synchronous Transmit Control Status
Register Functions (Cont)

Bits

Title

Function

()

Transmit
Done

This bit is set after a message has been trans-

Secondary

ferred from the secondary data buffer in main
memory to the synchronous interface. Setting this
bit causes an interrupt to the transmit vector if the
transmit interrupt enable bit (transmit CSR bit (5))
is set.

Bit (7) is read/write and is cleared by writing to the
secondary transmit character count register (indirect register [13] bits (13:0)).
This bit is set by either Master Reset or INIT.

(8)

Transmit

(9)

invert

Clock Source

Receive

Clock

Bit (8) selects the clock source for the transmitter.
Refer to Table 4-8 for definitions.
If this bit is set, the receiver clock signal (when not
in internal loop mode) is inverted. This function is
used for testing.

This bit is read/write and is cleared by a Master
Reset or INIT.
(13:10)

Unused Bits

These bits are always read as zeroes.

(14)

Transmit
Error

This bit is the “inclusive OR” of all error bits in the

transmit error register (indirect register [2] bits
(7:0)). As the transmit error bit (transmit CSR bit
(14)) is set, an interrupt to the transmit vector is
requested, if transmit interrupt enable bit (transmit
CSR bit (5)) is set. Transmit error bit (transmit CSR
bit (14)) is the logical ““inclusive OR"’ of the following signals:
®

Transmit DMA error

Transmit underrun error

Transmit message length

The transmit error bit is read-only; it is cleared by
reading the transmit error register (indirect register

[2] bit (7:0)), by a Master Reset, or by an INIT.

(15)

Transmit

Done
Primary

Bit (15) is set after a message is transferred from
the primary data buffer in main memory to the synchronous interface. Setting this bit causes an interrupt to the transmit vector if the transmit interrupt
enable bit (transmit CSR bit (5)) is set.
This bit is read only and is cleared by writing to the
primary transmitter character count register (indirect register [11] bits (13:0)).

This bit is set by either a Master Reset or INIT.

PROGRAMMING
NS,

Table 4-8

Bits

Transmit Clock Source Definitions

Bit (8) State

Definition

Uses the clock from the modem. This is an EIA
RS-232-C circuit DB, Transmission Signal Ele-

ment Timing (DCE Source). EIA RS-232C circuit DA, Transmit Signal Element Timing (DTE

Source) is held marking.
1

Uses the internal transmit baud rate generator,
with the baud rate specified in transmit baud
rate generator register (indirect register [2] bits

AR,

(11:8)). The output of the baud rate generator
is connected to EIA RS-232C circuit DA, Transmit Signal Element Timing (DTE Source).

This read/write bit is cleared by a Master Reset
or INIT.

4.4.3

Miscellaneous Register

The miscellaneous register performs the following:
e Selects one of the 16 indirect registers
e

Initiates Master Reset

The miscellaneous register has an address of base +8. Read/modify/write

UNIBUS cycles are allowed. Access is by word only.
Figure 4-5 shows the bit format of the miscellaneous register. Table 4-9
describes the functions of the miscellaneous register.
B

The miscellaneous register (Figure 4-5) and the data set change flag register

(Figure 4-6) are the lower and upper bytes of the same address (base +8).

i R

oSS,

)

PROGRAMMING

UNUSED BITS

INDIRECT REGISTER

ADDRESS

MASTER
RESET
TK-BE?T

Figure 4-5

Miscellaneous Register

Table 4-9

Bits

(3:0)

Miscellaneous Register Functions

Title

Function

Indirect

These read/write bits point to one of 16 indirect registers. These registers are accessible by word only,
and are accessed through address base + A. A
write to an indirect register causes indirect register

address field (miscellaneous register bits (3:0)) to
increment by one. Successive indirect registers may
be loaded by successive UNIBUS writes or read/
modify/write cycles.

The indirect register is cached when the indirect
register address is written to or changed. Therefore,
the indirect register address should always be written to prior to a read from the indirect register. Not
writing to the indirect register address causes multiple reads of the same clock in.the indirect register.
Writing to the indirect register causes the indirect
register address to increment. The data pointed to

by the incremented indirect register address is automatically cached in the indirect register. Table 4-11
lists the indirect registers.

Bits (3:0) are not necessarily affected by a Master
|
Reset or INIT.

(6:4)

Unused Bits

(7)

Master Reset

When the program sets this bit, a Master Reset is
initiated. This bit remains set while the reset is in
progress and clears automatically after the reset
has completed. The program should not access
synchronous device registers except for the miscellaneous register, while the reset is in progress. The
program can write a one to the Master Reset bit
while the reset is in progress, but the DMF32
ignores it because the reset is already in progress.
A Master Reset initializes various CSR bits as
specified in the bit descriptions. The transmitter is
held marking, the receiver is disabled, and the interface is set up to emulate the protocol specified in
E)r%t;mwl parameter register (indirect register [0] bits
7:0)).

Character count and buffer address registers are
not affected by a Master Reset.

PROGRAMMING

4.4.4

Data Set Change Flag Register

Figure 4-6 shows the data set change flag register bit format.

This register indicates which receive modem signals the DMF32 detects as having made a transition. This register can be used to identify a modem line that
PO

has experienced a rapid sequence of two transitions. For example, if the carrier
is lost for a short period, the carrier detect will go off and then go on again.
However, by the time the program reads the respective modem receiver regis-

ter, carrier detect may have returned to its original state. Without further infor-

mation, the program could not identify which modem receive signal experienced

this momentary transition. The data set change flag register provides this addi-

tional information by flagging the modem receive signal that changed.
RO

The data set change flag register is read-only and is automatically cleared by a

program read of the modem receive register (indirect register [4] bits (7:0)). It is
also cleared by a Master Reset or an INIT. Table 4-10 lists the receive modem
signals.

UNUSED
BITS

RING
CLEARTO
INDICATOR | SEND FLAG |

USER
RECEIVE

FLAG

DATASET
READY FLAG

CARRIER
DETECT
FLAG

UNUSED
BIT
S

TK-BE78

Figure 4-6

Data Set Change Flag Register

Table 4-10

Receive Modem Signals

Data Set Change
Flag Register Bit

Modem Signal

15
14
13
12
11
10

Data set ready flag
Ring indicator flag
Carrier detect flag
Clear to send flag
Unused bit
User receive flag

9:8

Unused bits

AN,

PROGRAMMING

4.5

SYNCHRONOUS INDIRECT REGISTERS

Bits (3:0) of the miscellaneous register addresses one of the 16 indirect registers. A write to one of these indirect registers increases the address of the

indirect registers by one. Table 4-11 lists the indirect registers.
An indirect register is cached whenever the indirect register address register is

written to or changed. These indirect registers have an address of base +A.
Therefore, the indirect register address register should always be written to,

before doing a read from an indirect register. If the indirect register address
register is not written to before the read, then multiple reads of the same data
will result. Writing to an indirect register increments the indirect register

address. This automatically caches the data pointed to by the incremented
indirect register address.
Table 4-11

Synchronous Indirect Registers

Indirect
Register

Bits

Title

(7:0)

Protocol parameter register

(15:8)

Transmit BPC/receive BPC

(7:0)

Receive error

(15:8)

Residual bit counts

(7:0)

Transmit error

(11:8)

Transmit baud rate generator

(4:0)

Number of syncs

(15:8)

Sync register

(7:0)

Modem receive

(15:8)

Modem transmit

(15:0)

Secondary station address

(15:0)

Primary receive buffer address

(13:0)

Primary receive character count

(15:0)

Secondary receive buffer address

(13:0)

Secondary receive character count

(15:0)

Primary transmit buffer address

(13:0)

Primary transmit character count

(15:0)

Secondary transmit buffer address

(13:0)

Secondary transmit character count

(7:0)

Match character

(15:8)

Unused bits

(15:0)

Unused bits

PROGRAMMING

Only the following indirect registers are cleared by both a Master Reset and an
INIT.

e Indirect register [0] bits (7:0) (receive error register)

e Indirect register [2] bits (15:0) (transmit error register and transmit BRG
register)

Only indirect register [4] bits (15:0) are cleared by an INIT but are not affected
by Master Reset. All other indirect registers are not affected by a Master Reset
and are of unpredictable value after an INIT. It is the responsibility of the

program to initialize these registers properly.

All of the indirect registers are read/write except for indirect register [4] bits
(7:0) (receive modem register). The receive modem register is read-only. Read/
modify/write UNIBUS cycles may be performed to all of the indirect registers.
4.5.1

Indirect Register [0]

The indirect register [0] consists of two registers: protocol parameter register

and transmit BPC/receive BPC register. The protocol parameter register (indirect register [0] bits (7:0)) determines the protocol and the error control. The
transmit BPC/receive BPC register determines the bits-per-character for the

synchronous transmit and the receive operation.
A,

Figure 4-7 shows the bit format of indirect register [0]. Table 4-12 describes
the
functions for indirect register [0].

PROTOCOL PARAMETER

TRANSMIT BPC/RECEIVE

‘

07
:

|
|

UNUSED
TRANSMIT BITS
PER CHARACTER | BITS

Figure 4-7

INDIRECT

BPC REGISTERS

UNUSED

|ImpiT

03
PROTOCOL

sTrip

SYNG

p—

PROTOCOL

ERROR CONTROL | PARAMETER
REGISTER
O

|RECEIVE BITS PER | TRANSMIT BPC/RECEIVE
CHARACTER
BPC REGISTERS

Synchronous Indirect Register [0]

PROGRAMMING

Table 4-12

Indirect Register [0] Functions

Bits

Title

Function

(2:0)

Error Control

Bits (2:0) determine the error control (shown in
Table 4-13). Table 4-14 lists valid error control, bits
per character, and protocol combinations.

(5:3)

Protocol

(6)

Strip Sync

(7)

Unused Bit

(10:8)

Receive Bits

Bits (10:8) determine the number of bits per charac-

Per Character

ter for the synchronous receive operation (shown in
Table 4-16).

Bits (5:3) determine the protocol to be performed

(shown in Table 4-15).

STRIP SYNC is used only for the GEN BYTE protocol. If this bit is set, then any characters contiguous
to the sync characters that cause synchronization
are automatically stripped off from the serial input
data. Other protocols automatically strip sync.

(12:11)

Used Bits

(15:13)

Transmit Bits
Per Character

Bits (15:13) determine the number of bits per character for the synchronous transmit operation
(shown in Table 4-17).

Table 4-13

Error Control Codes

Protocol Parameter Register

Bits (2:0)

Error Control

000

CRC-CCITT preset to 1s

001

CRC-CCITT preset to Os

010

LRC/VRC odd

011

CRC-16

100

LRC odd

101

LRC even

110

LRC/VRC even

111

No error control

PROGRAMMING

Table 4-14

Valid Error Control, Bits Per Character,
and Protocol Combinations
Bits/

- Protocol

Character

Error Control

SDLC

CRC-CCITT presetto 1s

SDLC

CRC-CCITT presetto 1s

SDLC

CRC-CCITT presetto 1s

SDLC

CRC-CCITT presetto 1s

HDLC

CRC-CCITT presetto 1s

HDLC

CRC-CCITT presetto 1s

HDLC

CRC-CCITT presetto 1s

HDLC

CRC-CCITT presetto 1s

DDCMP

CRC-16

GEN BYTE

CRC-16

GEN BYTE

No error control

GEN BYTE

VRC even

GEN BYTE

VRC odd

GEN BYTE

VRC/LRC even

GEN BYTE

VRC/LRC odd

GEN BYTE

‘No error control

GEN BYTE

VRC even

GEN BYTE

VRC odd

GEN BYTE

VRC/LRC even

GEN BYTE

VRC/LRC odd

GEN BYTE

No error control

GEN BYTE

VRC even

GEN BYTE

VRC odd

GEN BYTE

VRC/LRC even

GEN BYTE

VRC/LRC odd

GEN BYTE

No error control

SDLC

No error control

SDLC

No error control

PROGRAMMING

Table 4-14
-

Valid Error Control, Bits Per Character,

and Protocol Combinations (Cont)

Bits/

Protocol

Character

Error Control

SDLC

No error control

SDLC

No error control

HDLC

No error control

HDLC

No error control

HDLC

No error control

HDLC

No error control

Table 4-15

Protocol Selection

Protocol Parameter Register

Protocol

Bits (5:3)

000

DDCMP

001

SDLC

010

HDLC

011

Spare

100

Spare

101

Spare

110

Spare

Table 4-16

Receive Bits Per Character Selection

Receive Bits

Bits (10:8)

Per Character

000

100

110

111

101

011

010

001

]

PO,

PROGRAMMING

ARG,

Table 4-17

Transmit Bits Per Character
Transmit Bits

Bits (15:13)

Per Character

000

8
o,

001

010

011

100

101

110

111

4.5.2

Indirect Register [1]

Indirect register [1] consists of two registers: receive error register and residual
bit count register. The receive error register contains the errors for the synchronous receive operation. The residual bit count register specifies how many bits
of the last character transferred to main memory are part of the message for
bit-oriented protocoils.

Figure 4-8 shows the bit format for indirect register [1]. Table 4-18 describes
the functions for indirect register [1].

RESIDUAL BIT

RECEIVE ERROR

COUNT REGISTER

INDIRECT

l
|

|
00 |

}
RECEIVE

ERROR

l
REGISTER

| UNUSED|
BIT

RECEIVE
ABORT

RECEIVE
NON-

EXISTENT

,
RECEIVE

OVERFLOW

’

| 15

10
RESIDUAL

RESIDUAL BIT

COUNT PRIMARY

UNUSED BIT

BIT COUNT

SECONDARY

MEMORY

|UNUSED BIT

RECEIVE

BUFFER

DMA

ERROR

RECEIVE

OVERRUN

ERROR

RECEIVE VERTICAL

REDUNDANCY

08 |

CHECK ERROR

RESIDUAL BIT COUNT
SO,

UNUSED BIT
TK-8880

Figure 4-8

Synchronous Indirect Register [1]

PROGRAMMING

Table 4-18
Bits

Title

(0)

Unused Bit

(1)

Receive
Overrun
Error

Indirect Register [1] Functions

Function

This bit is set if a receive overrun condition is detected.
This would occur if the synchronous interface could
not process and direct memory access the received
characters fast enough (because the synchronous
interface was operating at too high a baud rate).

The receive overrun bit is cleared by a Master Reset,
INIT or by reading receiver error register bits (7:0).

(2)

Receive
DMA
Error

This bit is set if the DMF32 UNIBUS controller did not
receive a SSYN at least 32 us after issuing a MSYN.

Setting this bit clears the receiver enable bit.
This bit is cleared by a Master Reset or INIT, or by
reading receiver error register bits (7:0).
(3)

Receive Block
Check Character
Error

Bit (3) is asserted if the received message generates a
block check error.

This bit is cleared by a Master Reset, INIT, or by reading the receiver error register.

(4)

Receive
Vertical

Redundancy
Check Error

Bit (4) is used for byte-oriented protocols only. This bit
is asserted when the most recent character received

has incorrect character parity.

This bit is cleared by a Master Reset, INIT, or by reading the receiver error register.

Receive Abort

Bit (5) is used only for bit-oriented protocols. The
receive abort bit is set if an abort sequence (i.e., seven
consecutive one bits) is received while receiver active
bit (receives CSR bit (6)) is set.
This bit is cleared by a Master Reset, INIT, or by reading receiver error register.

(6)

Receive Buffer
Overflow

This bit is set when the receive character count regis-

ter counts to zero and the synchronous interface

knows that there are still more bytes of the message to

be received. For the DDCMP, SDLC, and HDLC protocols, the synchronous interface knows when the message is finished. For the GEN BYTE protocol, the
synchronous interface does not know when the message is finished, except by examining the character
count register. The GEN BYTE protocol is a byte-oriented synchronous transfer, in which the synchronous

interface does not know what the specific protocol is.
The receiver overflow bit is never set in the GEN BYTE
mode.

This bit is cleared by either a Master Reset, INIT, or by
reading the receiver error register bits (7:0).

PROGRAMMING
OIS,

Table 4-18

Bits

Title

(7)

Unused Bit

(10:8)

Residual Bit
Count Secondary

Indirect Register [1] Functions (Cont)

Function

These bits are used for bit-oriented protocols only. Bitoriented messages can be any length. The residual bit
count secondary bit field specifies how many bits of
the last character transferred to main memory are part
of the message. These bits should only be examined
after the receiver done secondary bit is set. The receiver residual secondary bit (receiver CSR bit {(11)) is set
when the residual bit count secondary bit field does not
equal zero; thus implying that the residual bit count
secondary bit field should be examined. The residual
bits are right-justified within the last byte.

(11)

Unused Bit

(14:12) Residual Bit
Count Primary

This bit should be ignored by the program.
These bits are used for bit-oriented protocois only. Bit-

oriented messages can be any length. The residual bit
count primary bit field specifies how many bits of the
last character transferred to main memory are part of
the message. These bits should only be examined
after the receiver done primary bit is set. The receiver
residual primary bit (receiver CSR bit (12)) is set when
the residual bit count primary bit field does not equal
zero; thus implying that the residual bit count primary
bit field should be examined. The residual bits are
right-justified within the last byte.

(15)

Unused Bit

AR,

This bit should be ignored by the program.

PROGRAMMING

4.5.3

Indirect Register [2]

Indirect register [2] consists of two registers: transmit error register and transmit baud rate generator register. The transmit error register contains the trans-

mit underrun error, transmit DMA memory error, and the transmit message
length error. The transmit baud rate generator contains the code that deter-

mines the synchronous transmit baud rate when using the on board baud rate
generator.

Figure 4-9 shows the bit format for indirect register [2]. Table 4-19 describes

the functions for indirect register [2].

TRANSMIT BAUD RATE
GENERATOR

p—

TRANSMIT ERROR

SRR

ORI

I
|

at
UNUSED BITS

G
O

INDIRECT

15
UNUSED BITS

BAUD
TRANSMIT
‘
'RAN
RATE

o8 |

| TRANSMIT
A
T TE
GENERATOR

TRANSMIT ERROR
REGISTER

TRANSMIT | MESSAGE

UNDERRUN | LENGTH
VIOLATION
TRANSMIT

ERROR
TK-8681

Figure 4-9

Synchronous Indirect Register [2]

PROGRAMMING
v,

Table 4-19

Bits
(0)

Title

Indirect Register [2] Functions

Function

Message

Bit (0) is set by the synchronous interface if the charac-

Length
Violation

ter count indicates a buffer length too small for the
message of the specific protocol. This error can be

detected before transmission is begun (SDLC frame
under four characters).
This bit is cleared by a Master Reset or by reading the
transmit error register.

(1)

Transmit

This bit is set if the synchronous interface UNIBUS

DMA Error

controller did not receive a SSYN at least 32 us after
issuing a MSYN.

This bit is cleared by a Master Reset, INIT, or by the
reading of transmit error register bits (7:0).

(2)

Transmit

This bit is set if a transmit underrun condition is

Underrun Error

detected. This would occur if the synchronous interface could not process and direct memory access the
transmitted characters fast enough (because the synchronous interface was operating at too high a baud
rate).
The transmit underrun error bit is cleared by a Master
Reset, INIT, or by reading the transmit error register

bits (7:0).

(7:3)

Unused Bits

(11:8)

Transmit
Baud Rate
Generator

Bits (11:8) specify the baud rate for the internal baud
rate generator. Table 4-20 lists the transmit baud rates.

(15:12)

Unused Bits

These bits are cleared by a Master Reset or an INIT.

PROGRAMMING

Table 4-20

Transmit Baud Rates

Bits (11:8)

Bits Per Second

0000

800.000

0001

1,200.000

0010

1,760.000

0011

2,152,357

0100

2,400.000

0101

4,800.000

0110

9,600.000

0111

19,200.000

1000

28,800.000

1001

32,081.013

1010

38,400.000

1011

57,600.000

1100

76,800.000

1101

115,200.000

1110

153,600.000

1111

316,800.000

CAUTION

Operation at speeds greater than 19,200 bps is not recommended due to bandwidth limitations.

4.5.4

sonen

Indirect Register [3]

Indirect register [3] contains the sync character used for transmit idle fill for a
transmit underrun and receive synchronization. This register also contains the

specified number of sync characters to be transmitted prior to a message.
Figure 4-10 shows the bit format for indirect register [3]. Table 4-21 describes
the functions of indirect register [3].

SYNC REGISTER

Figure 4-10

Synchronous Indirect Register [3]

00
NUMBER OF SYNCS

PROGRAMMING
s

Table 4-21

Indirect Register [3] Functions
AT

Bits

Title

Function

(7:0)

Number of
Syncs

Bits (7:0) specifies the number of sync characters
specified in sync register (indirect register [3] bits
(15:8)) to be transmitted prior to a message.

(15:8)

Sync Register

This register is used only for byte-oriented protocols, and has the following functions:
s

It contains the sync character transmitted
between messages when the IDLE bit is
clear. Thus, this register is used as an idle
fill. Also, the contents of this register are
transmitted before a transmit message is
direct-memory accessed. The number of
sync characters transmitted should be
specified in the number of sync register

bits (7:0).

SH:

The character in the sync register is used
for receive synchronization.

4.5.5

Indirect Register [4]

Indirect register [4] consists of two registers: receive modem register and trans-

mit modem register. The receive modem register contains all the modem signals that originate from the DCE. The transmit modem register contains the

modem signals to be transmitted to the DCE.
Py

Figure 4-11 shows the bit format for indirect register [4]. Table 4-22 describes

the functions of indirect register [4].
G

TRANSMIT MODEM
REGISTER

RECEIVE MODEM
REGISTER

INDIRECT

|l 07

UNUSED

BITS

|
|

| RING

CLEARTO

| | INDICATOR | SEND

| paTA

| SET

;

CARRIER
DETECT

USER

RECEIVE MODEM
REGISTER

RECEIVE

UNUSED BIT

| READY

| 15

08 |
S

UNUSED BITS
REQUEST
TO SEND

DATA

SIGNAL
RATE
SELECT

UNUSED BIT

USER

| TRANSMIT
o

DATA
TERMINAL

READY

Figure 4-11

Synchronous Indirect Register [4]

TK-BEB3

PROGRAMMING

Table 4-22
Bits

Title

(1:0)

Unused Bits

(2)

User Receive

Indirect Register [4] Functions
Function

Bit (2) is connected (via a jumper) to pin 25 of the
25-pin Cinch connector on the distribution panel.
The user receive bit can be used for whatever purpose the user desires.

The ON-to-OFF or OFF-to-ON transition of this signal causes the data set change bit (transmit CSR bit
(6)) to set.

(3)

Unused Bit

(4)

Clear To Send

Bit (4) reflects the state of the Clear to Send line
(RS-232C circuit CB) originating from the modem.
Any ON-to-OFF or OFF-to-ON transition of this line
asserts the data set change bit (transmit CSR bit

(6)).

(5)

Carrier Detect

This bit reflects the state of the Received Line
Signal Detector line (RS-232C circuit CF) originating
from the modem. Any ON-to-OFF or OFF-to-ON
transition of this line asserts the data set change bit
(transmit CSR bit (6)).

(6)

Ring Indicator

This bit reflects the state of the Ring Indicator line
(RS-232C circuit CE) originating from the modem.
Any ON-to-OFF or OFF-to-ON transition of this line
<asssertss. the data set change bit (transmit CSR bit
6)).

(7)

Data Set
Ready

(8)

User Transmit

(9)

Data Terminal
Ready

Bit (7) reflects the state of the Data Set Ready line
(RS-232C circuit CC) originating from the modem.
Any ON-to-OFF or OFF-to-ON transition of this bit
asserts the data set change bit.
This line is connected (via a jumper) to pin 18 of the
25-pin Cinch connector on the distribution panel.
This pin is an EIA RS-232C unassigned pin, and can
be used for whatever purpose the user desires.

Bit (9) controls the Data Terminal Ready line (EIA
RS-232C circuit CD) connected to the modem.
When bit (9) is set, the Data Terminal Ready line is
in the ON state. If this bit is clear, the Data Terminal
Ready line is in the OFF state.

PROGRAMMING

Table 4-22

Indirect Register [4] Functions (Cont)

Bits

Title

Function

(10)

Data Signal
Rate Selector

Bit (10) controls the Data Signa! Rate Selector line
(EIA RS-232C circuit CH) connected to the modem.
When this bit is set, the Data Signal Rate Selector
line is in the ON state. If this bit is clear, the Data
Signal Rate Selector line is in the OFF state.

(11)

Unused Bit

(12)

Request to
Send

Bit (12) controls the Request to Send line (EIA RS232C circuit CA) connected to the modem. When
this bit is set, the Request to Send line is in the ON

state. If this bit is clear, the Request to Send line is
in the OFF state.

(15:13)

Unused Bits
A

4.5.6

Indirect Register [5]

Indirect register [5] bits (15:0) contains either the secondary station address or
the tributary station address. For bit-oriented protocols, this register contains

the secondary station address. For DDCMP, this register contains the tributary

station address. The synchronous interface compares this address with the

address of an incoming receive message to determine whether the message is
destined for this node. If the station has a one-byte address, then only the low
byte is used and the upper byte is ignored.
Figure 4-12 shows the bit format for indirect register [5].

SECONDARY STATION ADDRESS

TR-8684

Figure 4-12

Synchronous Indirect Register [5]

PRHSGOO)

OB,

PROGRAMMING

Indirect Registers [6] and [7]

4.5.7

Figure 4-13 shows the bit format for both indirect registers [6] and [7].

Indirect register [6] bits (15:0) and indirect register [7] bits (15:14) together

contain the 18-bit primary receive buffer address. Indirect register [7] bits

(15:14) contain the two most significant address bits. This address points to a

receive data buffer in main memory. A received message is transferred into this

—

buffer via nonprocessor request (DMA).

_—
e
e

Indirect register [7] bits (13:0) are the primary receive character count register.

This register is loaded with the size (in bytes) of the receive data buffer (the
buffer pointed to by the primary receive character count buffer address). This
character count register is decremented by the synchronous interface each
time data is transferred to main memory. The program may read this register to

calculate the length of the received message. If the message size is larger than

condition is flagged by the receive overflow bit. Loading this register clears the

4.5.8 Indirect Registers [8] and [9]
Figure 4-14 shows the bit format for both indirect registers [8] and [9].

the buffer space allotted to the message, then part of the message is lost. This
receiver done primary bit.

Indirect register [8] bits (15:0) and indirect register [9] bits (15:14) together

contain the 18-bit secondary receive buffer address. Indirect register [9] bits

(15:14) contain the most significant address bits. This address points to a

receive data buffer in main memory. A received message is transferred into this

buffer via nonprocessor request (DMA).

PRIMARY RECEIVE BUFFER ADDRESS
15

| a%nég?r%‘; (6]
00

PRIMARY RECEIVE CHARACTER COUNT
-

PRIMARY RECEIVE
BUFFER ADDRESS

Figure 4-13

Synchronous Indirect Register [6] and [7]

INDIRECT
REGISTER (8]

‘

SECONDARY RECEIVE BUFFER ADDRESS

o
15

ggggg-%g (7]

1413

SECONDARY RECEIVE CHARACTER COUNT

SECONDARY RECEIVE

BUFFER ADDRESS
Figure 4-14

Synchronous Indirect Register [8] and [9]

INDIRE
o]
REGISTER

TK-B686

PROGRAMMING
s,

Indirect register [9] bits (13:0) are the secondary receive character count regis-

ter. This register is loaded with the size (in bytes) of the receive data buffer (the

RIS

buffer pointed to by the secondary receive character count buffer address).

This character count register is decremented by the synchronous interface
each time data is transferred to main memory. The program may read this

register to calculate the length of the received message. If the message size is
larger than the buffer space allotted to the message, then part of the message

is lost. This condition is flagged by the receive overflow bit. Loading this
register clears the receiver done secondary bit.

4.5.9

Indirect Registers [10] and [11]

]

Figure 4-15 shows the bit format for both indirect registers [10] and [11].
B

Indirect register [10] bits (15:0) and indirect register [11] bits (15:14) together
contain the 18-bit primary transmit buffer address. Indirect register [11] bits
(15:14) contain the two most significant address bits. This address points to a
transmit data buffer in main memory. A message to be transmitted is transferred from this buffer to the synchronous interface via nonprocessor request

(DMA). The primary transmit character count register (primary transmit charac-

p——

ter count) contains the size (in bytes) of the message.
AV

Indirect register [11] bits (13:0) are the primary transmit character count register. This register is loaded with the size (in bytes) of the transmit data buffer

(the buffer pointed to by the primary transmit character buffer address). This
character count register is decremented each time data is transferred from the
synchronous interface to main memory. Loading this register clears the transmit done primary bit.

4.5.10

Indirect Registers [12] and [13]

Figure 4-16 shows the bit format for both indirect registers [1 2] and [13].

Indirect register [12] bits (15:0) and indirect register [13] bits (15:14) together
contain the 18-bit secondary transmit buffer address. Indirect register [13] bits

(15:14) contain the two most significant address bits. This address points to a
transmit data buffer in main memory.

A message to be transmitted is transferred from this buffer to the synchronous interface via nonprocessor request

(DMA). The secondary transmit character count register (secondary transmit

character count) contains the size (in bytes) of the message.
Indirect register [13] bits (13:0) are the secondary transmit character count register. This register is loaded with the size (in bytes) of the transmit data buffer (the

buffer pointed to by the secondary transmit character buffer address). This
character count register is decremented each time data is transferred from the
synchronous interface to main memory. Loading this register clears the transmit done secondary bit.

PROGRAMMING

INDIRECT
REGISTER [10]

PRIMARY TRANSMIT BUFFER ADDRESS

INDIRECT
REGISTER [11]

PRIMARY TRANSMIT CHARACTER COUNT

PRIMARY TRANSMIT
BUFFER ADDRESS
TK-8687

Figure 4-15

Synchronous Indirect Registers [10] and [11]

INDIRECT

SECONDARY TRANSMIT BUFFER ADDRESS

00
INDIRECT
REGISTER[ [13]

SECONDARY TRANSMIT CHARACTER COUNT

SECONDARY TRANSMIT
BUFFER ADDRESS
TK-8688

Figure 4-16

Synchronous Indirect Registers [12] and [13]

15
UNUSED BITS

MATCH CHARACTER

TK-8689

Figure 4-17
4.5.11

Synchronous Indirect Register [14]

Indirect Register [14]

Figure 4-17 shows the bit format for indirect register [14].

Indirect register [14] bits (7:0) contains the match character. This termination
character is used only when operating in GEN BYTE mode. If receive match bit
(receive CSR bit (3)) is set, receiving a character that matches the character
stored in this register causes an interrupt.

Indirect register [14] bits (15:8) are not used.
4.5.12

Indirect Register [15]

This indirect register is not used.

PROGRAMMING
.

4.6

SYNCHRONOUS INTERFACE PROTOCOLS

The synchronous interface supports the following bit-oriented protocols:
® SDLC-Synchronous Data Link Control (IBM)
e HDLC-High Level Data Link Control (ISO)

The synchronon interface supports bit-oriented protocols by performing the
following:

e Bit stuffing and bit removal

* Flag character (01111110) recognition for receive message framing
* Flag character generation for transmit message framing
® Abort character (01111111) recognition in a receive message

¢ Abort character (11111111) generation in a transmit message

e Secondary station address recognition in a receive message (maximum
address length dependent upon protocol) when operating as a secondary

station

e CRC check on a receive message

CRC generation on a transmit message
4.6.1

Bit-Oriented Protocol — Transmit Operation

SRS

A message is preceded with an opening flag and is terminated with a closing
flag (01111110). Between transmitted messages, the synchronous interface
either sends ones or flag characters on the synchronous line, depending on
whether the idle bit (transmit CSR bit (3)) is a zero or a one.

4.6.1.1

Bit Stuffing - Bit stuffing prevents a flag character within the message
from being transmitted as a flag sequence. The synchronous interface performs

bit stuffing by inserting a 0 after any sequence of five ones within the message.
When CRC is specified, the CRC calculations include all bits within the mes-

AN,

sage, except for the stuffed zeros. The opening and closing flags are not includ-

ed in the CRC calculations.

4.6.1.2

Bit-Oriented Protocol Transmit Errors - A DMA memory error (indirect
register [2] bit (1)) or a transmit underrun error (indirect register [2] bit (2))

causes the transmission to abort. When the transmission is aborted, the syn-

chronous interface automatically transmits an abort character (11111111).
R

The synchronous interface detects a transmit length violation error prior to
message transmission. This error indicates that the message length is less than

four bytes.

PROGRAMMING

The transmit error bit (transmit CSR bit (14)) is an inclusive OR of all error bits in
the transmit error register (indirect register [2] bits (7:0)). Asserting the transmit
error bit causes the transmit enable bit (transmit CSR bit (0)) to clear. With the
transmit enable bit cleared, subsequent messages are not transmitted until the
program acknowledges the error condition.

The message in the transmit buffer should contain the complete SDLC or HDLC
frame, starting with the address field and terminating with the final data charac-

ter. The synchronous interface inserts the CRC characters prior to the closing
flag. If CRC is not specifed, the message should contain the CRC check as the
final 16 bits.

The transmitter operates the same for both SDLC and HDLC. However, the
receiver operates differently due to different interpretation of the address field

bits.

4.6.2

Bit-Oriented Protocol — Receive Operation

The beginning of a frame is recognized by receiving a nonflag character after a
flag character. When operating as a secondary station, the synchronous interface compares the secondary station address field in the received frame with

the programmed secondary station address. If the two secondary station

address fields are identical, the synchronous interface initiates the NPR transfer

to the receive buffer in main memory. If the addresses are not identical, the
message is ignored and the synchronous interface searches for the next mes-

sage. Regardless of the programmed secondary station address, the “‘all parties” address (11111111) is always recognized as a valid address.

4.6.2.1

Bit-Oriented Protocol Secondary Station Address — SDLC specifies a

secondary station address of one byte. The program loads the secondary sta-

tion address into the low byte of the secondary station address register (indirect
register [5] bits (7:0)).
HDLC specifies a secondary station address of either one or two bytes. If the
least-significant bit of the first byte is zero, the second byte is the address

extension. The first secondary station address byte could be loaded by the pro-

gram into the secondary station address bits (7:0) (indirect register [5] bits
(7:0)). The optional second byte should be loaded into the secondary station

address bits (15:8) (indirect register [5] bits (15:8)).
4.6.2.2

ADCCP Protocol - The Advanced Data Communication Control

Procedure (ADCCP) protocol is implemented by running the synchronous interface in HDLC or SDLC mode. ADCCP specifies any number of bytes for the
secondary station address. If the least-significant bit of the first byte is zero,
then the second byte is also part of the address. If the least-significant bit of the

second byte is also zero, then the third byte is part of the address. The final byte
of the address has a 1 in the least-significant bit position of the address.

PROGRAMMING
S

In HDLC mode, the synchronous interface only compares the first two bytes of

a multi-byte address. If the two addresses are identical, the synchronous inter-

face initiates an NPR transfer of the message from the buffer to the main memory. Thus, to receive an ADCCP message in HDLC mode, the program must
verify that any remaining address bytes of the transferred message are destined for the respective node.

4.6.2.3

Bit-Oriented Protocol CRC - All bits in the received message (a frame)

are included in the CRC, except for the stuffed bits. The synchronous interface
removes the stuffed bits prior to the CRC calculation. The stuffed bits are

always removed, even if CRC is not specified.

The received CRC is compared to the CRC generated by the synchronous inter-

face. If the two CRCs are not identical, the receive BCC error bit (indirect regis-

ter [1] bit (3)) is set. The received CRC is not transferred to the buffer in main
memory if CRC checking is specified.

4.6.2.4

Bit-Oriented Protocol Receive Errors - If receive overrun error (indi-

rect register [1] bit (1)), receive DMA error (indirect register [1] bit (2)), receive
buffer overflow error (indirect error [1] bit (6)), or receive abort error (indirect
register [1] bit (5)) is set when a message is received, the synchronous interface
clears the receive enable bit (receive CSR bit (0)). Clearing the receive enable bit

RO,

disables the receiver, thus inhibiting any further message reception.
4.6.3

DDCMP - Receive Operation

The synchronous interface supports DDCMP by:

Checking CRC on a receive message

¢ Generating CRC on a transmit message
e Recognizing a tributary address

e Checking quick sync bit for subsequent resynchronization
e Checking byte count to determine message length
The synchronous interface can be operated as a control station (primary/
secondary station bit is clear) or a tributary station (primary/secondary station

bit is set). When operating as a tributary station, the program should load both
the secondary station address (indirect register [5] bit (7:0)) with the tributary
address. The synchronous interface uses the secondary station address to
check the address of a receive message. If operating as a control station, the
synchronous interface does not check the receive address field.
4.6.3.1

DDCMP Received Message - A receive message is transferred with

header and possible data to the receive buffer in main memory. The CRC

checks, header CRC, and data CRC are removed from the transferred message. All sync characters that cause byte synchronization are stripped. Trailing
pad characters are removed.

ORI

PROGRAMMING

4.6.3.2

DDCMP Data Streams - For data messages and maintenance mes-

sages, the synchronous interface reads the character count information in the
header, and thus knows where the data stream ends. For data messages, the

character count begins after the first start of heading (SOH) character; for maintenance messages, the character count begins after the first data link escape

(DLE) character. The receive DMA character count register must contain a
length at least as long as the header and the data. Control messages have no
data field and are of a fixed length of eight bytes. The receive DMA character

count register must be loaded with a value of at least six. The two CRC bytes

are not direct memory accessed.
4.6.3.3

DDCMP Receive Synchronization - The synchronous interface

checks the quick sync bit in the receive message. When the quick sync bit is set,
the synchronous interface resynchronizes at the end of the message. If the

quick sync bit is not set, the synchronous interface checks the byte immediately
following the end of the message. If this byte is an SOH, enquing (ENQ), or DLE,
the synchronous interface recognizes this byte as the beginning of an abutting

message. The receiver resynchronizes if the byte is not an SOH, ENQ, or DLE.
The receiver always resynchronizes after receiving a message with a CRC
error.

4.6.4

DDCMP - Transmit Operation

The transmit buffer should not include any CRCs, either header or data. The

synchronous interface generates the CRCs and inserts them at the correct
points (for both header and data) in the transmit message stream. The synchronous interface inserts at least twc:» pad characters (eight consecutive 1s) at the
end of each message.

For data messages and maintenance messages, the synchronous interface
reads the character count information in the header, and thus knows where the

data stream ends. For data messages, the character count begins after the first
SOH character; for maintenance messages, the character count begins after
the first DLE character. The transmit DMA character count register must contain a length at least as long as the header and the data, otherwise, the transmit

message length error bit becomes asserted. Control messages have no data
field, and are of a fixed length of eight bytes. The transmit DMA character count
register must be loaded with a value of at least six. The synchronous interface

generates the two CRC bytes.
4.6.4.1

DDCMP Transmit Errors — Asserting either the transmit DMA memory

error bit (indirect register [2] bits (1)) or transmit underrun error bit (indirect register [2] bit (2)) terminates the transmission. Termination causes the line to
either idle sync characters or to mark, depending on the state of the idle bit

(transmit CSR bit (3)).

Setting the transmit error bit (transmit CSR bit (14)), which is the inclusive OR of
all the transmit error bits, clears the transmit enable bit (transmit CSR bit (0)).
Clearing the transmit enable bit terminates the message transmission until the
program acknowledges the error condition.

Aoy

PROGRAMMING

4.6.5

General Byte-Oriented (GEN BYTE) Protocol

The GEN BYTE protocol transfers character-oriented transmit or receive data.
Any byte-oriented protocol may be implemented by having software perform
the protocol-specific functions. An optional programmable receive match char-

acter specifies that, when a match character is received, the synchronous interface should generate a receive interrupt. The receive match character bit

(receive CSR bit (3)) determines if the optional programmable match character
is to be used. The programmable match character should be loaded into the
match character register bits (7:0). Also, block check or parity generation and
S

detection may be performed.

4.6.5.1

GEN BYTE Protocol — The character used for receive synchronization

is stored
in sync register bits (7:0). Receiving two successive sync characters
signals synchronization. If the strip sync bit is set, all sync characters contiguous to the initial two sync characters that caused synchronization are not

transferred to the receive buffer in main memory. This buffer is loaded with
receive data until the character count register counts to zero.

4.6.5.2

GEN BYTE CRC - If CRC is specified, the synchronous interface

checks the receive CRC and indicates an error condition by setting receive BCC

error bit (indirect register [1] bit (3)). If vertical redundancy check (VRC) or VRC
and longitudinal redundancy check (VRC/LRC) are specified, the first detection

of a VRC error sets the receive VRC error bit (indirect register [1] bit (4)). If
VRC/LRC is specified and only an LRC error is detected, the receive BCC error

bit (indirect register [1] bit (3)) is set.
4.6.5.3

Transmit Operation — Characters are direct memory accessed from

the buffer in main memory until the character count register counts to zero. If

CRC is specified, the synchronous interface generates the block check and
appends the block check to the end of the message. If the VRC is specified, the
synchronous interface attaches a parity bit to each character. If the VRC/LRC
are specified, the synchronous interface attaches a parity bit to each character,

and appends the LRC to the end of the message.
4.7

ASYNCHRONOUS INTERFACE
i

The asynchronous multiplexer contains eight transmit and eight receive lines.

Each of the asynchronous lines may be programmed to operate at one of 16
baud rates, ranging from 50 bps to 19,200 bps. Although the lines can be programmed to run at 19,200 bps, this should be done with caution, for the clock

error at 19,200 bps is 3.125%. The actual frequency is 19,800 bps. Two of the
eight lines have both split speed capability and modem control. Received char-

acters, with their respective line numbers and status information are stored in a
48-word silo. Interrupts may be generated if more than 16 characters are in the

silo or after the silo has been non-empty for a time exceeding the programmable timeout period since the last silo read.

PROGRAMMING

In SILO mode, each transmit line has its own 32-character silo for storing data

to be transmitted. Characters may be loaded into a silo one or two at a time. In
DMA mode, characters transmit from main memory via DMA, as specified by

the transmit line’s buffer address register and character count register. Once
DMA is initiated, the transmit silo is automatically filled with characters and

transmission may begin if the transmitter is enabled. After the silo fills, DMA

stops. When the silo count drops below two characters, DMA is restarted and
the silo is refilled. This cycle continues until the DMA byte count is equal to zero.
When the DMA byte count is zero and the last character has been removed
from the transmit silo, an interrupt will be requested if enabled.

The auto XON/XOFF mode is selectable on a per line basis and may be used in

DMA or silo transmit mode. When auto XON/XOFF is selected, the DMF32 automatically disables the transmitter for a line receiving an XOFF. The XOFF is still
entered in the receive silo, so the operating system may disable its timeout

function. Receiving an XON reenables the transmitter for that line. The XON is
also put into the receive silo to inform the operating system that transmissions
have restarted. This mode allows relatively long silo timeouts as the time-critical

XOFF instantly disables the transmitter.
4.7.1

Asynchronous Device Registers

The asynchronous interface uses four device registers and 32 indirect registers.
The device registers are as follows:

Control status register
Line parameter register

Receiver buffer
Receive silo parameter register

4.7.1.1 Control Status Ragister - The control status register performs the

o
©

Indicates when data becomes available in the receive silo.

Contains the transmit line number.

Enables the receive interrupt.

Indicates DMA error.

©¢

Initiates Master Reset.

Enables transmit interrupt.

Points to one of 32 indirect registers.

following:

Indicates transmit ready.

4.7.1.2

Line Parameter Register — The line parameter register indicates the

following:
¢ The line selected

The character length
Parity enabled

Even/odd parity
The stop code

Baud rates

PROGRAMMING

4.7.1.3

Receive Buffer Register -~ The receive buffer register performs the

following:

o Stores the receive character with line number and error status.
* Indicates when there has been a data set change and on which line.

® [ndicates parity, framing, and overrun errors.
® |ndicates when data is valid in the receive buffer.
4.7.1.4

Receive Silo Parameter Register - The receive silo parameter register

contains the receive silo alarm timeout.

4.7.2

Asynchronous Device Operation

After an INIT or a Master Reset, the transmit and receive buffers are empty, and

all lines are disabled. The program must load the line parameter register bits
O

(15:0) with the desired parameters for specific lines before enabling these lines,
even if all parameters are zero. Line select (line parameter register bits (2:0))
should contain the line number whose parameters are to be loaded. The program should also set the appropriate interrupt enable bits in the control status
register. The program is now ready to enable the desired transmit and receive
lines. The modem control signals emanating from the asynchronous multiplexer

can be set or cleared at any time. A Master Reset or INIT clears the bits in the

CSR representing the transmit modem bits. However, the actual transmit
modem signals are cleared only after an INIT, and are not affected by a Master

Reset.

4.7.2.1

Asynchronous Transmit Operation — A line must be enabled to transmit data. Setting the appropriate bits in the line parameter register enables a

transmit line. A disabled line is held marking unless the line is programmed for
auto echo or remote loopback.

When the transmit ready bit is set, the transmitter is available for loading. The

transmit ready bit is set under the following conditions:
* In silo mode, when a transmit silo becomes empty due to a character leaving the silo.

* In DMA mode, when a DMA transfer for a particular line has completed,

and the last character has been removed from the silo.
S

The transmit interrupt enable bit enables and disables the transmit ready bit to
generate interrupts.

If the transmit interrupt enable bit is active when the transmit ready bit becomes
set, an interrupt to the transmit vector is posted. The program should read the
asynchronous CSR to determine the cause of the interrupt. If the transmit ready
bit is set, the transmit line number (asynchronous CSR bits (10:8)) contains the
line number of the empty silo. If transmission stops due to an aborted DMA

transfer, the transmit DMA error bit is set. Reading the asynchronous CSR
clears the transmit ready bit. The transmit ready bit must be cleared before the
asynchronous interface can reset it for another line.

PROGRAMMING

To minimize interrupt overhead, the program should try to keep the silos filled.

If the program intends to fill the silo, it may examine the transmit silo count register for the particular line to determine how many characters have been transmitted from the silo while being filled.

The silo count indicates how many full positions there are in the silo. Thus a silo

count of zero indicates an empty silo, while a silo count of 32 indicates a full
silo. The transmit silo count registers may be examined at any time. A transmit

silo of a particular line may be loaded or flushed regard ess of whether the
respective transmit line is enabled.

If a line is disabled while its silo is being emptied, transmission stops after the

current character has been transmitted. The silo contents will remain valid.
Transmission from the silo resumes upon enabling the line.

4.7.2.2

Asynchronous Receiver Operation - A receive line is enabled by set-

ting the appropriate bit in the line parameter register. A line must be enabled to

receive data. All lines share a 48-character receive silo. There is no DMA mode
for the receiver.

The receive silo is accessed via the receive buffer. Every time the receive buffer
is read, data words in the silo are shifted down one position. Successive read

cycles access successive silo entries. The receive silo contains receive charac-

ters and associated status information, and also data set change information.
4.8

ASYNCHRONOUS DEVICE REGISTERS

The asynchronous interface uses four device registers and 32 indirect registers.

Control status register

Line parameter register

Receiver buffer register

The device registers are as follows:

Receive silo parameter register

4.8.1

Control Status Register

Asynchronous Control Status Register has an address of base +C.
Read/modify/write UNIBUS cycles are not allowed. This register can be

accessed by word only.
Figure 4-18 shows the bit format for the asynchronous control status register.
Table 4-23 describes the functions for the asynchronous control status
register.

PROGRAMMING

TRANSMIT LINE
NUMBER

,
‘
INDIRECT REGISTER ADDRESS

TRANSMITTER|UNUSED BIT|

UNUSED

RECEIVE

MASTER

READY

BIT

DATA

RESET

AVAILABLE
TRANSMIT

TRANSMIT

INTERRUPT
ENABLE

DMA ERROR

Figure 4-18

RECEIVE
INTERRUPT

ENABLE

Asynchronous CSR

Table 4-23

Asynchronous Control Status Register Functions

Bits

Title

Function

(4:0)

Indirect
Address

These read/write bits point to one of thirty-two
indirect registers.

|
R

A Master Reset or INIT clears bits(4:0).

Master Reset

When the program sets this read/write bit, a
Master Reset is initiated. This bit remains set
while the reset is in progress, and clears automatically after the reset has completed. The
program should not access the asynchronous
device registers, except for the asynchronous

control status register, during the reset. The
program can write a one to the Master Reset

bit during a reset, but the DMF32 will ignore it.
A Master Reset initializes various CSR bits as
specified in the bit descriptions.

(6)

Receive
Interrupt
Vector

When set, this bit allows interrupt requests to

be made to the receive vector when:

Receiver data available bit has been set

for longer that the timeout period.
e

More than 16 characters have entered the

receive silo.

A Master Reset or INIT clears this read/write
bit.
AT

Receive Data
Available

The DMF32 sets this bit when data becomes
available in the receive silo. The DMF32 automatically clears this bit when the receive silo
becomes empty.
This bit is read-only, and is cleared by a Master
Reset or INIT.

PROGRAMMING

Table 4-23

Asynchronous Control Status Register
Functions (Cont)

Bits

Title

Function

(10:8)

Transmit Line
Number
|

|
|
DMA Mode:
If the transmit ready bit (asynchronous CSR bit

(15)) is set, bits (10:8) contain the line number
of the transmit DMA transfer that has completed (successfully or unsuccessfully).

Silo Mode:

—

If the transmit ready bit (asynchronous CSR bit

(15)) is set, bits (10:8) contain the line number

- of the silo that has emptied.

e
-

(1)

Unused

(12)

Transmit DMA

fl
-

p—

Error

These read-only bits are cleared by either a

Master Reset, INIT, or reading the asynchro-

nous control status register.

This bit is used only when the respective line is
in DMA mode. This bit is set for the indicated

line if the DMF32 UNIBUS controller either did
not receive a SSYN at least 32 us after issuing

a MSYN. Bits (10:8) of the asynchronous control status register point to the line in error.

This read-only bit is cleared by a Master Reset,

INIT, or by reading this register.

(13)

Unused Bit

(14)

Transmit

Interrupt
Enable

When set, this bit allows an interrupt request to

be made to the transmit vector when the transmit ready bit (asynchronous CSR bit (15))

becomes set.

A Master Reset or INIT clears this read/write
bit.

(15)

Transmitter
Ready

Silo Mode: The DMF32 sets this bit when an

enabled line (pointed to by bits (10:8)) has
loaded the last character from the silo into

the respective UART’s holding register.
DMA Mode:

—
.-

The DMF32 sets this bit when an enabled line
(pointed to by bits (10:8)) has terminated a
DMA transfer either successfully or unsuc-

cessfully. A successful DMA termination

means that all the data has been transferred
from main memory to the DMF32 and that the

last character in the silo has been loaded into

the respective UART’s holding register. An

unsuccessful DMA transfer sets the transmit

DMA memory error bit (asynchronous CSR bit

This read-only bit is cleared when the program

reads the asynchronous CSR, or when a
Master Reset or INIT is performed.

PROGRAMMING
e

ORI

4.8.2

Line Parameter Register

The line parameter register has an address of base +E. Read/modify/write

UNIBUS cycles are allowed. Access is by word only.
A Master Reset or INIT causes the bits in the line parameter register to clear to

zero. The parameters for the line are only updated into the UARTs after this

always be loaded with the parameters for the particular line before the line is

enabled (even if the parameters are all zero).
This location, contains the line parameter for the line selected by indirect

address register bits (2:0).
g,

Figure 4-19 shows the bit format for the line parameter register. Table 4-24
describes the functions for the line parameter register.

TRANSMIT BAUD RATE | RECEIVE BAUD RATE

figggfifimfl
STOP CODE|

LINE SELECT

PARITY

APROIS

TSI,

ENABLE

EVEN/ODD
PARITY
TK-8691

Figure 4-19

Line Parameter Register

PROGRAMMING

Table 4-24

Line Parameter Register Functions

Bits

Title

Function

(2:0)

Line Select

Bits (2:0) contain the binary number of the line
to be loaded with parameters.

{4:3)

Character
Length

These two bits specify the character length
(not counting the start bits, stop bits, and the
parity bit, if enabled) for the selected line. Bit
codes for the characters are:
'Bit Code

Bits Per
Character

(5)

Parity Enable

When set, bit (5) causes a parity bit to be generated on transmission. The parity bit is
checked and stripped on reception for the
selected line.

(6)

Parity (even
odd)

When the parity enable bit is set, or bit (6)

(7)

(11:8)

Stop Code

Receiver
Baud Rate

specifies whether even or odd parity is generated and checked for the selected line. Parity is
indicated as follows:
e

Bit (6) is clear, odd character parity .

Bit (6) is set, even character parity

This bit specifies the number of stop bits for
the selected line, as follows:
e

Bit (7) is clear, one stop bit

Bit (7) is set, two stop bits

Split baud rate capability is supported for lines
zero and one. If line zero or line one is selected, the line parameter register specifies the
selected baud rate of the receiver, while line
parameter register bits (15:12) specify the
selected transmitter baud rate. However, if any
of lines two through seven are selected, then
bits (15:12) specify both the receive and transmit baud rates for the selected line. Bits (11:8)
are ignored when any of the lines two through
seven are selected. Table 4-26 lists the receiver baud rates.

(15:12)

Transmit
Baud Rate

Bits (15:12) specify one of 15 transmit baud
rates. Table 4-25 lists the bit codes for the
transmit baud rates.

PROGRAMMING
e,

Téb!e 4-25 Receiver and Transmit Baud Rates
A

Bit
Code

Desired
Baud Rate

Actual
Baud Rate

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100

50.00
75.00
110.00
134.50
150.00
300.00
600.00
1200.00
1800.00
2000.00
2400.00
3600.00
4800.00

75.00
110.00
134.52
150.00
300.00
600.00
1200.00
1800.00
2005.06
2400.00
3600.00
4800.00

0.0%
0.0%
0.0166%
0.0%
0.0%
0.0%
0.0%
0.0%
0.253%
0.0%
0.0%
0.0%

1101
1110
1111

7200.00
9600.00
19200.00

7200.00
9600.00
19800.00

0.0%
0.0%
3.125%

Deviation
(Per Cent)

50.00

0.0%

4.8.3

Receiver Buffer Register

The receiver buffer has an address of base +10. This register is read-only.

The program accesses the receive silo through the receiver buffer. Every time
this register is read, data words in the silo shift down one position. Successive
read cycles access successive silo entries. This receive silo contains receive

characters and associated status information, as well as data set change
information.

Either a Master Reset or INIT can flush this silo.
Figure 4-20 shows the bit format for the receiver buffer register. Table 4-26

S—————

describes the functions for the receive buffer register.

RECEIVE LINE

NUMBER

DATA

FRAMING | DATASET

VALID

ERROR

00
RECEIVE CHARACTER

CHANGE

OVERRUN

PARITY

ERROR

ERROR
A

TK-8692

Figure 4-20

Receive Buffer

PROGRAMMING

Table 4-26

Receiver Buffer Register Functions

Bits

Title

Function

(7:0)

Receive
Character

If data set change bit (receiver buffer bit (11)) is
clear, then the receiver buffer bits (7:0) contain the
received

character.

Bits

are

received

least-

significant bit (LSB) first. If parity is enabled, the
parity bit is stripped off. Characters less than eight
bits long are right-justified with the high order bits
set to zero.

If data set change bit (receiver buffer bit (11)) is set,
then the receiver buffer bits (7:0) will be zero; the
program should read the receive modem signals to
determine which signals changed.

{(10:8)

Receive Line
Number

These three bits contain the binary number of the
line on which a character was received or a data set
change was detected.

(11)

Data Set
Change

When this bit is set, the receiver buffer bits (7:0) are
‘zero, and the receiver line number (receiver buffer

bits (10:8)) contains the line number whose modem
signals changed state.

(12)

Parity Error

This bit is used only if the data set change bit is

clear. Bit (12) is set if parity is enabled for the line
on which the character is received, and the character is received with incorrect parity.

(13)

Framing Error

This bit is used only if data set change bit (receiver

buffer bit (11)) is clear. This bit is set if the line on

which the character was received was in the spacing (zero) state at the time the first stop bit was
sampled.

(14)

Overrun Error

This bit is used only if the data set change bit is
clear. Bit (14) is set if one or more previous characters were lost on the line on which the character
was received due to a full silo. The received character is valid.

(15)

Data Valid

When bit (15) is set, the remaining bits in the receiver buffer are valid. This bit is set when data is loaded into the receiver buffer, and remains set as long
as there is data in the buffer.
This bit is cleared by Master Reset, INIT, or when
the receiver buffer becomes empty.

~~~~~~

PROGRAMMING

4.8.4

Receive Silo Parameter Register

The receive silo parameter register has an address of base +208. This regmter

is write-only andis accessed by a word. The receive silo parameter register
contains the receive silo alarm timeout.
Figure 4-21 shows the bit format for the receive silo parameter register. Table
4-27 describes the functions of the receive silo parameter register.

UNUSED BITS

RECEIVER SILO ALARM TIMEOUT

TK-B893

Figure 4-21

Receive Silo Parameter Register

Table 4-27
Bits

(7:0)

Title

Receive Silo Parameter Register Functions
Function

Receiver Silo
Alarm Timeout

These eight bits specify the silo alarm timeout peri-

od. An interrupt is generated if data is in the silo for
a time equal to or larger than the timeout period.
Every time the receive silo is read, a Master Reset
or INIT occurs, the internal timer is initialized to

zeros.

The timeout period can range from approximately 0

to 300 ms.
00000000 = infinite

00000001 = no timeout

to
TSI

11111111 = maximum timeout
O

This interval timer is based on microcode loops and
thusis not very accurate. After a Master Reset or an
INIT, the timeout value is set to one.

PROGRAMMING

4.9

ASYNCHRONOUS INDIRECT REGISTERS

The indirect registers have an address of base +228. A 5-bit address (asynchronous control status register bits (4:0)) addresses the indirect registers.

The low three bits of the address indicate the line number being referenced.

The upper two bits select which indirect register of that line is being accessed.

4.9.1

Indirect Registers [0] Through [7]

Each indirect register [0] through [7] consists of a 16-bit write¥only register:

transmit character line [0] through [7]. Each indirect register [0] through [7] also
consists of two read-only registers: transmit silo count register and receive
-

modem register. The transmit character register is used only in silo mode to

load one or two characters into the 32-character transmit silo for the respective

—

line. The transmit silo count register is used only in silo mode to contain the

number of entries in the 32-character silo for the respective line. The receive
modem register contains all modem signals received from the DCE. Since lines

2 through 7 have no modem control signals, receive modem registers 2 through
7 are always read as all zeros.
-

Figure 4-22 shows the bit format for indirect registers [0] through [7]. Table

4-28 describes the functions of indirect registers [0] through [7].

—
(WRITE

TRANSMIT CHARACTER LINE ZERO THRU SEVEN

RECEIVE MODEM

TRANSMIT SILO

=0 FOR

COUNT (LINES 0 THRU 7)

LINES 2 THRU 7

ONLY)

INDIRECT

REG

(0]

THRU [7] FOR LINES 0 THRU 7
RESPECTIVELY

(READ ONLY) INDIRECT REG [0]

‘

oot
£ OR LINES 0 THRU 7
|

1 110

USED BITS

RING
CLEARTO |
INDICATOR| SEND
DATA SET

READY

USER
RECEIVE

SECONDARY RECEIVE
LINE SIGNAL DETECTOR

CARRIER

DETECT
TK-BES4

Figure 4-22

Asynchronous Indirect Registers [0] Through [7]

PROGRAMMING
OO

Table 4-28

Indirect Registers [0] Through [7] Functions
AN,

Bits

Title

(15:0)

Transmit
Character

Function

This write-only register should be written only in
SILO mode. Writing to this register in DMA mode
has unpredictable resulits.
Writing to this register, one or two characters are
entered into the 32 character transmit silo for the
selected line. When the write to this register is a
WORD (UNIBUS DATO), two characters are loaded
into the silo, the low-order character first. If the
write to this register is a BYTE (UNIBUS DATOB),
only the low-order character is loaded into the silo;
the high-order character is ignored. If the silo is full,
a write to this register has no effect on the silo.
WARNING

The program must wait eight us after writing to this register before accessing this
register again or accessing any other register on the DMF32. If this time period is
not respected, a SSYN timeout may occur on the subsequent DMF32 register
access.

(7:0)

Transmit
Silo Count

This read-only register is used only in silo mode.
The transmit silo count register contains the number of entries in the 32 character transmit silo for
the specific line.

A Master Reset or INIT clears this register.

(15:8)

Receive
Modem Status

The receive modem status register (indirect registers [0] through [7] bits (15:8)) is cleared during a
Master Reset or INIT, but is updated if the following
conditions are met:
e

Data set change flag clear.

Data set change flag is set and there is room in
the receive silo for a data set change entry.

After a Master Reset, the data set change flag is
cleared. If the receive silo is full, the data set change
is enabled; the data set change is flagged when the
silo is no longer full. Thus, data set changes are not
lost when the receive silo is full.

When read, bits (15:8) of this read-only register
contain the receive modem status for the selected
line. This register is valid only for lines 0 and 1.
Lines 2 through 7 return all zeroes in these bits. All
modem signals represented in this register emanate
from the DCE.

(9:8)

Unused Bits
P

PROGRAMMING

Table 4-28

Indirect Registers [0] Through [7] Functions (Cont)

Bits

Title

(10)

User Receive

(11)

Secondary
Receive

Line Signal

Function

Bit (10) is connected (via a jumper) to pin 25 of

the 25-pin CinchTM connector on the distribution panel. The user receive bit can be used for
whatever purpose the user desires.

This bit reflects the state of the secondary
received line signal detector (RS-232-C circuit
SCF) received from the modem.

Detector

(12)

(13)

Clear To
Send
Carrier
Detect

Bit (12) reflects the state of the Clear to Send
line (RS-232-C circuit CB) received from the

modem.

Bit (13) reflects the state of the Received Line
Signal Detector line (RS-232-C circuit CF)

received from the modem. If jumpered (on the

distribution panel), this bit can represent the
Secondary Receive Line Signal Detector.

(14)

Ring
Indicator

Bit (14) reflects the state of the Ring Indicator
line (RS-232-C circuit CE) which is received
from the modem.

(15)

4.9.2

Data Set
Ready

This bit reflects the state of the Data Set Ready
line (RS-232-C circuit CC) which is received

from the modem.

Indirect Registers [8] Through [15]

Indirect registers [8] through [15] have an address of base +12.
Read/modify/write UNIBUS cycles are allowed and all of the bits within these
registers may be read or written. These registers are accessed by word only.
Each indirect register [8] through [15] consists of two registers: a line control
register and a transmit modem register. Each line control register controls
various functions for each respective line (indirect register [8] controls line 0,
indirect register [9] controls line 1). Figure 4-23 shows the bit format for the line
control registers of indirect registers [8] through [15]. Table 4-29 describes the
functions of the line control registers. This register is cleared by a Master
Reset or INIT. However, this register must be loaded with the appropriate
information prior to using a line after a Master Reset.

PROGRAMMING

TRANSMIT MODEM REGISTER

INDIRECT REGISTER [8] THRU [15]
(LINES O THRU 7, RESPECTIVELY)

LINE CONTROL REGISTER

I
l

00 |

LINE CONTROL

[

)]

MAINTENANCE FLusH

| CONTROL CEl

RECEIVE | TRANSMIT
TRANSMIT | ENABLE | ENABLE LINE
SILO

DATASET

CHANGE

BREAK

ENABLE

|
TRANSMIT MODEM REGISTER

BITS

(LINES 0 AND 1 ONLY)
REQUEST

DATA

TOoSEND | SIGNAL

RATE
SELECT

TRANSMIT
AUTO
XON/XOFF

UNUSED

PREEMPT

USER

1 TransmIT
PR

SECONDARY

DATA

REQUEST

TERMINAL

TO SEND

READY
TK-8898

Figure 4-23

Asynchronous Indirect Registers [8] Through [15]

Table 4-29

Indirect Registers [8] Through [15] Functions

Bits

Title

Function

(0)

Transmit

When this bit is set, the transmitter for the

Enable Line

selected line is enabled. If this bit is clear,
the transmitter for the selected line is disabled. If the transmit enable bit is cleared
while a character is being transmitted, the

transmitter is disabled after the complete
character has been transmitted.

(1)

Transmit
Auto XON/XOF

ORI,

When this bit is set, XOFF disables the
transmitter for the respective line. The XOFF
is still loaded into the receive silo. Receiving

XON reenables that line. XON is also loaded
into the receive silo.

(2)

Receive Enable

When this bit is set, the receiver for the
respective line is enabled. If the bit is clear,
the receiver for the respective line is disabled. If the receive enable bit is set to zero
while a character is being assembled, the
character is lost.

[

(3)

Break

Setting this bit will force and hold the EIA
transmitted line to a space condition at the

end of the current transmitted character.
Normal operation will resume after the break
bit is cleared.

PROGRAMMING

Table 4-29

Indirect Registers [8] Through [15] Functions (Cont)

Bits

Title

Function

(4)

Flush Transmit
Silo Line

Setting this bit flushes the transmit silo for
the selected line and terminates the DMA in
progress. The contents of the transmit silo
are invalidated. Disabling the transmitter
does not flush the silo, it just inhibits character transmission. After the silo has been
flushed, this bit is automatically cleared and
a transmit interrupt is generated.

()

Data Set
Change Enable

When set, this bit enables the DMF32 to
search for a transition in the modem receive
signals for the selected line. Finding a
change results in an entry into the receive
silo with the data change bit set. If the data
set change enable bit is clear, transitions on
the receive modem lines for the selected line
are ignored.

Maintenance

Table 4-30 defines the maintenance control
function bits.

(7:6)

Control
Function Line

(8)

User Transmit

Data Terminal
Ready

This line is connected (via a jumper) to pin 18

of the respective line’s 25-pin Cinch connector on the distribution panel. This pin is an
EIA RS232-C unassigned pin that can be
used for any purpose.
This bit controls the Data Terminal Ready
line (EIA RS-232-C circuit CD) connected to

the modem. When bit(9) is set, the Data Terminal Ready line is in the ON state. If this bit
is clear, the line is in the OFF state.

(10)

Data Signal
Rate Select

Bit (10) controls the Data Signal Rate Select
line (EIA RS-232-C circuit CH) connected to
the modem. When this bit is set, the data
signal rate select line is in the ON state. If
the bit is clear, the line is in the OFF state.
Data signal rate select is a read/write bit that
is cleared by INIT, but is not affected by a
Master Reset.

(11)

Secondary
Request
To Send

This bit controls the Secondary Request to
Send line (EIA RS-232-C circuit SCA) connected to the modem. When this bit is set,
the Secondary Request to Send line is in the
ON state; if the bit is clear, the line is in the

OFF state.

(12)

Request To
Send

Bit (12) controls the Request to Send line
(EIA RS-232-C circuit CA) connected to the
modem. When this bit is set, the Request to

Send line is in the ON state; if the bit is clear,
the line is in the OFF state.

PROGRAMMING

Table 4-29

Indirect Registers [8] Through [15] Functions (Cont)

Bits

Title

(14:13)

Unused Bits

(15)

PREEMPT

This bit may be set by the. program to preempt silo output. When set, transmisssion is
halted. The user may then load the transmit
character indirect register. The low byte
loaded is transmitted and the silo is reenabled. This allows the program to interrupt a
silo or DMA transmission, send a character
(presumably an XON or XOFF), then continue silo or DMA transmission. No characters
are lost; the preempt character is merely
inserted into the effective transmit output
stream. Loading the character into the indirect register clears this bit.

Table 4-30

Bits (7:6)

Function

Maintenance Control Function Bits

Definition

Normal operation.

Automatic. echo mode. The received data is retransmitted at the
same baud rate as the receiver, regardless of the state of the transmit enable bit. The receive enable bit must be set for this mode to
work.

Local loopback. The transmitter output is internally connected via

DMF32 to the receiver input. The EIA Transmitted Data line is held
marking, while the EIA Received Data is ignored. Various other conditions must be satisfied to operate in local loopback mode. Also,
various modem receive signals are ignored when operating in this
mode. Refer to Section 4.10 for a description of these conditions.
11

Remote Loopback. The received data is not loaded into the receive
silo, but is automatically retransmitted. The receive clock clocks the
transmitter. The transmit enable bit is ignored.

The transmit modem registers contain the modem signals applied to the DCE.
Each transmit modem register controls a respective line (transmit modem reg-

ister of indirect register [8] controls line 0, indirect register [9] controls line 1).
The transmit modem registers for indirect registers [10] through [15] are not

used. Figure 4-23 shows the bit format for the transmit modem registers. Table
4-29 describes the functions of the transmit modem registers.
Although this register may be read and written for all lines, only lines 0 and 1

actually have modem connections.

A Master Reset does not clear the actual

transmit modem lines even though the bits in this register are zero. The actual

signals are updated after the transmit modem register is loaded. An INIT clears
the actual modem signals.

PROGRAMMING

4.9.3

Indirect Registers [16] Through [23] (Read/Write)

Indirect registers [16] through [23] have an address of base +12. Read/modnfy/
&

write UNIBUS cycles are allowed. These registers are accessed by word only.
Each buffer address register is used only if the respective line is in DMA mode.

This register should be loaded with thelow 16-bits of the DMA buffer address
for the respective line.

This register is read/write, and is not necessarily cleared by Master Reset or

INIT. After
a read or write of the DMA buffer address register, subsequent reads

or writes of the indirect register will access the DMA character count register.
This permits two writes of the indirect register to load first the DMA buffer

—

address register and then the DMA character count register without an intervening write to the indirect address register (asynchronous CSR bits (4:0)).
However, the indirect address register remains pointing to the DMA buffer

address register because only a working copy of the indirect address register
TM

~used by DMF32 microcode is auto-incremented. To access any other indirect
register, including the DMA buffer address register, the indirect register must be
reloaded. Reloading the indirect register updates the working copy of the indi-

rect register with the appropriate address.

)

The appropriate register is loaded with the low 16-bits of the DMA buffer
address for the respective line (indirect register [16] is used for line 0, indirect
register [17] is used for line 1).
Figure 4-24 shows the bit format for indirect registers [16] through [23].
These registers are read/write and are not always cleared by a Master Reset or

an INIT.

TRANSMIT BUFFER ADDRESS

INDIRECT
REGISTERS
[23:16]
(WRITE ONLY)
TK-8696

Figure 4-24

Asynchronous Indirect Registers [16] Through [23]

PROGRAMMING

4.9.4

Indirect Registers [24] Through [31]

Each indirect register [24] through [31] contains two registers: DMA character

count register and the upper two bits of the transmit buffer address. Bits (13:00)
of indirect registers [24] through [31] contain the 14-bit character counts for the
respective lines (indirect register [24] is used for line 0, indirect register [25] is

used for line 1).

Bits (15:14) contain the two most significant bits of the 18-bit UNIBUS buffer

address for the transmit lines.

Figure 4-25 shows the bit format for indirect registers [24] through [31].

Indirect registers [24] through [31] are read/write registers that are used only in

DMA mode. Read/modify/write UNIBUS cycles are allowed. Writing to these
registers initiates a DMA transfer. These registers are not always cleared by a
Master Reset or INIT.
15

00
INDIRECT
REGISTERS [31:24]

DMA CHARACTER COUNT
y

MSB OF UNIBUS

BUFFER
ADDRESS

Figure 4-25

4.10

Asynchronous Indirect Registers [24] Through [31]

RELATIONSHIP BETWEEN MAINTENANCE MODES AND MODEM

SIGNALS

Table 4-31 lists the relationship between maintenance modes and modem
signals.

Table 4-31
Async Line

Relationship Between Maintenance Modes
and Modem Signals

Mode

Description

Normal operation,

Async line zero Carrier Detect modem sig-

auto echo, and

nal must be ON for the receiver to operate.

remote loopback

Local loopback

Async

line

zero

modem signal

Data Terminal

is OFF.

Ready

Async line

zero

Request to Send modem signal is OFF. The
programmable bit Data Terminal Ready 0
must be ON, even though the actual Data
Terminal Ready modem signal for async line
zero is OFF. Carrier Detect 0 follows the
state of Data Terminal Ready 0. The Carrier
Detect modem signal for async line zero is
ignored.

The programmable bit Request to Send 0
must be ON, even though the actual

Request to Send modem signal for async
line zero is OFF.

PROGRAMMING

Table 4-31

Async Line

Relationship Between Maintenance Modes
and Modem Signals (Cont)

Mode

Description

Normal operation,
auto echo, and
remote loopback

Async line one Carrier Detect modem signal
must be ON for the receiver to operate.

Local loopback

Async line one Data Terminal Ready modem
signal is OFF. Async line one Request to
Send modem signal is OFF. The programmable bit Data Terminal Ready 1 must be
ON, even though the actual Data Terminal
Ready modem signal for async line one is
OFF. Carrier Detect 1 follows the state of
Data Terminal Ready 1. The Carrier Detect
modem signal for async line one is ignored.

The programmable bit Request to Send 1
must be ON, even though the actual
Request to Send modem signal for async
line one is OFF.

Normal operation,
auto echo, and
remote loopback

Operation is independent of any modem
|
signals.

Local loopback

User Transmit modem signal for async line
zero is OFF. The Secondary Request to
Send modem signal for async line zero is
OFF. The programmable bit USER TX 0
must be ON, even though the actual User
Transmit modem signal for async line zero
is OFF.

The programmable bit Secondary Request
to Send 0 must be ON, even though the
actual Secondary Request to Send modem
signal for async line zero is OFF.
- Normal operation,
auto echo, and
remote loopback

Local loopback

Operation is independent of any modem

signals.

User Transmit modem signal for async line
one is OFF. The Secondary Request to
Send modem signal for async line one is
OFF. The programmable bit USER TX 1
must be ON, even though the actual User
Transmit modem signal for async line one is
OFF.

The programmable bit Secondary Request
to Send 1 must be ON, even though the
actual Secondary Request to Send modem
signal for async line one is OFF.

PROGRAMMING

Table 4-31

Relationship Between Maintenance Modes
and Modem Signals (Cont)

Async Line

Mode

Description

Normal operation,
auto echo, and
remote loopback

Operation is independent of any modem
signals.

Local loopback

The Data Signal Rate Select modem signals
for async lines zero and one are OFF. The
programmable bit Data Signal Rate Select 0
must be ON, even though the actual Data
Signal Rate Select modem signal for async
line zero is OFF. The programmable bit Data
Signal Rate Select 1 must be ON, even
though the actual Data Signal Rate Select
modem signal for asynchronous line one is
OFF.

Normal operation,
auto echo, and
remote loopback

Operation is independent of any modem
signals.

Local loopback

The Request to Send modem signal for the
synchronous line is OFF. The Data Terminal
Ready modem signal for the synchronus
line is OFF. The programmable bit Data
Terminal Ready in the sync line must be ON,
even though the actual Data Terminal Ready
modem signal for the sync line is OFF.

The programmable bit Request to Send in
the sync line must be ON, even though the
actual Request to Send modem signal for
the sync line is OFF.
Normal operation,
auto echo, and
remote loopback

Operation is independent of any modem
signals.

Local loopback

The User Transmit modem signal for the
synchronous line is OFF. The Data Signal
Rate Select modem signal for the synchronous line is OFF. The programmable bit

USER TX in the sync line must be ON, even
though the actual User Transmit modem

signal for the sync line is OFF.

”

The programmable bit Data Signal

Rate

Select in the sync line must be ON; even
though the actual Data Signal Rate Select
modem signal for the sync line is OFF.
Normal operation,
auto echo, and
remote loopback

Local loopback

Operation is independent of any modem
signals.

PROGRAMMING

LINE PRINTER CONTROLLER

4.11

The line printer controller interfaces with LP model printers. Optionally, this
DMA device can perform the following low level formatting functions:
Tab expansion (with version 27 of the microcode)
Automatic carriage return insertion
Automatic line wrap

Form feed to multiple line feed conversion

The line printer controller uses two UNIBUS addresses. The first address
accesses the line printer CSR, while the second address accesses one of eight

indirect registers. The indirect address field (line printer CSR bits (10:8)) determines which one of the eight indirect registers is to be accessed.

The printer CSR performs enables:
The printer controller

Printer interrupt

~ Formatting
Master reset

Connect verify

Print done

Line printer error

DMA error

The printer CSR points to one of eight indirect addresses. It also indicates:

DAVFU ready

4.11.1

Line Printer Controller Operation

After power up or an INIT, the line printer controller is in the idle state. Next the
program should set the appropriate bits in the line printer CSR bits.
4.11.1.1 Loading Line Printer CSR and Indirect Registers — The line printer
CSR and indirect registers should be loaded as follows.

1. If formatting is desired, the format control (line printer CSR bit (2)) is set to
one; the indirect register address field (line printer CSR bits (10:8)) is set to
two. Setting the interrupt enable bit (line printer CSR bit (6)) enables the
interrupts.

2. The program loads indirect register [2] bits (15:0) with the prefix character

(indirect register [2] bits (15:8)) and the prefix character count (indirect
register [2] bits (7:0)). The prefix character count specifies the number of
prefix characters inserted at the beginning of the message. Accessing the

indirect register, increments the indirect address field (line printer CSR bits
{(10:8)) by one.

100

PROGRAMMING

3. The program then loads indirect register [3] bits (15:0) with the suffix character (indirect register [3] bits (15:8)) and the suffix character count (indi-

rect register [3] bits (7:0)). The suffix character count specifies the number
of suffix characters to be appended at the end of the message.
4. The program loads the low order 16 bits of the DMA buffer address into

the indirect register [4] bits (15:0). The program then loads the DMA
character count in two’s complement form into indirect register [5] bits
(15:0). The next word loaded should contain the two high order bits of the

UNIBUS DMA buffer address, and certain format control.
A

5. The last word loaded should contain the number of lines on a page (indirect register [7] bits (7:0)) and the carriage width (indirect register [7] bits

(15:8)) for the particular line printer used.

6. If formatting is not desired, then the format control (line printer CSR bit (2))
is cleared to zero. The indirect register address field (line printer CSR bits

(10:8)) is set to 4. Three writes to the indirect register load the DMA character count and buffer address.

At this point, all the appropriate indirect registers have been loaded. Table 4-32
lists the indirect registers.

4.11.1.2

Line Printing Cycle - To initiate printing, the program sets the print

enable bit (line printer CSR bit (0)). After the device successfully transfers the
last character to the line printer, the print done bit (line printer CSR bit (7)) is set.
The print enable bit automatically clears when the print done bit becomes set. If

the interrupt enable bit (line printer CSR bit (6)) is set, an interrupt request is

posted. The interrupt service routine should read the line printer CSR. If the service routine finds the print done bit (line printer CSR bit (7)) set and the line

printer error bit (line printer CSR bit (14)) clear, this indicates a successful print

cycle.

The indirect register auto-increment feature reduces the number of device reg-?
ister accesses the interrupt service routine must make. Either a read or write to
an indirect register increments the address field by one.

After a successful print cycle, if formatting is enabled, the program should read

the indirect register twice to retrieve two words of status. The indirect address

field is equal to zero at this time. The first word (indirect register [0]) is a count
of the number of bytes transferred to the line printer. The second word (indirect

from the last print cycle.

After having read the status of the previous print cycle, the indirect register
address field points to indirect register [2]. To initiate a new DMA cycle, successive writes to the indirect register are executed to load the desired parameters
and then the print enable bit (line printer CSR bit {(0)) is set.

PSS

PROGRAMMING

Table 4-32

Indirect Register

_—

2
M

Name

Bytes transmitted

[1] - bits (15:0)

Line count

[2] - bits (15:8)

Prefix character

[2] - bits (7:0)

[3] - bits (15:8)

Suffix character

Suffix character count

[4] - bits (15:0)

DMA buffer address (15:0)

DMA character dount in2's

complement form

[6] - bits (1:0)

DMA buffer address (17:16)

[6] - bits (7:‘2)

Unused bits

[6] - bit (8)

Auto carriage return insert

[6] - bit (10)

[6] - bit (11)

[6] - bit (12)

[6] - bit (13)

Prefix character count

[3] - bits (7:0)

[5] - bits (15:0)

Line Printer Indirect Registers

[0] - bits (15:0)

[6] - bit (9)

101

Form feed to line feed convert
Nonprintable character accept

~ DAVFU

Line wrap
Inhibits line truncation

(requires version 28 of microcode)

[6] - bit (14)
|

Inhibits tab expansion
(requires version 27 of microcode)

[6] - bit (15)

Lower case to upper case convert

[7] - bits (15:8)

Line printer carriage width

[7] - bits (7:0)

Lines per page

4.12 LINE PRINTER CSR REGISTER
The line printer control status register has an address of base +14.

Read/modify/write UNIBUS cycles are allowed. This register is accessed by
word only.

Figure 4-26 shows the bit format for the line printer CSR. Table 4-33 describes
the functions for the line printer CSR.

102

PROGRAMMING

0605

INDIRECT

ERROR

READY

|UNUSED BIT

g:‘.‘r‘ffi”

ADDRESS
NXM

|MAINTENANCE

FORMAT

DONE

|MODE

CONTROL |

ENABLE

LINE

CONNECT

INTERRUPT

MASTER

PRINTER

VERIFY

ENABLE

RESET

ERROR

Figure 4-26

Line Printer CSR

Table 4-33

TK-8698

Line Printer Control Status Register Functions

Bits

Title

Function

(0)

Print Enable

This bit is used to initiate, suspend, or continue line printer output.
|

)

When this bit is set, the line printer controller
is enabled. When enabled, characters are

transferred from the controller to the line

printer, provided there are characters to
send. If this bit is clear, no characters are
transferred from the controller to the line
printer.

If the print done bit (line printer CSR bit (7))
is set, writing a one to set the print enable bit
(line printer CSR bit (0)) clears the following:

DMA error (line printer CSR bit (15))
Print done (line printer CSR bit (7))
Indirect register [0] (bytes transmitted)
Indirect register [1] (line count)
This bit is read/write and is cleared by either

a Master Reset or INIT. This bit is automatically cleared when the print done bit (line
printer CSR bit (7)) or DMA error bit (line
printer CSR bit (15)) becomes set.

(1)

Master Reset |

The program can read Master Reset, but
write ones only. When the program sets this

bit, a Master Reset is initiated. The Master
Reset bit remains set while the reset is in

progress, and clears automatically after the

reset has finished.

The program should not access the line
printer device registers, other than line printer CSR, while the reset is in progress. The

program may write a one to the Master

Reset while the reset is in progress, but the

- DMF32 ignores such action.

Master Reset or an INIT clears lines per
page (7:0). All other indirect registers are

indeterminate after a Master Reset or INIT.
The device driver ensures that the indirect
registers contain valid data. The Master
Reset may be used to abort the output.

PROGRAMMING

Table 4-33

Line Printer Control Status Register Functions (Cont)

Bits

Title

Function

(2)

Format Control

When the format control field is clear,
formatting is disabled. Characters from main
memory are direct memory accessed directly to the line printer.

When the format control field contains 1,
formatting is enabled.
If the format control field contains 1, and
DAVFU bit is set, all direct memory
accessed characters with MSB set are discarded by DMF32, unless the character is a
‘“‘paper instruction channel select’” code
(#200:#213), or a "‘paper instruction, lines
to be stepped’’ code (#200:#237) in which
case, the character is passed on to the printer. However, if the format control field contains 1 and DAVFU bit is clear, all direct
memory accessed characters with MSB set
are discarded by DMF32. If the format control field contains 0, all characters, regardless of their MSB, are transmitted to the line
printer.

The format control field is read/write, and is
cleared by a Master Reset or an INIT.
(4:3)

‘Unused Bits

These bits are always read as zeros.

(5)

Maintenance
Mode

When this bit is set, data is not sent to the
line printer, but written into the DMF32 diagnostic register. The diagnostic register is the

second word of the 16 words DMF32
responds to.

After setting the print enable bit (line printer
CSR bit (0)), the software should wait at
least 500 us before reading the looped back
data. It should also wait 500 us between
subsequent reads. If the register is read
sooner, it may contain zeros until the character is loaded in by microcode.
This bit is read/write and cleared by a
Master Reset or INIT.

(6)

Interrupt

Enable

If the interrupt enable bit is set, interrupt
requests are posted when the error bit (line
printer CSR bit (15)) or the print done bit (line
printer CSR bit (7)) becomes set.

The interrupt enable bit is read/write, and is
cleared by a Master Reset or an INIT.

103

104

PROGRAMMING

Table 4-33

Line Printer Control Status Register Functions (Cont)

Bits

Title

Function

(7)

Print Done

If the format control field contains 0, the
print done bit (line printer CSR bit (7)) is set
after the DMA transfer is complete and all
characters are transferred to the line printer.
If the format control field contains 1, the
print done bit (line printer CSR bit (7)) is set
after the DMA transfer is complete and all
characters, including extra formatting characters (suffix characters), are transferred to
the line printer.

Setting bit (7) causes an interrupt request to
be posted, if the interrupt enable bit (line
printer CSR bit (6)) is set. Bit (7) is set when
bit (15) (DMA error) is set.
The print done bit is read-only, and is
cleared by setting the print enable bit. It is
set by either a Master Reset or by an INIT.

(10:8)

indirect
Address Field

Bits (10:8) point to one of eight word registers. After an access (read or write) to an

indirect register, the indirect address field is
automatically incremented by one. When the
print done bit (line printer CSR bit (7)) or
error bit (line printer CSR bit (15)) is set, the
indirect address
cleared to zero.

field

automatically

This automatic increment feature may be

used in the following way. After an interrupt
is posted due to the print done bit (line printer CSR bit (7)) becoming set, the program
reads the line printer CSR register. The program finds, for example, that the print done
bit is set and the error bit is clear. The program reads from address Base + 16. Since
the indirect register address field points to
zero, the first three words should be read to
get the status of the previous DMA transfer.
The program now sets up parameters for
the next DMA transfer. This is done by writing a word of prefix information to the
address Base + 16, then writing again with a
word of suffix information. The next word
loaded contains the DMA buffer address,

and the word loaded after that is the DMA
character count. Assuming that the other
indirect registers already contain valid data,
the program sets the print enable bit to initiate printing.

The indirect register address field is
read/write and cleared by a Master Reset or
an INIT. Table 4-34 lists the line printer indirect registers.

rrrrr

PROGRAMMING

105

Table 4-33 Line Printer Control Status Regism Functions (Cont)
| |

Bits

Title

- Function

(11)

Unused Bit

This bit is always read as a zero.

(12)

Connect Verify

This read-only bit indicates the connect status of the line printer to the DMF32. A

ground reference line is connected to the

J—

ground through the line printer. If this bit is
clear, the line printer is connected to the
DMF32 distribution panel. If this bit is set,

the line printer is not connected.

(13)

DAVFU Ready

This bit reflects the state of the DAVFU

(14)

Line Printer
Error

This bit reflects the state of the OFFLINE
signal from the line printer. When this bit is

ready line from the line printer. This bit is not
affected by a Master Reset or an INIT.

set, the line printer is offline. The zero to one
transition of this bit posts an interrupt if the
interrupt enable bit (line printer CSR bit (6))
is set.

~ This bit is read-only.

(15)

DMA Error

This bit is set if the DMF32 UNIBUS control-

ler either did not receive SSYN at least 32 us

after issuing a MSYN, or the controller could
not become bus master for at least 32 us
after having asserted BUS NPR.

This bit is read-only and is cleared by a

Master Reset, or INIT, or writing a 1 to the
print enable bit.

4.13 LINE PRINTER INDIRECT REGISTERS
The line printer controller uses eight read/write indirect registers. These registers are addressed by the line printer CSR bits (10:8). Read/modify/write
UNIBUS cycles are not allowed to the indirect registers. Table 4-34 describes
the functions of the line printer indirect registers. Figure 4-27 shows the bit
configuration of indirect register [6].

106

PROGRAMMING

Table 4-34
Register/Bits
Indirect Register [0]

Bits (15:0)

Line Printer Indirect Registers Functions
Title

Function

Bytes

This register contains the num-

Transmitted

ber of bytes transferred from the
line printer controller to the line
printer. If format control (line

printer CSR bit (2) equals one,
the prefix characters, formatted
data, and suffix characters are
included in the count. When the
format control (line printer CSR

bit (2)) equals zero, the bytes
transmitted (indirect register [0]

bits (15:0)) indicate the actual
number

characters

direct

memory accessed.

If the print done bit is set, writing
a 1 to the print enable bit clears
the bytes transmitted register
(indirect register [0] bits (15:0)).

Indirect Register [1]

Line Count

Bits (15:0)

Line count register bits {(15:0) is
used only if DAVFU is clear.

This register contains a count of
the number of lines the paper on
the line printer has moved from
printing the latest buffer.

If print done bit is set, writing a 1
to the print enable bit clears this
register.
Indirect Register [2]

Bits (15:8)

Prefix

Character

Indirect register [2] bits (15:8) is
loaded with the type of prefix

character to be inserted at the
beginning of the buffer.
A zero value for this prefix character is interpreted as a ‘“‘new
line” command. A ‘“new line”
command is a carriage return followed by a line feed that is sent
to the line printer. The carriage
return

precedes the line

feed

only if the automatic carriage
insert bit (indirect register [6] bit
(8)) is not active, that is, equal to
one. If the prefix character count
(indirect register [2] bits (7:0))
equals zero, then no prefix characters are sent.

Indirect Register [2]

Bits (7:0)

- Prefix

Character
Count

The prefix character count regis-

ter (indirect register [2] bits (7:0))
is loaded with the number of prefix characters to be inserted at
the beginning of the buffer.

DI,

PROGRAMMING

Table 4-34

| Register/Bits

lndirectyflagismr [3]
Bits (15:8)

Line Printer Indirect Registers Functions (Cont)
Title

Function

Suffix
Character

Indirect register [3] bits (15:8) is
loaded with the type of suffix
character to be appended at the
end of the buffer.
A zero value for this suffix character is interpreted as a ‘‘new
line” command. A “new line”
command is a carriage return followed by a line feed that is sent
to the line printer. The carriage
return precedes the line feed
only if the automatic carriage
insert bit (indirect register [6] bit

(8)) is not active, that is, equal to
one. If the suffix character count
(indirect register [3] bits (7:0))
equals zero, then no suffix characters are sent.

Indirect Register [3]

Bits (7:0)

Indirect Register [4]

Bits (15:0)

Suffix
Character
Count

DMA Buffer
Address

The suffix character count regis-

ter (indirect register [3] bits (7:0))

is loaded with the number of suffix characters to be appended at
the end of the buffer.
This register contains the low-

order bits of the UNIBUS DM
buffer address. The two highorder bits reside in the indirect

Indirect Register [5]

Bits (15:0)

Indirect Register [6]
Bits (1:0)

DMA

16-bit DMA character count in
2's complement form.

DMA Buffer

“Indirect register [6] bits (1:0) are

Address (two
most signifi-

cant bits)

Indirect Register [6]

Unused Bits

Indirect Register [6]
Bit (8)

Automatic

Bits (7:2)

This register is loaded with the

Character
Count

Carriage

loaded with the two most significant bits of the UNIBUS DMA
buffer address.

If the format control (line printer

CSR bit (2)) equals one, and the
automatic carriage insert bit is
clear, the line printer automatically inserts a carriage return
before a line feed or form feed.
Carriage returns in the data
stream preceding a line feed or
form feed are stripped out if
automatic carriage insert bit is
active.

108

PROGRAMMING

Table 4-34

Line Printer Indirect Registers Functions (Cont)
S,

‘Register/Bits

Title

Function

Indirect Register [6]

Form Feed/
Line Feed
Convert

If format control (line printer CSR
bit (2)) equals one, and the form

Bit (9)

feed/line feed convert is clear, a

form feed is translated into multiple line feeds
to reach the next
top of form.
Indirect Register [6]
Bit (10)

Nonprintable
Character
Accept

If format control (line printer CSR
bit (2)) equals one, this bit specifies that nonprintable, non control characters are sent to the
line printer, assuming that such a

ARy,

character causes a space to be
printed.
Characters with the
MSB set are considered nonprintable characters. If this bit is set,
all characters with the MSB set
are transferred to the line printer,
regardless of the setting of
DAVFU bit.
If format control (line printer CSR

bit (2)) equals one and this bit is

clear, then the DMF32 discards
nonprintable characters.
Oy

Indirect Register [6]
Bit (11)

Direct Access
Vertical Format

The program sets this bit if the
line printer is a DAVFU.

Unit (DAVFU)
When DAVFU bit is set, special
vertical format control codes are
allowed to be direct memory
accessed to the line printer.

Indirect Register [6]
Bit (12)

Line
Wrap

If format control (line printer CSR
bit (2)) equals one and this bit is
set, a carriage return and line
feed are inserted into the charac-

ter stream prior to the current
character if the horizontal position of the current character is

past the value stored in the line

printer carriage width (indirect

automatic carriage insert bit is
set, only the line feed is sent to
the printer.

PROGRAMMING

109

Table 4-34 Line Printer Indirect Registers Functiona (Cont)
Register/Bits

Title

Function

Indirect Register [6]

Line
Truncation

If this bit is set, line truncation is inhibited. Version 28 of the microcode

Bit (3)

is required.

Indirect Register [6]

Tab
Expansion

If this bit is set, tab
expansion is inhibited.
the
of
27
Version
microcode is required.

Indirect Register [6]

Lower Case
to Upper
Case Convert

If format control (line
printer CSR bit (2)) equals
one and the lower case to
upper case conversion bit
is clear, this specifies

Bit (14)

Bit (15)

lower case character to
upper case character
conversion.

If format control (line
printer CSR bit (2)) equals
one, and the DAVFU bit is
clear, then the indirect
register [7] bits (7:0) (lines
per page) is loaded with
the number of lines on a
page for the attached line

Lines Per

Indirect Register [7]
Bits (7:0)

Page

printer.

Line Printer

Indirect Register [7]
Bits (15:8)

Carriage Width

If format control (line
printer CSR bit (2)) equals
one, the line carriage
width (indirect register [7]
bits (15:8)) is loaded with
the width of the carriage
of the attached line
printer.

UNUSED
BITS

LOWER CASE
TO UPPER CASE
CONVERT

UNUSED BITS

LINE WRAP NON

AUTO
PRINTABLE | CARRIAGE
CHARACTER| RETURN

ACCEPT
DIRE CT

ACCESS
VERTICAL

MSB OF DMA

BUFFER ADDRESS

INSERT
FORM
FEED-LINE
FEED CONVERT

FORMAT UNIT
TK-B6S9

Figure 4-27

Line Printer Indirect Registers [6]

DY,

110

PROGRAMMING

4.14

PARALLEL INTERFACE (DR)

The parallel interface (DR) is not only functionally a DR-11-C, but also supports

silo data transfers or double buffered DMA transfers in one direction. The parallel interface can operate in three modes: DR-11-C functional mode, silo mode
and DMA mode. When the device is not in the DR-11-C mode, an enhanced
transfer protocol is emulated. This enhanced transfer protocol causes a trans-

fer or interrupt request to occur whenever a zero-to-one or a one-to-zero transition of either User Request A or User Request B line occurs.
4.14.1

DR-11-C Functional Mode

In this mode, the program reads the parallel interface input buffer to read data

from the user device. After the data has been read, the DMF32 pulses the Data
Transmitted line to inform the user device that the data has been read and that
the data hold time has been satisfied. The parallel interface buffer bits (15:0)

reflect the state of the 16 input line wires at the time the parallel interface input

buffer bits (15:0) are read.
The program writes to the parallel interface output buffer bits (15:0) to write

data to the user device. The 16 output lines to the user device reflect the state of
the parallel interface output buffer bits (15:0). After the program writes to the
parallel interface buffer, the DMF32 pulses the New Data Ready line.

4.14.1.1

DR-11-C User Request A and B - The user device controls both the
User Request A and B lines. User Request A is reflected in the parallel interface

CSR bit (7); User Request B line is reflected in the parallel interface CSR bit(15).
When the Interrupt Enable A bit (parallel interface CSR bit (6)) is set, a zero-to-

one transition of User Request A line causes an interrupt request to Vector A.

Similarly, if the Interrupt Enable B bit is set, a zero-to-one transition of User
Request B causes an interrupt request to vector B.

4.14.2

Silo Mode
~
In silo mode, the 32-word silo can be used as either a transmit silo or as a

receive silo, depending on the mode selected. Both User Request A and B lines

are activated by either a zero-to-one or one-to-zero transition. One of the user
request lines must be dedicated to operate as a transfer request line so that the

NSO

user device can access the silo without program intervention.
4.14.2.1

Writing To and Reading From Silo - If the silo is being used for
receive, the program reads the silo via the parallel interface input buffer. Each

read of the parallel interface input buffer causes the silo entries to shift down by |
one word. However, if the silo is being used for transmit, the program loads a

data word into the silo by writing to the parallel interface output buffer. The contents of the silo (either transmit or receive) can be flushed by the program writing a one to the flush buffer bit (parallel interface bit (11)).
4.14.2.2

Silo Request A and B - The following explanation assumes that the

User Request A is programmed for use as the transfer request line, and the silo
is used to receive words (mode
= 0111).

PROGRAMMING

111

After the user device changes the state of the User Request A line, the parallel

interface reads the data, pulses the Data Transmitted signal, and loads the data

word into the silo. After a word is loaded into the silo, the parallel interface sets

Request A (parallel interface CSR bit (7)).
If the Interrupt Enable A bit (parallel interface CSR bit (6)) is set when Request A
changes state, an interrupt request is posted for vector A. However, the User
Request A line can be used to load up to 32 words into the silo before the interrupt service routine empties the silo. After 32 words are loaded into the silo, the

parallel interface does not accept any more characters until the program reads
from the silo. The parallel interface indicates to the user device that the silo is

full (cannot accept any more characters) by not pulsing the Data Transmitted

signal in response to User Request A line. In this example, the operation of
User Request B is the same as in DR11-C functional mode; that is, asserting

User Request B causes an interrupt request to vector B if the interrupt enable B

bit (parallel interface CSR bit (5)) is set.

4.14.3

DMA Mode

DMA mode is activated by setting the mode bits (miscellaneous register bits

(3:0)) appropriately. Either User Request A or Request B is selected for use as a
transfer request line. Both Request A and Request B are activated by a transition on the respective line. DMA operation is double buffered, so that the program has a full buffer time to respond to an interrupt.

4.14.3.1

DMA Transfer — The following explanation assumes that User
Request A is selected as the transfer line, and the DMA is a receive operation

(mode = 1011). Also the NPR primary/secondary bit (parallel interface CSR bit

(2)) is clear, indicating that the primary buffer is active.

The transition (zero-to-one or one-to-zero) of User Request A indicates to the

parallel interface that the user device wants to transfer data to memory. Next,
the parallel interface reads the data on the 16 input lines, pulses the Data
Transmitted signal, and transfers data to the on-board silo. Data in the silo is
subsequently direct memory accessed to the main memory buffer. After suc-

cessfully filling the buffer in main memory, the NPR primary/secondary bit (par-

allel interface CSR bit (2)) and the done primary bit (parallel interface CSR bit
(8)) are both set. An interrupt request is posted to vector A provided that the
Interrupt Enable A bit (parallel interface CSR bit (6)) is set.
The DMA transfers continue into the secondary buffer, unless the done secon-

dary (parallel interface CSR bit (9)) is set. If the done secondary bit is set, DMA
transfers are inhibited until the program writes to the secondary word count
register, which clears the done secondary bit.

An error condition aborts an NPR transfer. When an error occurs, the DMA
memory error (parallel interface CSR bit (13)) is set instead of the done bit.

Setting the DMA memory error bit terminates the DMA transfer. An interrupt
request is posted to vector A if the interrupt enable bit (parallel interface CSR bit

(6)) is set. DMA transfers continue after a Master Reset or INIT clears the error
bits.

PROGRAMMING

112

When receive DMA is used, the program may read the parallel interface input
buffer to read the previous word that was direct memory accessed to memory.
If transmit DMA is used, a program write to the parallel interface output buffer

causes the written data to be applied to the output lines as the next transfer to

the user device, after which DMA transmissions are resumed.

Request A bit (parallel interface CSR bit (7)) reflects the state of the User
Request A line, but does not post an interrupt request. User Request B func-

tions as a general purpose interrupt request line.

The DMA buffer address register is 17 bits long. The least significant bit is
assumed to be zero (the address is on a word boundary). The word count register specifies the number of words to be direct memory accessed.
4.14.4

Parallel Interface Device Registers

The parallel interface uses four device registers and four indirect registers. The
registers are as follows:

e Parallel interface control status register
e Qutput buffer
e Input buffer/miscellaneous register
e |ndirect registers

4.14.4.1 Parallel Interface Control Status Register - The read/write parallel
interface control status register has an address of base +18HEX.
Read/modify/write UNIBUS cycles are not allowed. This register is accessed

by word only.

The parallel interface control status register enables the following:

Interrupt enable B

Interrupt enable A

Buffer flush

Control zero line
Control one line

Master reset

This register also points to one of four indirect registers, and indicates the

Request A state
Request B state

Primary or secondary buffer in use
Primary or secondary count register in use

following:

Successful transfer to primary buffer (DMA mode)
Successful transfer to secondary buffer (DMA mode)

'DMA error

Figure 4-28 shows the bit format for the parallel interface CSR. Table 4-35

describes the functions of the parallel interface CSR.

PR,

PROGRAMMING

,
i

‘

REQUEST B

fhomm

DMA

ERROR

MASTER
RESET

FLUSH

BUFFER

UNUSED
BIT

DONE |

ADDRESS

- | REQUEST AJINTERRUPT

|SECONDARY

UNUSEDBIT

04
03
INDIRECT

DONE
PRIMARY

ENABLE B

INTERRUPT
ENABLE A

NPR

PRIMARY/

SECONDARY

CONTROL
ZERO

CONTROL
ONE
TR-BT00

Figure 4-28

113

Parallel Interface CSR

Table 4-35
Bits

Title

(0)

Control Zero

Parallel Interface Control Status
Register Functions

Function

Bit (0) controls the state of the control zero line origi-

nating from the parallel interface. When bit (0) is set,
control zero is high. When bit (0) is clear, control zero

is low. This bit can be used for any user-defined

)

function.

Bit (0) is cleared by a Master Reset or INIT.

(1)

Bit (1) controls the state of the control one line origi-

Control One

nating from the parallel interface. When bit(1) is set,

control one is high. When bit (1) is clear, control one is

low. This bit may be used for any user-defined
function.

Bit (1) is cleared by a Master Reset or INIT.
(2)

NPR Primary/

Bit (2) indicates which of the buffer address registers

Secondary

(primary or secondary) and word count registers (primary word count or secondary word count) are being

used or are to be used. A zero indicates that the primary registers are active; a one indicates that the secondary registers are active. After a buffer (primary or

o
s

secondary) has successfully or unsuccessfully been
filled with data via DMA, NPR primary/secondary bit
changes state, and thus points to the other buffer.
When NPR primary/secondary bit changes state, the
appropriate done bit or error bit is set, and an interrupt request is posted.

If User Request A requests a DMA transfer (MODE =
'1001 or '1011), then the interrupt is posted to Vector

A, provided that interrupt enable A bit (DR CSR bit (6))

(MODE = '1010 or '1000), then the interrupt is posted

is set. If User Request B requests a DMA transfer

to Vector B, if interrupt enable B bit (DR CSR bit (5)) is

set. After NPR primary/secondary bit changes state,
data is direct memory accessed to the new buffer provided that the new buffer’s done bit is not set. If the

new buffer’s done bit is set, then DMA is inhibited until
the done bit is cleared.

114

PROGRAMMING

Table 4-35 Parallel Interface Control Status
Register Functions (Cont)

Bits

Title

Function
AR

An error condition (DMA memory error being set)
aborts the NPR transfer and causes an interrupt
request to be posted. This interrupt request is posted
to the same vector that would have been chosen had
the buffer been filled successfully. After an error condition, operation continues only after the error bits are
cleared, either by a Master Reset or INIT.
NPR primary/secondary bit is read-only,
cleared by a Master Reset or INIT.

and

is
s

(4:3)

Indirect
Register
Address

Bits (4:3) point to one of four indirect registers.
The indirect register address is read/write, and is
cleared by a Master Reset or INIT.
m——

(5)

Interrupt

When set, bit (5) enables interrupt request to vector B.

Enable B

Bit (5) is read/write, and is cleared by a Master Reset
or INIT.
g

(6)

Interrupt
Enable A

When set, bit (6) enables interrupt requests to vector
|

Bit (6) is read/write, and is cleared by a Master Reset
or INIT.

v
O,

(7)

Request A

The state of bit (7) follows that of the input signal
USER REQUEST A. In DR11-C functional mode
(Mode (3:0) = '0000), the zero to one transition of user
REQUEST A causes an interrupt request to be posted
to Vector A if the Interrupt Enable A bit is set.
In silo mode with the User Request A line requesting a
data transfer (miscellaneous register bits (3:0) equals
either 0101 or 0111), any transition (zero-to-one or
one-to-zero) causes either data to enter the silo from
the user device (receive) or leave the silo to be transferred to the user device (transmit). After the data has

entered or left the silo, an interrupt request is posted
to Vector A provided that the interrupt enable A bit is
set.
|
The receive buffer cannot overflow; after 32 words
are entered into the silo, the DMF32 will not accept
any more characters until the program reads from the
silo to provide room for more characters. The DMF32
informs the user device that it will not accept any more
characters by not pulsing the Data Transmitted line in
response to the User Request line, thus not completing the handshaking protocol. Also, the silo- cannot
underrun in SILO transmit mode. If the silo is empty
and the user device requests new data by changing
the state of the User Request line, the DMF32 does
not apply new data to the output lines or pulse the
New Data Ready signals until the program has
entered new data into the silo.

PROGRAMMING

Table 4-35

Parallel Interface Control Status

Bits

Title

Function

In DMA mode (receive or transmit), if User Request A

requests a data transfer (Mode (3:0) = '1001 or '1011),
the zero-to-one or one-to-zero transition of Request A
does not cause an interrupt request to be posted, but
is used by the user device to transfer data.

(8)

Done Primary

Bit (8) is used only in DMA mode. This bit is set if a
DMA transfer to or from the primary buffer has completed successfully. If a DMA transfer aborts due to
an error condition, the DMA error bit is set instead of
the done primary bit.

Bit (8) is read-only, and is cleared by writing to the pri-

mary word count register. It is set by a Master Reset
or an INIT.

(9)

Done
Secondary

Bit (9) is used only in DMA mode. This bit is set if a
DMA transfer to or from the secondary buffer has
completed successfully. If a DMA transfer aborts due
to an error condition, the DMA error bit is set instead
of the done secondary bit.
This bit is read-only, and is cleared by writing to the
secondary word count register. It is set by a Master
Reset or an INIT.

(10)

Unused Bit

(11)

Flush Buffer

Bit (11) is used only in silo mode. Writing a one to the
flush buffer causes the contents of the buffer to be
invalidated.

This bit is cleared by either a Master Reset or INIT.

(12)

Unused Bit

(13)

DMA Error

This bit is used only in DMA mode. It is set when the

DMF32 UNIBUS controller did not receive a BUS
SSYN at least 32 us after issuing a BUS MSYN. Setting the DMA error bit causes an interrupt to Vector A
or B, depending on whether User Request A or User
Request B is used to request the data transfer,
respectively. The respective interrupt bit must be set

to post an interrupt request.

This bit is read-only, and can only be cleared by a

Master Reset or INIT.

(14)

Master Reset

When the program sets this bit, a Master Reset is initiated. This bit remains set while the reset is in progress and clears automatically after the reset is
completed.

While the Master Reset is occurring, the program

should not access the DMF32 parallel interface device
registers, except for the parallel interface CSR. The

program may write a one to the Master Reset bit
while a reset is occurring, but such action is ignored.
The Master Reset bit is high when the reset is occurring. A Master Reset initializes various CSR bits as
specified in the bit descriptions.

115

116

PROGRAMMING

Table 4-35

Parallel Interface Control Status Register Functions (Cont)

Bits

Title

Function

(15)

Request B

The state of bit (15) follows the state of the input sig-

nal user Request B. In DR11-C functional mode
(Mode (3:0) = ’'0000), the zero-to-one transition
causes an interrupt request to be posted to Vector B
provided that Interrupt Enable B bit (parallel interface
CSR bit (5)) is set.

In SILO mode, with the User Request B line requesting a data transfer (miscellaneous register bits (3:0)
equals either 0110 or 0100), any transition (zero-to-

one or one-to-zero) causes either data to enter the
silo from the user device (receive) or leave the silo to
be transferred to the user device (transmit). After the
data has entered or left the silo, an interrupt requestis
posted to Vector B provided that the interrupt enable

B bit is set.

The miscellaneous register has an address of base

+1C. This write-only register is accessed by word
only.

When in DMA mode (receive or transmit), if User
Request B requests a data transfer (Mode (3:0) =

1010 or "1000), the zero-to-one or one-to-zero transition of Request B does not cause an interrupt request
to be posted, but is used by the user device to transfer data.

4.14.4.2

Parallel Interface Output Buffer — The parallel interface output buffer
has an address of base +1A. Read/modify/write UNIBUS cycles are not
allowed. In the DR11-C functional mode, this register can be accessed by either

high or low byte. In DMA and silo modes, this register is accessed by word only.
S

In DR11-C functionality mode, silo receive mode, or DMA receive mode, the
program uses this register to output data onto the 16 output lines. In functionality mode, this register may be accessed by a high or low byte. If only the high

byte is accessed, the clock signals NEW DATA READY and NEW DATA READY
HIGH are pulsed for one microsecond after the data has been put on the output
lines. If only the low byte is written to, NEW DATA READY and NEW DATA

READY LOW are pulsed for one microsecond after the data has been put on the
output lines. If this register is written to as a word, NEW DATA READY, NEW

RO,

DATA READY HIGH, and NEW DATA READY LOW are all pulsed for one micro-

second after the data has been put on the output lines.
s

In SILO transmit mode, the program uses this register to enter data into the

32-word silo one word at a time. The silo word count register may be accessed
to determine the number of words in the silo. In SILO transmit mode, this register must be accessed as a word, entering two bytes into the silo at a time. When
the device asserts the user request line to get a word from the silo, the DMF32

pulses NEW DATA READY, NEW DATA READY HIGH, and NEW DATA READY

LOW for one microsecond after the data has been put onto the output lines.

PROGRAMMING

117

In DMA transmit mode, the program uses this register to insert a word onto the
output lines between DMA transfers. The program inserting a word onto the
output lines between words that have been direct memory accessed is transparent to the user device. It is transparent because the user device does its normal handshake protocol to obtain the data regardless of whether the data has
been direct memory accessed from main memory or inserted between direct
memory accesses by the program writing to this register. The normal handshake protocol is used when the user device toggles the request line, then the
DMF32 applies the data onto the lines and pulses the New Data Ready lines.
The parallel interface output buffer is cleared by either a Master Reset or INIT.
4.14.4.3

Parallel Interface Input Buffer

The parallel interface input buffer has an address of base +1C. This register is
read-only.

In either DR11-C functionality mode, SILO transmit mode, or DMA transmit
mode, this register reflects the state of the 16 input lines from-the user device.

The user data should be stable on the input lines before the program reads the

parallel interface input buffer. After the program reads the parallel interface
input buffer, the DMF32 pulses the Data Transmitted line to inform the user
device that the data has been read.

In SILO receive mode, this register is used to access the receive silo. Reading
the parallel interface input buffer causes the silo entries to shift down by one
word position. The word count register should be read to determine the number
of entries remaining in the silo.

In DMA receive mode, this register contains the previous word direct memory
accessed to main memory.

A Master Reset or INIT clears the parallel interface input buffer bits (15:0).
4.14.4.4 Miscellaneous Register — The miscellaneous register has an address
of base +1C. This write-only register is accessed by word only.
The miscellaneous register indicates the following:
e Specific mode of operation

e Most significant UNIBUS primary buffer address bit (DMA)
e Most significant UNIBUS secondary buffer address bit (DMA)

The miscellaneous register is cleared by a Master Reset or INIT.

Figure 4-29 shows the bit format for the miscellaneous register. Table 4-36

describes the functions for the miscellaneous register.

118

PROGRAMMING

04
UNUSED BITS

DR OPERATING MODE

L—SECONDARY BUFFER ADDRESS MSB
PRIMARY BUFFER ADDRESS MSB
A

TR-E701

Figure 4-29

Miscellaneous Register

Table 4-36

Parallel Interface Miscellaneous Register Functions

Bits

Title

Function

(3:0)

DR Operating
Mode

Bits (3:0) contain the parallel interface operating mode. The program should write the
desired DMF32 parallel interface operating
mode to the miscellaneous

(3:0). A write to the miscellaneous register

should be preceded by a Master Reset if the
operating mode specified in the miscellaneous register bits (3:0) is being changed.
After a Master Reset or INIT, the parallel
interface is initialized to the DR11-C functional mode (Table 4-37 lists the modes).

(13:4)

Unused Bits

(14)

Secondary
Buffer

”
Bit (14) is the most significant UNIBUS secondary buffer address bit, used in the DMA

Address MSB

(15)

JRE—

mode.

Primary
Buffer
Address MSB

Bit (15) is the most significant UNIBUS primary buffer address bit, used in the DMA
mode.
S,

Table 4-37

Bits

Parallel Interface Operating Modes

(3:0)

Mode

0000

DR11-C functional mode

0101

Siloftransmit, User Request A requests data transfer

0100

Silo transmit, User Request B requests data transfer

0111

Silo receive, User Request A requests data transfer

0110

Silo receive, User Request B requests data transfer

1001

DMA transmit, User Request A requests data transfer

1000

DMA transmit, User Request B requests data transfer

1011

DMA receive, User Request A requests data transfer

1010

DMA receive, User Request B requests data transfer

———
e

PROGRAMMING

119

4.14.5

registers have an address of base +18 HEX. Read/modify/write UNIBUS

Parallel Interface Indirect Registers - The parallel interface indirect

cycles are not allowed. This register is accessed by word only.
—

The parallel

interface uses four indirect registers. These registers are

addressed by the parallel interface CSR bits (4:3). Table 4-38 describes the
o

functions for the parallel interface indirect registers.

Table 4-38

Parallel Interface Indirect Registers Functions

indirect
-

Indirect Register [0]

Bits (15:0)
-

Title

Function

Primary

This read/write register stores the pri-

-Buffer

mary

Address
Register

address) of the transmit or receive
buffer for DMA transfers. The most
significant UNIBUS address bit (the
seventeenth bit counting from zero) is
the primary buffer address bit (17)
(miscellaneous register bit (15)). Bits
(16:1) are stored in the primary buffer
address register. -Since only wordaligned transfers are permitted, the
least significant UNIBUS address bit is
assumed to be zero.

|
—

buffer

address

(UNIBUS

The primary buffer address register is
-

cleared by a Master Reset or INIT.

Indirect Register [1]

Bits (15:0)

Primary
Word Count

In DMA mode, this read/write register
is loaded with the primary buffer size

in words (receive or transmit). Writing

to this register clears the done prima-

ry bit (parallel interface CSR bit (8)).

~In silo mode, (transmit or receive), this
read/write register contains the num-

ber of word entries in the silo.
o

This register is cleared by a Master
Reset or INIT.

ARG

120

PROGRAMMING

Table 4-38 Parallel Interface Indirect Registers Functions (Cont)
Indirect

Title

Function

Indirect Register [2]
Bits (15:0)

Secondary
Buffer

This read/write register stores the
secondary buffer address (UNIBUS

Address

address) of the transmit or receive
buffer for DMA transfers. The most
significant UNIBUS address bit (the
seventeenth bit counting from zero) is
secondary buffer address bit (17)
(miscellaneous register bit (14)). Bits
(16:1) are stored in the secondary
buffer address register. Since only
word-aligned transfers are permitted,
the least significant UNIBUS address
bit is assumed to be zero.

The secondary buffer address register
is cleared by a Master Reset or INIT.

Indirect Register [3]
Bits (15:0)

Secondary
Word Count

[

In DMA mode, this read/write register
is loaded with the secondary buffer

size in words (receive or transmit).
Writing to this register clears the done

secondary bit (parallel interface CSR
bit (9)).
This register is cleared by a Master
Reset or INIT.

4.15

DIFFERENCES BETWEEN DMF32 AND THE DR11-C

The DMF32 parallel interface is a microcoded implementation; the DR11-C is a
hardwired implementation. These two devices are functionally similar, but are

not identical. Different implementations result in different signal timings, different register access times, and different data transfer rates. The bandwidth of
the DMF32 parallel interface depends upon many factors, such as latency time
and the extent to which other devices on the DMF32 (synchronous interface
and asynchronous multiplexer) are used. The more other devices are used, the

less the bandwidth of the parallel interface.

PROGRAMMING

121

The following list specifies the major differences between the DMF32 running in
-

the DR11-C functional mode and the DR11-C.

1. DMF32: The timing of NEW DATA READY, NEW DATA READY HIGH,

—

NEW DATA READY LOW, and DATA TRANSMITTED signals are fixed.

These signals are fixed as one microsecond active high pulses. The width

of these pulses CANNOT be changed. If a longer pulse is required, then

the user’s device needs to contain the appropriate circuitry to change the
g

characteristics of the signal.

A monostable multivibrator may be used to

lengthen the pulse.
DR11-C: The timing of these signals may be varied by changing a capaci-

tor on the DR11-C module.

2. The DMF32 uses bits in the control and status registers that are not used

by the DR11-C. These bits must not be set by software when running in

DR11-C functional mode.

3. DMF32: Read/modify/write UNIBUS cycles to any of the parallel interface

control and status registers are not permitted. These cycles are not per-

mitted because there is no interlock by the DMF32 in between the read
-

and write part of the cycle. This means that macro instructions such as

“bit set’” and ‘‘bit test’”” are not permitted. Move instructions are

recommended.

DR11-C: Can

registers.

perform

read/modify/write

UNIBUS cycles to some

4. DMF32: Data out byte (DATOB) UNIBUS cycles should not be used to

write to a control and status register in any mode, except for the output

—

buffer when in the DR11-C functional mode. Except for the above noted
special case, the DMF32 treats a DATOB cycle as DATO cycle and ignores

—

the least significant UNIBUS address bit.

DR11-C: No restrictions.

5. The DMF32 and DR11-C have the same electrical signals that interface to
the user device, but the CONNECTORS AND CONNECTOR PINOUTS

ARE DIFFERENT. The DMF32 distribution panel has two 37 pin D type

to the user device.

connectors to which the user can connect user supplied cables to connect

6. The DMF32 and DR11-C both have TTL compatible logic for the interfacing signals. However, these devices use DIFFERENT types of drivers and
receivers. Table 4-39 lists the drivers and receivers that the DMF32 uses.

4.16

DMF32 DRIVERS AND RECEIVERS

Table 4-39 lists the DMF32 drivers/receivers and associated signals. Figure 430 shows the drivers and receivers.

122

PROGRAMMING

Table 4-39

DMF32 Drivers/Receivers and Associated Signals

Driver/Receiver

Associated Signals

7437 driver with 1 kohm
pullup resistor to +5
volts on output

New Data Ready
New Data Ready High
New Data Ready Low
Data Transmitted
INIT

| 745240 driver with 1 kohm
pullup resistor to +5 volts

Sixteen data output lines
S

on output

74L.5240 driver with 1 kohm
pullup resistor to +5 volts

Control Zero
Control One

on output

74L.S240 receiver with 1 kohm
pullup resistor to +5 volts
on pullup

Sixteen data input lines
User Request A
User Request B

+5V

? 1K OHM

7437 DRIVER

+oV

?H{ OHM
S

745240 DRIVER

+5V

7415240 DRIVER

+5V

7415240

RECEIVER
THH242

Figure 4-30

DMF32 Drivers and Receivers

Synchronous
25-Pin Cinch Connector

USRT CTS H; (CCITT 106)
USRT CAR H; (CCITT 109)

USRT DTR H; (CCITT 108.2)

USRT DSR H; (CCITT 107)
USRT RI H; (CCITT 125)
USRT DSRS H; (CCITT 111)

SIGNAL GROUND

24
o

> i

sw2

B Q)
N

USRT RTS H; (CCITT 105)

RX D H; (CCITT 104)

LW!E

TX D H; (CCITT 103)

CONNECTOR

N O03

DCE TX CLK H; (CCITT 114)

{112)

]
LI

DCE RX CLK H; (CCITT 115)

DTE TX CLK H; (CCITT 113)

' SW3

SINGLE LINE

O~ ORNONQOQONQEQU Q0w ON 057 0TI QR OF 0

USER TX H

H3248

25 PIN CINCH

TK-BE88

Figure A-1

Synchronous 25 Pin Cinch Connector

ORI

AN,

SIS

Asynchronous
25-Pin Cinch Connector

H3248

25 PIN CINCH

e e

CONNECTOR

RX D H; (CCITT 104)

RTS H: (CCITT 105)
|

CTS H; (CCITT 106)

CAR H; (CCITT 109)

S.CAR H; (CCITT 122)
S.RTS H: (CCITT 120)

USER TX H

CONNECTOR

‘

3
16

| oo !|

O5i

SW8O !

P
|

e
swi

‘

SW6

O’/R

l ;

SW3

fflg

ffi;

j\f’fi

L®

ff%

USER RX H

LOOPBACK

(J4 OR J5)

l SW1 OR SW2

TX D H; (CCITT 103)

SINGLE LINE

]

‘
19

‘

LTM

12
)

SW8

DSR H: (CCITT 107)
-

RI H; (CCITT 125)

DSRS H: (CCITT 111)

SIGNAL GROUND

DTR H; (CCITT 108)

o
TK-8587

Figure B-1

Asynchronous 25 Pin Cinch Connector

Parallel Interface/Line
Printer Signals
Table C-1

Parallel Interface/Line Printer Signals

Signal Name
Number

Connector/Pin

J3 TX DR/LP{0) L (printer data (1))
J3 TX DR/LP(1) L (printer data (2))
J3 TX DR/LP(2) L (printer data (3))
J3 TX DR/LP(3) L (printer data (4))
J3 TX DR/LP{4) L (printer data (5))
J3 TX DR/LP(5) L (printer data (6))
J3 TX DR/LP(6) L (printer data (7))
J3 TX DR/LP(7) L (printer data (8))
J3 TX DR/LP(8) L (printer spare)

J14-26
J14-20
J14-22
J14-1
J14-24
J14-23
J14-5
J14-6
J14-3
J14-21
J14-25
J14-7
J14-36
J14-2
J14-37
J14-8
J14-13
J14-10
J14-9
J14-4
J13-22
J13-13
J13-20
J13-9/J14-12
J13-1
J13-21
J13-4
J13-2
J13-6
J13-3
J13-16/J14-18
J13-14/J14-17
J13-8
J13-18/J14-14
J13-10
J13-11
J13-5/J14-11
J13-17/J14-19
J13-7
J13-19/J14-15
J14-16

J3 TX DR/LP(9) L (printer spare)
J3 TX DR/LP{10) L (printer spare)
J3 TX DR/LP(11) L (printer spare)
J3 TX DR/LP(12) L (printer spare)
J3 TX DR/LP(13) L (printer spare)
J3 TX DR/LP{14) L (printer spare)
J3 TX DR/LP{15) H (printer strobe)
J3 RX DR REQ A H
J3TX DR N.D.R.LOH
J3 TX DR N.D.R. HI H
J3TXDR N.D.R. H
J3TX DR REQBH
J3 TX DR DATA XMTD H
J3 RX DR/LP(15) H
J3 RX DR/LP(14) H (printer on-line)
J3 RX DR/LP{13) H
J3 RX DR/LP(12) H
J3 RX DR/LP(11) H
J3 RX DR/LP(10) H
J3 RX DR/LP(9) H
J3 RX DR/LP(8) H
J3 RX DR/LP(7)H (printer demand)
J3 RX DR/LP(6) H (printer DAVFU RDY)
J3 RX DR/LP(5) H
J3 RX DR/LP(4) H (printer conn VFY)
J3 RX DR/LP{3) H
J3 RX DR/LP{2) H
J3 RX DR/LP(1) H (printer spare)
J3 RX DR/LP(0) H (printer spare)
J2 TX DR CTRL ZERO L
J2TXDRINITL
J2 TX DR CTRL ONE L

Note: Signal returns for J13 are on pins 12, 15, and 23 through 37. Signal returns for

J14 are on pins 27 through 35.

ARG

SRR

—

oS,

DMF32 Option Designations

INTRODUCTION

D.1

This appendix lists the option variations and cabinet kits available for the
DMF32 Multi-Function Communication Interface. The method for assigning
DMF32 option designations is also described.

The communications option designations enable DIGITAL customers to obtain
communication options that are tailored to their particular needs. FCC regulations require that all system cabinets manufactured after October 1, 1983 and
intended for use in the United States, be designed to limit electromagnetic

interference (EMI). Since both shielded and unshielded cabinets currently exist
in the field, DIGITAL provides separate communication options for each cabinet type.

D.2

OPTION DESIGNATION CONVERSION

Most older DMF32 configurations are discontinued or changed to MAINTENANCE ONLY status. Therefore, the new option designations must be specified to obtain the necessary equipment. Table D-1 can be used to determine
which communication option designations are necessary when designing or
expanding upon a computer system.

Communication options may be ordered by customers either at the time a
system is purchased (a factory-installed system option) or as an upgrade to an
existing system (a field upgrade).
Table D-1

Option Compatibility Cross Reference

Old Option

Equivalent New Option

Field Upgrade

System Option

Base Option

Cabinet Kit

DMF32-AA

DMF32-M

CK-DMF32-L(*)1

DMF32-LP2

DMF32-AB

DMF32-M

CK-DMF32-L(*)

DMF32-LP

DMF32-AC

DMF32-M

CK-DMF32-LR

DMF32-LP

1 The last character of the cabinet kit (*) varies depending on which kit is required
(refer to Table D-3).

2 The last character of the system option designation is always “P’". This specifies that the option is to be factory installed.

130

DMF32 OPTION DESIGNATIONS

D.2.1

Factory-Installed System Options

A factory-installed system option is identified by a single option designation.

OGS

When this designation is specified (see Table D-1), the appropriate module(s),
cable(s), and distribution panel(s) are installed in the particular system being

constructed.

NOTE
This is an embedded action for the VAX-11/730 system and may be embedded

for the VAX-11/750 system.
R

D.2.2

Field Upgrade Options

A field upgrade is identified by two option designations. The two option designations are:
e A base option designation
e A cabinet kit designation

Refer to Table D-1 to determine which new option designation to specify when

additional replacement equipment is required.
D.2.2.1

Base Options - The base option designation specifies which compo-

nent parts make up the base option. The component parts specified are:
e The electronic module(s)
e The turnaround test connector(s)

e The option documentation

D.2.2.2

Cabinet Kits - The cabinet kit designation specifies which component

parts are included in the cabinet kit. The component parts specified are:
S5

e The internal cable(s)

e The distribution panel(s)

e An adaptor bracket (not always included) for installing the distribution

panel in a non-FCC compliant (unshielded) cabinet
NOTE
External cables needed to connect to a modem or other external device are

usually not included.
D.3

OPTION CONFIGURATION SUMMARY

This section describes the method used to assign communication option

designations.

Communication option designations ensure that the proper cable(s), distribution panel(s), and adaptor brackets (if necessary) are shipped with each base

option.

|
O

DMF32 OPTION DESIGNATIONS

131

Communication options may be obtained by customers either at the time of
system purchase (a factory-installed system option) or as an upgrade to an
existing system (a field upgrade).
The basic designations identify:

e System options (factory installed)
e Base options and cabinet kits (field upgrades)

System options are installed at the factory and are configured for the particular
cabinet in which the option is being installed.

Base options and cabinet kits are ordered as upgrades to existing systems. A

complete field upgrade option must include a base option and a cabinet kit.
NOTE

A field upgrade option alone does not make an unshielded cabinet FCC-compliant. Shielded cabinets are specially constructed to limit EMI.
D.3.1

System Option Designations

System option designations provide the following information:

DMF32-LP

THE DEVICE NAME (FOR EXAMPLE DMF32)

THE INTERFACE TYPE IDENTIFIER (TABLE D-2)
SPECIFIES FACTORY INSTALLATION

D.3.2

Base Option Designations

Base option designations provide the following information:

DMF32-M

THE DEVICE NAME (FOR EXAMPLE DMF32)
INTERFACE TYPE IDENTIFIER (TABLE D-2)

Table D-2

Electrical and Mechanical Interface Type

identifier

Interface Type

Multi-function device!

Base option - Module, documentation, and test connector

1 See Chapter 1 for detailed description of functions.

132

DMF32 OPTION DESIGNATIONS
g

D.3.3

Cabinet Kit Designations

Cabinet kit designations enable customers to obtain communication options
that are tailored to their particular cabinet(s). Cable lengths, distribution panels,
and method of installation may vary depending on the cabinet kit obtained.

Cabinet kits are individually tailored to specific cabinet types. This enables
customers to install communication options in both shielded (FCC-compliant)
and unshielded (non-FCC-compliant) cabinets.

Cabinet kits for shielded cabinets include:
e Internal cable(s)
e Distribution panel

The internal cable connects the module to the distribution panel which is

installed in a shielded 1/O bulkhead.

NOTE
Typically, cables required to connect to a modem or other external device are
not supplied with most cabinet Kits.

Cabinet kits for unshielded cabinets include:

SR,

e Internal cable(s)
e Distribution panel

e H9544-SJ adaptor bracket (may also be included)
The internal cable connects the module to the distribution panel. If the distribution panel is designed for installation in a shielded 1/O bulkhead, an H9544-SJ

adaptor bracket is included. Typically, external cables needed to connect to a
modem or other external device must be ordered separately.

Cabinet kit designations provide the following information:

SPECIFIES CABINET KIT

THE DEVICE NAME (FOR EXAMPLE DMF32)

CK-DMF32-LD

_f ! |

THE INTERFACE TYPE IDENTIFIER (TABLE D-2)

THE CABINET IDENTIFIER * (TABLE D-3)

* THE CABINET IDENTIFIER INDICATES WHICH CABLE LENGTHS ARE SUPPLIED

MY,

WITH THE CABINET KIT. IT ALSO INDICATES WHETHER AN ADAPTOR
BRACKET FOR UNSHIELDED CABINETS IS SUPPLIED.

TK-10675
GOy

DMF32 OPTION DESIGNATIONS

Table D-3

Cabinet Identifier

Component Parts Supplied

Letters Indicate

Shielded Cabinets

A 3.05 m (10 ft) internal cable with a 10.16 cm by

20.32 cm (4 in by 8 in) I/O connector panel or
distribution panel. The panel can be installed in an

H9544-SJ shielded 1/O bulkhead.

p—

—

Cabinet Kit Components

e A “2.13 m (7 ft) internal cable and I/O connector
panel or distribution panel. The panel can be
installed in an H9544-SJ shielded /O bulkhead.

Numbers Indicate

Unshielded Cabinets

o
.

w—

A 3.05 m (10 ft) internal cable and 1/O connector
panel that can be installed in an H9544-SJ or 7427292-01 adaptor bracket (depending on the

option).

NOTE

The H9544-SJ adaptor bracket has space for two 10.16 cm by 20.32 cm (4 in by 8

in) I/0O connector panels. The 74-27292-01 adaptor bracket has space for three

2.54 cm by 10.16 cm (1 in by 4 in) I/O connector panels or equivalent.

133

134

DMF32 OPTION DESIGNATIONS
SOt

D.4

DMF32 OPTION CONFIGURATIONS

Refer to Table D-4 for reference to the component parts of various DMF32
Multi-Function Communications Interface configurations.

Table D-4

DMF32 Option Configurations

SIS

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OPTION CONFIGURATIONS

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$/S/SIS/S/T/S
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FACTORY INSTALLED OPTION
e

DMF32-LP

e | x|

x|e

e | e

FIELD UPGRADE OPTION
e DMF32-M (Requires one of the | ®

e | e

following three cabinet kits)

- CK-DMF32-LD

- CK-DMF32-LE

- CK-DMF32-L1

®
e | e

Equipment supplied with option

Cables used depend on cabinet configuration.

o | o

TK-10674

AT,

135

i...-.
bl

DMF32 OPTION DESIGNATIONS

BCO6R - **CABLE

NOTE - LENGTH VARIATION (**) DEPENDS ON CABINET KIT OBTAINED
B!

TK-10670

Figure D-1

BCO6R-** Cable

@
@
@) ASYNCHRONOUS EIA

@
@
@ 0EDE2d DMF32 DIST. PANEL
60

O
SYNC PORT EIA

PARALLEL IN

LP32 OR PARALLEL OUT

DISTRIBUTION PANEL
FRONT VIEW
TK-10671

Figure D-2

DMF32 Distribution Panel

TH-10867

Figure D-3

H9544-SJ Adaptor Bracket

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Digital Equipment Corporation «Bedford, MA 01730