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Document:	DMC11 IPL Microprocessor User's Manual
Order Number:	EK-DMCMP-OP
Revision:	001
Pages:	56
Original Filename:

OCR Text

DMC11
IPL microprocessor

user’'s manual

dlifgliltiall

EK-DMCMP-OP-001

DMC11
IPL microprocessor

user's manual

digital equipment corporation - maynard, massachusetts

First Edition, September 1976

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this

manual.

Printed in US.A.

This document was set on DIGITAL’s DECset-8000
computerized typesetting system.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECtape

DECCOMM

DECUS

RSTS

DECsystem-10

DIGITAL

DECSYSTEM-20

TYPESET-8

MASSBUS

TYPESET-11

PDP

UNIBUS

CONTENTS
Page

CHAPTER 1

INTRODUCTION

CHAPTER 2

INSTALLATION

2.9

e e e e e e e e e e e e e e e e e e e e e e e e
. . . .
SCOPE
e
. . . . . . . o i i i i e et et e e
UNPACKING AND INSPECTION
. . . . e e e e e e e e e e e e e e e
OPTION DESIGNATIONS
MECHANICAL PACKAGING . . . . . . . o et ettt e e e e e e
PRE-INSTALLATIONPROCEDURES . ... .. .. .. ... ... ....
General Information . . . . . . . . . . 0 o 0 e e e e e e e e e
Preinstallation Checkout Procedures . . . . . . . . . .. ... ... ..
INSTALLATION . . . o o o e e e e e e e e e e e e e e e e e e e
. . . . . o o i e e e e e e e e e e e e e e e e
DEVICE ADDRESSES
Introduction . . . . . . o e e e e e e e e e e e e e e e e e e e e e
. . . . . . . . .. ... .. ...
Floating Device Address Assignments
e e
Device Address Selection . . . . . . . . . . . .00 e e
e e
e
e
e
e
e
e
e
e
e
.
.
.
VECTOR ADDRESSES . .
e e e
e
e
e e e e e e e e e e e e e
Introduction . . . . . . .
ee
Floating Vector Address Assignment . . . . . . . .. .. e
oo
oo 0
. . . . . . . . . .0
Vector Address Selection
e e e
e
e
et
ettt
i
o
.«
.
.
.
.
.
INSTALLATION CHECKLIST

CHAPTER 3

PROGRAMMING INFORMATION

2.1
2.2
2.3

2.4
2.5

2.5.1

2.5.2
2.6
2.7

2.7.1
2.7.2

2.7.3
2.8
2.8.1

2.8.2
2.8.3

3.1

3.2
3.3

3.4

3.4.1
3.4.2

34.2.1
3.4.2.2

3.4.2.3
34.2.4
3.4.2.5

3.4.3
3.4.4

3.4.5
3.4.6
3.4.7

3.4.8

3.4.9

3.4.10
34.11

3.4.12
3.4.13

INTRODUCTION . . . . o o o et e e e e e e e e e e e e e e e e e e e e
e e e e e e e e e e e e e e e e e
. . . . . o o o
INTERRUPT VECTORS

2-1
2-1
2-1
2-2
2-2
2-2
2-3
2-4
2-5
2-5
2-5
2-6
2-6
2-6
2-9
2-9
2-9

3-1
3-1

. . . . . o o it e e e e e e e e e e e e e e e 3-2
PRIORITY SELECTION
PDP-11 PROGRAMMING INFORMATION . .. ... .. ... .. ..... 3-2
Introduction . . . . . . . . e e e e e e e e e e e e e e e e e e e e 3-2
Unibus Control and Status Registers . . . . . . . .. ... ... .. .. 3-2
. . . . . . . . .. ... ... ...... 34
BSELO — Input Register
. . . . . . . . ... ... ... ... 3-5
Register
BSEL1 Maintenance
BSEL2 Output Register . . . . . ... ... .. ... ....... 3-6
BSEL3 Line Number/Priority Register . . . . . . . ... ... .. 3-7
Data Port Message Formats . . . . . . . .. ... .. ... .... 3-7
Input Transfers . . . . . . . . . . . .o Lo 39
o oo o 3-10
Output Transfers . . . . . . . . . . .
Initialization . . . . . . . . e e e e e e e e e e e e e e e e e e e e e 3-11
DDCMPStart Up . . . . . . . o o e e e e e e e e e e e 3-11
Data TranSmission . . . . . v & v v v v e v e e e e e e e e e e e e e 3-12
e e e e 3-12
L
. . . . . . . .«
Data Reception
. . . . . . .« « i i i i v i e e v e e e e e 3-13
Control Qut Transfers
. . . . . . . o . ot e e e e e e e e e 3-14
Maintenance MeSSages
. .. ... ... ... ... 3-14
Down Lineload
and
Detect
Remote Load
e 3-15
o i o
o
Power Fail Recovery . . . . . . . . . . .«
e e e e e e e e e e e e 3-15
Data Set Control . . . . . . . .

CONTENTS (Cont)
Page
3.5

3.5.1
3.5.2
3.5.3

3.5.4

3.5.5
3.6

3.6.1
3.6.2

3.6.3
3.6.4
3.6.5

3.6.6
3.6.7
APPENDIX A

MICROPROCESSOR CONTROL AND STATUS REGIS

TERS
. ..
...
..
. . ... ... .
OUT BUS*/IN BUS* Registers0—-7
. . . . . .. . .. .. .. .
NPR Control Register (OUT BUS*/IN BUS* 10) . . ...
........

Introduction

Microprocessor Miscellaneous Register

(OUTBUS*/INBUS* 11)

. .. ... ... ...

... .. .. .

(OUT BUS/IN BUS 0-—7)
LINEUNIT REGISTERS
. . . ... ... ...
. ... ... .. . .
In/Out Data Silo Registers (10)
. . . . ... ... .. ...
Out Control Register (11)
. . . . . . .. ... .
.. ... .. .
In Control Register (12)
. . . . . . .. ... ... ... ... ..
Modem Control Register (13)
. . . . . .. . ..
.. . ... ..
Sync Register (14)
. . . .. ... .. ... ...
... ..
Switch Selectable Registers (1Sand 16)
. . ...
. ... ... .
Maintenance Register (17)
. . . . . . ... ...
.. . .. . .
PDP-11 MEMORY ORGANIZATION AND ADDRESSING

3-15

3-15
3-17
3-17

. 3-18

3-19

3-19
3-20

. 3-21
3-22

3-23
3-24
3-24

CONVENTIONS

ILLUSTRATIONS

Title

Page

DMC11 Remote Line Unit Interface
. . . . ... ... ... .
DMC11 Local Line Unit Interface . . .. ... ... ... ..
.
Microprocessor Simplified Block Diagram . . . . ... . . ...
Microprocessor Device and Vector Address Switches
. . . . . .
Unibus Control and Status Registers
. . . . . . ... .. ...

Microprocessor Registers

. . . . . .. .. ... ...

. .

...

1-2

1-3

... .

1-5

. . . . . .

2-8

.. . .

3-3

3-16

TABLES
Table No.
2-1

2-2
2-3

24
2-5

Title

Page

Line Unit Option Designations

. . . . . .. .. . .. .. ...
. . . ... ... ... ...
.. .. .. ...
Guide for Setting Switches to Select Device Address
. . . . . .
Guide for Setting Switches to Select Vector Address
. . . . . .
Configuration of Jumpers and Switch Pack No. 1

LineUnitCables

onLineUnit

. . ... ...

..........
.. e

e e e

. .

...

2-2

. .. . . . .

2-7

.. ... .. 2-10
e e e 2-12

CHAPTER 1
INTRODUCTION

This manual provides the information necessary to install and operate the DMCI11 Microprocessor.
Specifically, it covers the DMCI11-AL and DMC11-AR Microprocessors, which have their ROMs
configured to operate under the discipline of the DDCMP protocol. It is organized into three chapters
and one appendix as follows.

Chapter 1
Chapter 2
Chapter 3
Appendix

Introduction
Installation
Device Registers and Programming Information
PDP-11 Memory Organization and Addressing Conventions

In this manual, the term DMCI11 denotes the DMCI11 Network Link, which consists of a microprocessor module and a line unit module. Explicit references to these modules may or may not be
prefixed by the term DMCI1.
The DMCI11-AR Microprocessor module is designated M8200-Y
A; the DMC11-AL Microprocessor
module is designated M§8200-YB.
Where the computers are located remotely and connected via common carrier facilities, DMC11s can
be configured to interface to synchronous modems such as Bell models 208 and 209.

The DMCI1 ensures reliable data transmission by implementing the DDCMP line protocol in firmware using a high-speed microprocessor. The DDCMP protocol detects errors on the channel inter-

connecting the systems by using a 16-bit Cyclic Redundancy Check (CRC-16). Errors are corrected,
when necessary, by automatic retransmissions. Sequence numbers in message headers ensure that

messages are delivered in proper order with no omissions or duplications.

A number of advantages are offered by the DMCI11 over conventional interfaces that require a combination of hardware and software to implement a protocol. Programming is greatly simplified. Extensive communications expertise is no longer required when programming the DMC11. PDP-11 memory
and processor time are not wasted with instructions implementing the protocol. As a direct result,
throughput is enhanced because the DMC11 operates at high speeds and is not delayed when the
processor has to perform high priority tasks.
There are two versions of the line unit. The M8202 high-speed line unit is intended for local network
applications using coaxial cables. The M8202 contains an integral modem that operates at 1M bps or

56K bps.

The M8201 low-speed unit has no integral modem but contains level conversion logic to interface with
EIA/CCITT V24 or CCITT V35 compatible modems at speeds up to 19.2K bps and 56K bps,
respectively.

1-1

The M8201 and M8202 line units can operate with DDCMP and Bit Stuff protocols.

The line unit is not a stand-alone device. It must be used with a DMC11 Microprocessor.
A separate manual (EK-DMCLU-MM-002) covers the M8201 and M8202 line units.

The microprocessor is a general-purpose control unit that provides a full-duplex parallel data interface
between any PDP-11 family central processor and a given DMC11 Line Unit. With the microprocessor/line unit combination, computers can be configured in many different network applications.
Where the computers are located at the same facility, DMCl1s can be configured for high-speed
operation (56,000 or 1,000,000 bps) over inexpensive coaxial cable. The necessary modems are built-in.
Other DMCI11 (M8200) features include:

Down-line loading of satellite computer systems

Ability to initialize an incorrectly functioning satellite computer system by command over
the link (Remote Load Detect)

|
J

Same PDP-11 software supporting local or remote, full- or half-duplex configurations
Recovery from power failures at either or both ends of a link without loss of data

16-bit NPR (DMA) transfers.
A typical configuration is illustrated in Figure 1-1. Shown is the DMC11-DA (M8201) line unit used

T30

for synchronous data communications. The M8201 interface converts data from the DMCI11 to a
binary serial format compatible with the Electronic Industries Association RS-232C interface specification, used as a standard by nearly all low-speed modem manufacturers.

DMC11

DMC11-AR

MICROPROCESSOR

REMOTE

LINE UNIT

MODEM

;
’ TO REMOTE STATION
VIA TELEPHONE LINES

PDP-11

PROCESSOR

PDP-11
MEMORY

11 - 4365

Figure 1-1

DMCI11 Remote Line Unit Interface

1-2

—

The other line unit is the M8202 with an integral modem. The overall system function is identical to
that of the M8201. In this case, however, because of the built-in modem, the M8202 interfaces directly
to a local coaxial cable.

£>

This configuration uses a single coaxial cable for half-duplex operation or two coaxial cables for fullduplex operation (Figure 1-2).

DMC11

}

LINE

(M8202)

LOCAL

DMC11-AL

MICROPROCESSOR

UNIT

(MB200-YB)

[INTEGRAL

MODEM

TO LOCAL STATION
VIA ONE OR TWO

COAXIAL CABLES
PDP-11
PROCESSOR

POP-11
MEMORY

11 - 4366

Figure 1-2

DMCI1 Local Line Unit Interface

Figure 1-2 defines, in greater detail, the general interface between the microprocessor and any line unit.
First, there are two 8-bit parallel data buses; one is an input bus and the other is an output bus. Two
separate buses are used to sustain full-duplex operation. In the line unit, the data source is addressed
by the microprocessor using the Input/Output register address bus.
The line unit contains eight registers. During a read operation, which uses the Input bus, the microprocessor uses four addressing bits. The most significant bit is held low to show that a line unit register
is being read. The other three bits select the line unit register to be read. During a write operation,
which uses the Output register, the microprocessor uses four different addressing bits. The most significant bit is an enabling bit and the other three bits select the line unit register to be written into.
Simultaneous addressing on the Input and Output buses is possible.

The remaining bus, the control signal interface, delivers timing and control information to the line
unit, such as clock sync and data strobe signals.

Data transfers between the DMC11 and the PDP-11 processor are in the form of the three common
bus transactions. They are the NPR bus cycle, the interrupt sequence, and the reading (DATI) and
writing (DATO) of DMC11 Control and Status Registers (CSRs).

1-3

The Unibus CSRs are composed of eight bytes of device
76XXXO0 through 76XXX7. These device addresses are

addresses and are accessed by addresses
henceforth referred to as Byte Select (BSEL)

0-7 for indicating individual bytes, and SEL, 0, 2, 4, 6 for

indicating word transfers (SELO consists of
etc...). BSELO and BSEL?2 are handshaking
CSRs, which interlock transfers through a common data
port. This data port is accessed through
BSEL4-7 (SEL 4, 6).
BSELO and BSEL1, SEL2 consists of BSEL2 and BSEL3,

When the PDP-11 program wishes to transfer data to

the DMC1 1, the program (through BSELO) sets
up a REQUEST IN (RQI) and a function describing the
data to be passed. The DMC11 responds by
setting READY IN. BSELA4-7 is then loaded by the PDP-11
program, and clears RQI. The DMCl11
takes the data and drops RDYI, which completes the exchang
e.

Similarly, the DMCI11

transfers data to the PDP-11 program by setting READY
OUT (RDYO) with a
function after having loaded BSEL4-7. The PDP-11] program
, after reading the required registers,
should then clear RDY
O, releasing the port for further use.
The DMC11-AR and DMCI11-AL are referenced as micropr
ocessors throughout this manual, as well
as in other related documentation. This is due to the fact
that ROMs are used as controlling elements.
The ROMs act as compact logic arrays that replace a large
amount of distributive logic. For example,
a 2048-bit ROM is organized as 512 words of 4-bits each.
Combining four of these ROMs produces
512 words of 16-bits each. Each word in the ROM is pre-pro
grammed and is unalterable. When
addressed, a specific word always produces the same output.
PR

e
25 st o

,—/1 A}

The information stored in the ROMs at the word level can be

called microste . Executing an appropriate series of microsteps is called a microroutipe. It can represen
t a particular instruction or function.
The combination of microroutines is called a micropgggz,am,
—_—
P

As the microroutine is being executed, the ROM output signals
are sent to the appropriate circuits in
the microprocessor to perform the instruction or function that is
repesented by the microroutine.
P———
———

————,

As illustrated in Figure 1-3, the DMC11 essentially connects the
Unibus to the line unit interface
through internal registers. This allows the data to be processed
by the microprocessor as it passes
between the two buses. The processing is dependent on the micropr
ogram residing in the microprocessor. Currently, a microprogram is available to accommodate

the

D DCMP line protocol.

The block diagram in Figure 1-3 very much resembles a processor

, hence the term microprocessor. It
has a program counter (PC) addressing the microprogram residing
in 1K of ROM. Each microinstruction is a 16-bit word. Certain bits of the microinstruction then serve
as address bits for three

additional ROMs, which control data flow and determine what operation to

perform on the operands.

The DMC11 and line unit consist of two separate modules interconnected
by a one foot cable. Each is
ordered separately. Two microprocessor versions and four synchronous
line unit versions are available: local operation at 1M bps, local operation at 56K bps, remote operation
with EIA/CCITT V24
compatible modems up to 19.2K bps, and remote operation with CCITT
V35 compatible modems up
to 56K bps.
Both the DMCI11-AR and DMC11-AL microprocessor modules (hex
SPC) include a 300 ns bipolar
microprocessor, a ROM implementing the DDCMP protocol, local scratchpa
d memory, and a Unibus
interface.
The DMCI11-MA line unit module (notched hex) includes a built-in modem

bps over coaxial cable up to 6,000 feet in length.

1-4

for local operation at 1M

PROGRAM

COUNTER

CROM

N\
FUNCTION

ROM

SOURCE

ROM

DESTINATION

ROM

J
\Z
UNIBUS

INTERFACE

ALU AND DATA
REGISTERS

LINE UNIT
INTERFACE

11 - 4367

Figure 1-3

Microprocessor Simplified Block Diagram

1-5

The DMC11-MD line unit module (notched hex) includes a built-in modem for local operation at S6K

bps over coaxial cable up to 18,000 feet in length.

Coaxial cables are not included with either line unit. Optional BCO3N-AO coaxial cable is available in

100 foot lengths only. One is required for half-duplex operation and two are required for full-duplex
operation.

The two versions of the remote line unit, DMC11-DA and DMCI11-FA, use the same module
(M8201). Both versions contain level conversion logic that accommodates the EIA /CCITT V24 inter-

face and the CCITT V35 interface. The only difference is the modem cable that is supplied to match
the specified interface.

The DMCI11-DA is shipped with a 25 foot BCOSC cable for the EIA/CCITT V24 interface to accommodate Bell 208 or 209 synchronous modems or their equivalent.

The DMCI11-FA is shipped with a 25 foot BCO5Z cable for the CCITT V35 interface. This synchronous interface is used in certain European networks and in the domestic Digital Data Service (DDS).

1-6

CHAPTER 2

INSTALLATION

2.1 SCOPE
This chapter provides all necessary information for a successful installation and subsequent checkout
of the DMCI11 microprocessor subsystem.

NHAWN—OVHOIRNE
W —

2.2 UNPACKING AND INSPECTION
The microprocessor/line unit system combination arrives at the customer site in one of two ways,
either as a part of a complete computer system or as an add-on option. When it arrives as an add-on
option, the microprocessor module, line unit module, and associated mounting hardware and cables
arrive packaged in a single carton. Inspect the carton visually for any signs of physical damage. Included in the contents of the carton are the following:
M38200-Y
A or M8200-YB Microprocessor module
M8201 or M8202 Line Unit module
BCO08S-1 cable (interconnects microprocessor and line unit)
BCO05C-25 cable (M8201 EIA/CCITT V24 interface only)
BC05Z-25 cable (M 8201 CCITT V35 interface only)
H325 test connector (M 8201 only)
12-12528 coaxial cable test connector (M 8202 only)
MAINDEC-11-DZDMC Microprocessor Basic W/R and Up Test
MAINDEC-11-DZDME Line Unit DDCMP Test
MAINDEC-11-DZDMF Line Unit Bit Stuff Test
MAINDEC-11-DZDMG Jump and Free Running Test
MAINDEC-DEC/XII System Test
ITEP One Line Test
EK-DMCUP-MM-001, Microprocessor Manual
EK-DMCLU-MM-002, Line Unit Manual

2.3 OPTION DESIGNATIONS
There are two microprocessors available, both configured to implement the DDCMP protocol only.
The DMCI11-AR is for remote applications; the DMCI11-AL is for local applications.
The various line units and cables are listed in Table 2-1 and 2-2, respectively.

2-1

Table 2-1

Line Unit Option Designations

Option

Description

DMCI1-DA

M8201 Line Unit Module with cable for EIA /CCIT
T V24

DMCI1I1-FA

M38201 Line Unit Module with cable for CCITT V35
interfa

DMCI11-MA

M8202-Y
A Line Unit Module with 1M bps integral modem
and no cable

DMCI11-MD

M8202-YB Line Unit Module with 56K bps integral

interface
ce

Table 2-2

modem and no cable

Line Unit Cables

Option

Description

BCO3N-A0

100 foot coaxial cable with connectors, used with

BCO05C-25

25 foot EIA/CCITT V24 cable for use with DMC11-DA

BC05Z-25

25 foot CCITT V35 cable for use with DMC11-FA

2.4
MECHANICAL PACKAGING
The DMCI1 consists of a microprocessor module (hex) and

modules plug into any DD11-B Rev E or later, DD11-C, DD1

M8202 Line Unit module

Line Unit

a line unit module (notched hex). These

1-D, or equivalent SPC system unit. The
or 3 in the DD11-B or DDI11-C. The line
unit module may be installed in any of the remaining slots. Should
two DMC1s be installed in a single
DDI11-B, then the line unit module plugs into slot 1 or 4.

microprocessor module must always plug into either slot 2

The line unit does not interface with the Unibus so module
edge connectors A and B are not required.
As a result, the corner of the module in the vicinity of the
A and B connectors has been removed. This

allows the M8201 and M8202 to be installed in the end slots of
the DD11-B, C, and D system interfacing units. The module plugs into connectors C, D, E, and
F and fits over the Unibus cable con-

nector and short length (approximately 2-1/2 inches) Unibus
terminator that are installed in end slot
connectors A and B.

The two modules are interconnected by a Berg 40-pin connecto

r and a 1-foot BC08S-1 cable.

2.5

PRE-INSTALLATION PROCEDURES

2.5.1

General Information
Installation of the microprocessor/line unit combination should
be done in three phases. First, the
microprocessor is physically installed then checked and verified
with MAINDEC-1 1-DZD MC. In this
manner the microprocessor is checked as a stand-alone module
apart from the line unit. Next, the line
unit module is installed and operationally verified with MAINDEC-11-D
ZDME and MAINDEC-11DZDMR, which also provides an additional confidence factor for
the microprocessor. The third and

final installation phase involves the execution of MAINDEC-1 I-DZDM
G, which verifies the operational status of both the microprocessor and the line unit as a free running
test. Additionally, this test
checks the contents of the ROMs (microcode) and the BRANCH instructio
ns.

2-2

A minimum of 8K of memory is necessary for execution of the MAINDEC diagnostics.

Check the power supply to ensure against overloading. The microprocessor/line unit total current
requirement for the +5 V supply is approximately 8 A. Additionally, the line unit requires £15 V for
the silos and the level conversion logic and the integral modem.
Installation requires two adjacent hex SPC slots, one of which can be either the Unibus input or
terminator slot if the modules are 2-1/2 inches or less. The DMC11 microprocessor requires a full hex
slot, while the line unit fits into any slot in the DD11 backplane. The microprocessor can be installed in
the DDI11-B Rev E or higher, DD11-C, DD11-D, or equivalent backplanes. Such an equivalent backplane is that used in the PDP-11/04 or PDP-11/34 computers.
2.5.2 Preinstallation Checkout Procedures
Before installing the microprocessor module, the following functions must be performed.
.

Verify that jumper W1 is installed. This jumper should not be removed in the field. It is
removed only at the factory during automated module testing to inhibit the oscillator in the
microprocessor clock logic.

The microprocessor device address must be selected in accordance with Paragraph 2.7.

The microprocessor vector address must be selected in accordance with Paragraph 2.8.

Verify that a BRS priority card is installed in position E75.

Verify that switch numbers 7 and 9 in the DIP switch package, located in position E76, are
both OFF. In this package, switches 1-6 are used for the vector address and switches 8 and
10 are not used.

Switch 7 is the Run Inhibit (RI) switch, which is connected between ground and the CLEAR input of
the RUN flip-flop. Normally, it is OFF and the RUN flip-flop cannot be cleared directly. Under

normal conditions, initialization of the microprocessor directly sets the RUN flip-flop, which allows

the microcode to be executed immediately. Because of an internal malfunction or execution of
malicious microcode during power up, it is possible for the microprocessor to hang the Unibus. Now,
it 1s not possible to load the diagnostics to determine the fault. Placing the RI switch in the ON
position clears the RUN flip-flop and allows the diagnostics to be loaded.

Switch 9 is the Byte Sel | Lockout (BS1) switch. It is related to the “computer in a closet” application,

where all programs are down-line loaded. When set, the BS1 switch prevents a runaway program in the

PDP-11 processor from preventing a boot or down-line loading operation via the DMC11 link. This
switch inhibits all maintenance functions.

NOTE
Before installing the microprocessor (M8200),
remove the NPR Grant wire that runs between pins
CA1l and CB1 on the backplane for the slot that is
going to accept the M8200. Do not remove the wire
for the slot that is going to accept the line unit
(M8201 or M8202).

The M8200 Microprocessor presents one load to the Unibus and the M8201 and M8202 Line Units
present no load to the Unibus except for power requirements.

2-3

The local DMCI11 configuration (DMC11-AL Microprocessor and
DMC11-MA or DMC11-MD
Line Unit) requires bus placement nearest to the PDP-11 processor; this
is due to the high rate of NPR
transactions that is required. For example, the DMC11-MA Line Unit
(IM bps) requires an average of
one NPR every 8 us.
|

2.6 INSTALLATION
After completing the pre-installation checkout procedures in Paragrap
h 2.5.2, proceed with the installation as follows:
I.

Insert the microprocessor module in the proper backplane slot.

Run MAINDEC-11-DZDMC to verify correct operation of the microproc

essor.

DIAGNOSTIC NOTE
If the installation is in a system using a PDP-11/04
or other PDP-11 processor that does not have a

switch register, a software switch register is used to
allow the user the same switch options. If a switch
register is available but contains all 1s (177777), the
software switch register is used. Refer to the appropriate diagnostic document for further details.
3.

Check all appropriate switch settings and jumpers on the line unit module
in accordance
with the recommendations in Chapter 2, Installation, of the line
unit manual (EKDMCI11LU-MM-002).

Insert the line unit module in the proper backplane slot.

[Interconnect the line unit and microprocessor using cable BC08S-1 which is a
1-foot long, 40
conductor flat mylar cable with H856 female connectors on each end. The mating
connector
on the microprocessor and line unit is an H854 male connector. On the microprocessor,
this
connector is designated J1. On the M8201 Line Unit, it is designated J2 and
on the M8202
Line Unit it is J1.

On the M8201, install the BCO5C-25 cable to connector J1. On the other end
connect the H325 test connector.

of this cable,

On the M 8202, install the 12-12528 coaxial test connector, which ties the two coaxial pigtails
together. These two 3-foot cables are soldered to the M8202.
7.

On the M8202, check that the integral modem clock is within specificatons. Refer to

unit manual.

the line

On the backplane, check that the supply voltages are within the following tolerances:

Min
+4.75

Voltage
Nominal

|
Max

-14.25

+5.0
—15.0

+14.25

+5.25
—15.75

+15.0

+15.75

2-4

Backplane
Pin
ClA2
C1B2
ClUl1

Run MAINDEC-11-DZDME and -DZDMF to verify correct line unit operation.

10.

Run MAINDEC-11-DZDMG to verify correct line unit/microprocessor operation. This
diagnostic also tests the microcode and BRANCH instructions.

Remove the test connector.

For the M8201, connect the BCO5C-25 or BC0O5Z-25 cable to the customer-supplied modem.

CAUTION
The maximum allowable length for the BCOSC and
BCOSZ cable is 50 feet.
For the M8202, connect the pigtails to the customer coaxial cables or the optional 100-foot
BCO3N-AO cable.
2.7

DEVICE ADDRESSES

2.7.1
Introduction
Starting with the DJ11, new communications devices are to be assigned floating addresses. The
addresses for current production devices are to be retained.
The word floating means that addresses are not assigned absolutely for the maximum number of each
communications device that can be used in a system.
2.7.2 Floating Device Address Assignments
Floating device addresses are assigned as follows:
1.

The floating address space starts at location
designations).

760010 and extends to location 764000 (octal

The devices are assigned, in order, by type: DJ11, DH11, DQ11, DU11, DUP11, DMCl1,

and then the next device introduced into production. Multiple devices of the same type must
be assigned contiguous addresses.

The first address of a new type device must start on a modulo 10s boundary, if it contains
one to four bus-addressable registers. The starting address of the DH11 must be on a modulo 205 boundary because the DH11 has eight registers.

A gap of 10g, starting on a modulo 103 boundary, must be left between the last address of
one type device and the first address of the next type device. A gap must be left for any
device on the list that is not used, if the device following it is used. The equivalent of a gap
should be left after the last device assigned to indicate that nothing follows.
No new type devices can be inserted ahead of a device on the list.

If additional devices on the list are to be added to a system, they must be assigned contiguously after the original devices of the same type. Reassignment of other type devices
already in the system may be required to make room for the additions.

The following examples show typical floating device assignments for communications
-devices in a system.

2-5

Example 1: No DJl11s, 2 DH1l1s, 2 DQI11s, 1 DUPII, and | DMCl1

760010
760020
760040
760060
760070
760100
760110
760120
760130
760140
760150
760160

DJ11gap
DHI11 #0 first address
DHI11 #1 first address
DHI11 gap
DQI1 #0 first address
DQI11 #1 first address
DQI1 gap
DUI11 gap
DUPI11 #0 first address
DUPI11 gap
DMCI11 #0 first address
Indicates no more DMC11s and no other devices following

Example 2: 1 DJ11, 1 DHI11, 2 DQlls, 2 DUPI1Is, and 2 DMCl1s
760010
760020

760040
760060
760070
760100
760110
760120
760130
760140
760150
760160
760170
760200

DJ11 #0 first address
DIJ11 gap

DHI11 #0 first address
DHI11 gap
DQI11 #0 first address
DQI11 #1 first address
DQI11 gap
DUI11 gap
DUPI11 #0 first address
DUPI11 #1 first address
DUPI11 gap
DMCI11 #0 first address
DMCI1 #1 first address
Indicates no more DMC11s and no other devices following

2.7.3 Device Address Selection
In the floating address space (760010-764000), bits 13-17 are always 1s (function of

PDP-11 processor). Appendix A shows the PDP-11 memory organization and addressing conventions
. Bits 312 are
selected by switches in the address decoding logic (Table 2-3). With the switch on (closed),
the decoder
looks for a 0 on the associated Unibus address line. Bits 0, 1, and 2 are decoded
to select 1 of 8
registers.
The device address selection switches are contained in one DIP switch package

located in position
E113. All 10 switches in the package are used. The correlation between switch numbers
and address bit
numbers is shown in Table 2-3. The ON and OFF positions and the switch numbers
are marked on the
package. The switches are rocker type and are pushed to the desired position (Figure
2-1).

2.8

VECTOR ADDRESSES

2.8.1
Introduction
Communications devices are assigned floating vector addresses. This eliminates the
necessity

ing addresses absolutely for the maximum number of each device that can be used in

2-6

of assignthe system,

| 716

(4312

|7 | 6

|5 | 4

760030

760040

760050
760060
760070

e
R Re

760020

760010

Address

760300

760200

760400

oo R
ol

Device

760100

760500
760600

760700

761000
762000

763000

NOTES:

I
| =it

|18

12111109 { 8

1019

Switch No.

Bit No.

Table 2-3 %uide for Setting Switches to Select Device Address

X means switch off (open) to respond to logical 1 on the Unibus.

Switch numbers are physical positions in switch package 1.

2-7

764000

76c74c

UNUSED

BYTE SEL1 LOCKOUT (BS1)
UNUSED

RUN INHIBIT (R1)
A3

e e A12

D3—

UNIBUS ADDRESS

BITS A3-A12

beed

r——

=0 W W

—

-D8

cune

ons B o

l
6

e B cems B e B o B e [ S

SWITCH ON GENERATES LOGICAL 1

DEVICE

VECTOR

ADDRESS

—

8ITS D3-D8

—

UNIBUS DATA

SWITCH ON SELECTS LOGICAL O

ro5

—

ADDRESS

E113

L _E8

= ..

L _EEZ_J

E76

E75

BR PRIORITY

SOCKET

;

M8200
MODULE

11 - 4368

Figure 2-1

Microprocessor Device and Vector Address Switches

2-8

2.8.2 Floating Vector Address Assignment
Floating vector addresses are assigned as follows:
I.

The floating address space starts at location 300 and proceeds upward to 777. Addresses
500-534 are reserved.

The devices are assigned in order by type: DCI1: KL11/DL11-A, B; DP11;
DM11-A;
DN11; DM11-BB; DR11-A; DR11-C; PA611 Reader; PA611 Punch; DT11;
DX11; DL11C, D, E; DJ11; DHI11; GT40; LPS11; VT20; DQ11; KW11-W:; DUI11; DUPIL;
DV11;
DMCl1,

Ifany type device is not used in a system, address assignments move up to fill the

If additional devices are to be added to the system, they must be assigned contiguous
ly after
the original devices of the same type. Reassignment of other type devices already
in the

vacancies.

system may be required.

2.8.3 Vector Address Selection
Each drive interrupt vector requires four address locations (two words), which
implies only evennumbered addresses. A further constraint is that all vector addresses must end
in a 0 or 4. The vector
address is specified as a three digit, binary-coded, octal number using Unibus
data bits 0-8. Because
the vector must end in 0 or 4, bits 1 and 0 are not specified (they are always 0) and
bit 2 determines the
least significant octal digit of the vector address (0 or 4). The interrupt
control logic sends only seven
bits (2-8) to the PDP-11 processor to represent the vector address.

The DMCI11 is shipped with a BRS priority selection card installed in the
interrupt control logic. This
logic generates two vector addresses: RDY 1 interrupts generate vector addresses
of the form XX0, and
RDY O interrupts generate vector addresses of the form XX4. For this
method of operation, the state
of bit 2 is selected by the logic, not by a switch. The two most significan
t octal digits of the vector
address are determined by switches in lines 3-8 (Table 2-4). With the switch
OFF (open), a 0 is generated on the associated Unibus data line; with the switch ON (closed),
a 1 is generated on the associated
Unibus data line.

The vector address selection switches are contained in one DIP package located in position E76 (Figure 2-1). Only 6 of the 10 switches in the package are used for the vector address. The correlation
between switch numbers and bit numbers is shown in Table 2-4. The ON and OFF positions and the
switch numbers are marked on the package. The switches are rocker type and are pushed to the desired
position.
2.9 INSTALLATION CHECKLIST
The following items represent a concise checklist of the important features of the DMC11
1.

Power Requirements

M8200
M8201

+5V@4.0A
+5V@3.0A
+15V@0.03 A

—15V@031A

M8202

+5V@30A
+15V@0.18
A
—15V@0.46
A

2-9

|
.
installation.

oo
|

»<
S

Vector

Address
300

310
320

330
o TR

340
350

Pl X R P4 K K X X

Bit No.

< 2K < XK

Switch No.

Guide for Setting Swit?hes to Select Vector Address
0|
N

Table 2-4

400

360

NOTES:

)

370

X means switch off (open) to produce a logical 0 on the Unibus.

Switch numbers are physical positions in switch package 2.

Unibus Loading. The M8200 presents one Unibus load. The M8301 and M 8202 present no
Unibus loads.
Special Installation Requirements
a.

MS8200 Microprocessor. Before installing, remove the NPR Grant continuity wire that
runs between pins CAl and CB1 on the backplane for the slot that is going to accept
the M8200. If a system change requires removal of the M8200, the wire must be
replaced.

M8200 Microprocessor with Local Line Units (DMC11-MA or DMCI11-MD). This
configuration must be placed on the Unibus closest to the PDP-11 processor because of
the high rate of NPR transactions that are required. It must also be placed before a
DBI11-A Bus Repeater if one is used.

2-10

MB8200 Microprocessor Switch Settings

//@

Address Selection (E113)

Switch No.

Switch OFF

Address Bit

2
3

5
6
7
8
9
10

8
9
10
11
12

5
7

(open) to respond to logical 1 on Unibus.

Switch ON (closed) to respond to logical 0 on Unibus.

Vector Selection (E76)

Vector Bit

WV I
o JEN W

~—~

Switch No.

AWNE

Switch OFF (open) to produce a logical 0 on the Unibus.
Switch ON (closed) to produce a logical 1 on the Unibus.
¢c.

Remaining switches in E76

Switch 7 is RUN INHIBIT (RI) and should be OFF.
Switch 9 is BYTE SEL 1 LOCKOUT (BS1) and should be OFF.
Switches 8 and 10 are not used and should be OFF.

2-11

Line unit switch settings and juniper configuration as shipped.
a.

Switch Settings

(1)

Switch Pack No. 2 (E87 on M8201 and E90 on M8202) - All switches
should be
OFF.

(2)

Switch Pack No. 3 (E88 on M8201 and E91 on M8202) - All switches

OFF.
(3)

should be

Switch Pack No. 1 (E26 on M8201 and E29 on M8202) - The switches
should be
positioned as shown in Table 2-5.

The jumpers should be configured as shown in Table 2-5.

Table 2-5 Configuration of Jumpers and
Switch Pack No. 1 on Line Unit

*
Switch No.

DMC11-DA
M8201

DMCI11-FA
M8201

DMC11-MA/MD
M8202

|
2

OFF

3
4

OFF

OFF
OFF

5
6
7
8

OFF
OFF
ON
ON

OFF
ON
OFF
OFF
ON
ON

OFF
OFF
OFF
OFF
OFF
OFF

OFF

Jumper No
|
2

IN
ouT

010))
ouT

OuUT

5
6

OUT
Not Present

ouT

ouT
Not Present

OuT
OUT (FD)

IN (HD)
NOTES
*Switch pack no. 1 located at E26 on M8201 and E29 on M8202.
FD = Full Duplex.
HD = Half Duplex.

2-12

CHAPTER 3
PROGRAMMING INFORMATION

3.1 INTRODUCTION
This chapter contains general information necessary for PDP-11 programming of the DMC11 Microprocessor. In general, the information is presented by operational categories such as input transfers,
output transfers, etc. Also included are descriptions of the Unibus control and status registers, microprocessor control and status registers, and line unit control and status registers.

The information in this chapter is arranged as follows.

Paragraph

Description

Number

Introduction
Interrupt Vectors

3.1
3.2
3.3
3.4

Priority Selection
PDP-11 Programming Information
Introduction
Unibus Control and Status Registers
Input Transfers

34.1
342

e
—

WWWwWwwww

il
ol ol ol ol o

Control Out Transfers
Maintenance Messages
Remote Load Detect and Down Line Load
Power Fail Recovery
Microprocessor Control and Status Registers
Line Unit Registers

Data Transmission
Data Reception

Initialization
DDCMP Start Up

\D OO0 ~J O\

343
344
34.5

Output Transfers

3.2 INTERRUPT VECTORS
The DMCI1 generates two vector addresses: input (PDP-11 to microprocessor) interrupts generate
vector addresses of the form XXO0; and output (microprocessor to PDP-11) interrupts generate vector
addresses of the form XX4. The conditions that initiate the interrupts are:

XX0 - An interrupt at address XX0 occurs when the PDP-11 requests the port (SEL4 or SEL6) and the
microprocessor responds by asserting Ready In (RDY]I) and Interrupt Enable In (IEI).
XX4 - An interrupt at address XX4 occurs when, after charging the port with data, the microprocessor
asserts Ready Out (RDYO) and Interrupt Enable Out (IEO).

3-1

3.3 PRIORITY SELECTION
The priority for the interrupts is selectable on the microprocessor via a plug-in priority

It 1s shipped with a card that establishes BRS as the priority level.

3.4

selection card.

PDP-11 PROGRAMMING INFORMATION

3.4.1
Introduction
Programming the DMCI1 is described at two levels. The first level describes how a PDP-11
program

uses the DMCI11 control and status registers together with the interrupt system for transfer of
control
and status information between the PDP-11 program and the DMC11 microprogram. The
second
level describes details of these transactions, including formats, details of device and protocol
initialization, data transfer, and unusual cases.

In order to successfully program the DMCl11, it is not necessary to be familiar with the details of

DDCMP protocol operation. These are handled by the DMC11 microprogram. H owever, some famil1arity with the protocol operation is useful in interpreting the significance of the various error counters
provided to assess the quality of the circuit connecting the two computers. If a DMC11 is to communicate with a different interface, which uses a software implementation of DDCMP, the person programing the software implementation should consult the DDCMP protocol standard document.
3.4.2

Unibus Control and Status Registers
Communication of control and status information between the PDP-11 and the DMC11 uses eight
bytes of control and status registers (CSRs). These are addressed as 76XXXO0, 76XXX1, 76XXX2,
76X XX3, 76XXX4, 76XXXS5, 76XXX6, and 76XXX7. These device addresses are subsequently
referred to as Byte Select 0 to 7 (BSELO - BSEL?7) for indicating individual bytes and as SELO, SEL2,
SEL4, and SELG6 for indicating words.

NOTE
The CSRs are implemented with Random Access
Memory (RAM). Thus, at power on, the CSRs come
up in random states. As part of the microprocessor
initialization, the CSRs (SEL0-6) are cleared with
the exception of bit 15 of SELO (RUN) which is set.
The lower order 8 bits of SEL0 (BSELO) are cleared
first. Due to the high speed of the microprocessor,
the registers are cleared before access by the PDP11 is possible.
BSEL4-7 comprise a 32-bit data port that is used to pass information between the microprocessor and

the PDP-11. The transfer of information from the PDP-11 to the microprocessor is called an Input
Transfer, often abbreviated IN or I. The transfer of information from the microprocessor to the PDP11 1is called an Output Transfer, often abbreviated OUT or O. These terms are not to be confused with
sending and receiving data on the serial line which are called sending or transmission, and receiving or
reception.

BSELO controls input transfers and BSEL2 controls output transfers. BSEL1 contains bits used for
maintenance purposes which are of no concern to the programmer. It also contains the MASTER

CLEAR bit which can be used to initialize the DMC11 microprocessor. BSEL2 is not used. A switch
on the microprocessor module prevents the PDP-11 program from clearing RUN or performing other
maintenance functions in BSEL1 which would disable the microprocessor’s ability to initialize an
unattended PDP-11 computer system.
As reference for the programmer, the bit assignments for the Unibus CSRs are shown in Figure 3-1. A
detailed description of each register is shown in tabular form.

3-2

15 l 14

12 I 1

6 | 5

step | LU | rom | rom | ster B o0 | e | Ra
'
RUN l MCL n y////
//. w | oor| o
|
uP
|
|

PRIORITY

]

3 |2

' €0

N
IN

o10

US ADDRESS

Figure 3-1

Unibus Control and Status Registers

bosT Durr =4

3-3

FYPE
| |

3.4.2.1
1).

BSELO - Input Register - This register comprises the low byte of address

76XXX0 (Figure 3-

Bit

Name

Description

0,
1

TYPE INPUT
(TYPI)
E

These bits define the type of input transfer as follows.
Bit 1
0

Bit 0
0

Control In (CNTL I)

Reserved

Base In (BASE I)

Buffer Address/Character
In (BA/CC )

Count

Each of these transfers is explained in detail.
00 = Buffer Address/Character Count In utilized with
REQUEST IN (RQI). This is a request to the microprocessor by the PDP-11 to use the data port (BSEL4-7)
for purposes of transferring an 18-bit bus address and a
14-bit character count must be expressed as a positive
binary number.
01 = Control In - When used with RQI, requests the use
of the data port (BSEL4-7) from the microprocessor for
the purpose of transferring protocol and/or process
control information.

10 Reserved
11 Base I - Base In provides a base address which, when
used with RQI, requests from the microprocessor the
use of data port (BSEL4-7) for the purpose of transferring up to an 18-bit Base Address and RESUME (power
fail) bit.
02

INI/O

3,4

RESERVED
REQUEST IN

(RQI)

Defines the flags (BA/CC, etc.) for Input (receive) or
output (transmit). For example, if BSEL4-7 contained a
new BA /CC, the microprocessor would need to know
whether this was a block to be transferred out, or a buffer for a message to be received.

Set by the PDP-11 to request an input transfer. Cleared
by the PDP-11 when the data has been loaded. This bit
serves as an interlock bit, which is used to request the
use of the data port (BSEL4-7) in order to transfer up to
40 bits of data from the PDP-11 program. The RQI bit
is accompanied by type of transfer as defined by bits
2-0.

3-4

Bit

Name

INTERRUPT ENABLE | When set, allows the microprocessor to vector interrupts

Description

INPUT (IEI)

to XXO0 having set RDY 1.

READY IN
(RDY D)

This

is a microprocessor response to RQI. When
asserted, it indicates to the PDP-11 program to proceed
with loading the data port (BSEL4-7). This bit is cleared
by the microprocessor at the end of an input transfer.

3.4.2.2 BSELI1 Maintenance Register - This CSR contains all maintenance
functions other than
MASTER CLEAR and is not intended for normal user communications between
the PDP-11 program
and the microprocessor. These functions override all other control functions.
All bits are read /write;
however, only MASTER CLEAR is functional if BSEL1 LOCK OUT
is set. This register comprises
the high byte of address 76XXXO0 (Figure 3-1).
Bit

Name

Description

STEP MICROPROCESSOR
(STEP MP)

This bit, when set, steps the microprocessor through one
instruction cycle, composed of five 60-ns clock pulses.
The RUN flip-flop should be cleared before executing
this control function.

ROM INPUT
(ROM 1)

When set, directs the contents of BSEL6-7 as the next
microinstruction to be executed by the microprocessor
when STEP MP is asserted.

ROM OUTPUT
(ROM 0)

When set, modifies the source paths for BSEL4-7 to be
the contents of the addressed CROM or the next microinstruction executed when STEP MP is asserted.

LINE UNIT LOOP
(LU LOOP)

This control function, when asserted, connects the line
unit’s serial line out back to its serial line in. This is done
at the TTL level, before level conversion. When the
LINE UNIT LOOP bit is set and RUN is cleared, the
STEP LU clock is the only clock available for shifting
data out or in. When LU LOOP is set and RUN is set
data is clocked at a 10K bps rate. If the H325 loop back

connector is installed at the end of the EIA cable with

RUN set and not in LU LOOP mode, data is shifted by
a free running clock of approximatly 10K bps.

The 1M bps and 56K bps line units require a 12-12528
coaxial adapter installed at the line unit pigtail cables to
provide the loop back. The line unit operates at the
clock rate of the integral modem in this case.
12

STEP LINE UNIT
(STEP LU)

RESERVED

This control function is used in conjunction with LU
LOOP. When asserted, the transmitter shifts, and when
negated, the receiver shifts.

3-5

Bit

Name

Description

MASTER CLEAR

When set, MASTER CLEAR initializes both the microprocessor and the line unit. This bit is self-clearing. The

microprocessor clock is enabled and the RUN flip-flop
is asserted. The CROM’s PC is also temporarily cleared
by MASTER CLEAR allowing the microcode to enter
the idle state.
15

RUN

RUN controls the microprocessor clock. This bit is set
by BUS initialization or MASTER CLEAR, which
enables the microprocessor clock. RUN can be cleared
for maintenance states. A switch (BS1) is provided,
which prevents RUN from being cleared by a runaway
microcode program when the microprocessor malfunctions. Refer to Chapter 2, Installation, for more information concerning the BS1 switch.

3.4.2.3 BSEL2 Output Register — This register contains control information relative to output transfers from the microprocessor to the PDP-11 program. This register comprises the low byte of address

76XXX2 (Figure 3-1).

Bit

Name

Description

0, 1

‘TYPE OUTPUT

These bits are encoded for the type of data transfer from

(TYPE O)

the microprocessor to the PDP-11 program.

00 = Bus Address and Character Count Out
01 = Control Output
10 = Reserved
11 = Reserved
2

OUTI1/0

OUT I/O defines the flags (BA/CC, etc.) for Input

(receive) or Output (transmit). For example, if BSEL4-7
contained a BA/CC, the PDP-11 program would want
to know whether this was a block completed on output
or a message received. An input is indicated when this
bit is set; an output is indicated when this bit is cleared.
3-5
6

RESERVED
INTERRUPT ENABLE | When set, the microprocessor, upon asserting RDYO,

OUTPUT (IEO)

vectors an interrupt to XX4.

READY OUTPUT
(RDYO)

This bit, when asserted, indicates that BSEL4-7 contain

data as defined by bits 0-2. This bit must be cleared by
the PDP-11 program after the port data has been
sampled.

3-6

3.4.2.4 BSEL3 Line Number/Priority Register - If the DMCI11 is used as a multiple line controller,
this register is used to designate line numbers and to assign priority for block data transfers.

This register comprises the high byte of address 76XXX2 (Figure 3-1).

Bit

Name

Description

8-13

LINE NUMBER

These bits are designated for line numbers during format transfers. The line number bits are required when
the DMCI11 microprocessor is used as a multiple line
controller.

14, 15

PRIORITY

These bits assign priority to blocks of data for transfer

via the DMC11 microprocessor when it is used as a multiple line controller. This is especially useful when lines

of different speed are used.

3.4.2.5 Data Port Message Formats - The data port is represented by addresses 76XXX4 and
76XXX6. The first half of the port is 76XXX4, which includes BSEL4 and BSELS. The second half of
the port is 76XXX6, which includes BSEL6 and BSEL?7.
The port is loaded by the PDP-11 on input transfers and by the microprocessor on output transfers.
The format and contents of the data port depend on the transfer type (TYPE I or TYPE O).

In discussing the data port message formats, it is sometimes more convenient to use word designations
(SEL4 and SELG6) rather than byte designations (BSEL4-7).
There are four formats:
1.

Buffer address/character count input and output (BA/CC I and BA/CC O).

Base input (BASE I)

Control input (CNTL I)

Control output (CNTL O)

BA/CC I and BA/CC O Format — The formats for BA/CC I and BA/CC O are the same
(Figure 3-1). SEL4 contains the least significant 16 bits (0-15) of the 18-bit buffer address.
The two most significant bits (16 and 17) of this address are contained in bits 14 and 15 of
SEL6. The remaining 14 bits (0-13) of SEL6 contain the character count in positive notation, not 2’s complement notation.

The microprocessor can stack a maximum of seven BA /CCs each for input and output. This
number is based on the size of the core tables (BASE) in the PDP-11 memory, which is
limited to 256 bytes.

For input operations, BA /CC I supplies new message buffers to the microprocessor.
For output operations, BA/CC O returns the buffers to the PDP-11 that were successfully
transferred to the microprocessor.

3-7

BASE I Format - SEL4 and bits 14 and 15 of SEL6 provide the first address of a reserved
block of addresses in the PDP-11 memory (Figure 3-1). The block size is 256 bytes. Upon
assigning the BASE address to the microprocessor, the PDP-11 program must not modify
any locations within the assigned block.
Bit 13 of SEL6 is called RESUME. If this bit is cleared, the microprocessor initializes the

base table and protocol. If set, the microprocessor resumes operation as specified by the

contents of the base table.
3.

CNTL I Format - The CNTL I format provides a means of implementing certain control

functions (Figure 3-1).

SEL4 and bits 14 and 15 of SEL6 contain the address for this format. The control bits are
located in SEL6 as shown below.

Bit
0-7

Name

Description

SECONDARY

These bits define the address of a station in the second-

ADDRESS

(SEC ADRYS)
8

DDCMP

MAINTENANCE
(DDCMP MAINT)
9

RESERVED

DDCMPHALF

DUPLEX
(DDCMP HD)
11

DDCMP

(SECONDARY
DDCMP SEC)

12,13

ary mode under the discipline of DDCMP.

With this bit set, the microprocessor enters the DDCMP
maintenance mode, where it remains until it is subsequently initialized.

With this bit set, DDCMP half-duplex operation is
selected. With this bit cleared, DDCMP full-duplex

operation is selected. This bit must be used with bit 11.

With this bit set, DDCMP half-duplex secondary sta-

tion

operation

selected.

With

this

DDCMP half-duplex primary station
selected. Not used for full-duplex.

bit

cleared,

operation

RESERVED

CNTL O Format - The CNTL O format provides a means of informing the PDP-11 program of error conditions involving the DMCI11 hardware, PDP-11 program, communications channel, or the remote station.

SEL4 and bits 14 and 15 of SEL6 contain the address of this format. The control bits are
located in SEL6 as shown below (Figure 3-1).

Bit

Name

Description

DATA CHECK
(DATA CK)

When set, this bit indicates that a retransmission thresh-

TIME OUT

old has been exceeded.

When set, this bit indicates that the microprocessor has

received no response from the remote end of the link for
21 seconds.

3-8

Bit

Name

Description

OVERRUN (ORUN)

DDCMP
When set, this bit indicates that a message in the
MAINTENANCE
DDCMP maintenance format has been received and
RECEIVED (DDCMP | that the protocol operation has entered the maintenance
MAINT RECD)
|
state.
|

LOST DATA

RESERVED

DISCONNECT

When set, this bit indicates that a message was received,
but no buffer is available to receive it.

When set, this bit indicates that the received message is
longer than the supplied buffer.

When set, this bit indicates that an off to on transition of

the modem Data Set Ready lead has been detected.
7

When set, this bit indicates that a DDCMP Start mesRECEIVED (DDCMP | sage was received when the protocol was in the running
START RECD)
or maintenance state.

NON EXISTENT

DDCMP START

MEMORY (NON EX
MEM)
9

PROCESSOR ERROR | When set, this bit indicates that the PDP-11 program

(PROC ERR)

3.4.3

When set, this bit indicates that a Unibus address time
out has occurred.

has performed a procedural error.

Input Transfers

Whenever the data port is not in use, it is subject to being seized by the microprocessor for use in an

output transfer. Therefore, the PDP-11 program must request the microprocessor to assign it the port
before proceeding with an input transfer. It must also specify the type of input transfer (a transmit
buffer, a receive buffer, control information, etc.) so the microprocessor can make appropriate
preparations.
The PDP-11 program should set bits 0-2 of BSELO to indicate the type of transfer and then set bit 5,

Request In (RQI), to request the port. These bits may be set by a single instruction. The microprocessor responds by setting bit 7, Ready In (RDYTI), when the port has been assigned to the PDP-11

program. When RDY
1 has been set, the PDP-11 program should load the desired data into the data
port (BSEL4-7). Then, it should clear RQI. The microprocessor takes the data and clears RDYI which
completes the transfer.

Bit 6 of BSELO, Interrupt Enable Input (IEI), controls whether the PDP-11 program receives an
interrupt (to Vector XX0) when the microprocessor has set RDYI. The microprocessor responds to
RQI immediately (within 10 us) when operating at speeds below 1 Mb or at | Mb when either the
transmitter or receiver is idle. It is most efficient for the PDP-11 program to have interrupts disabled
and simply scan RDYI one or more times until the microprocessor has set it. While the PDP-11
program is waiting, it must be prepared to accept an output transfer because the microprocessor may
have seized the port in the meanwhile.

3-9

The microprocessor cannot service certain types of input transfers immediatel
y. For example, the
PDP-11 program may attempt to queue more than seven buffers for transmissi
on. In these cases, it is
convenient to use interrupts. If the PDP-11 program finds RDY] clear after
several scans, it can enable
interrupts by setting IEI with a BIS or MOV instruction. The DMC11 interrupts
the PDP-11 (to
Vector XX0) when the microprocessor has set RDYI. The PDP-11 program
gets the interrupt in all
cases, even if the microprocessor had already set RDY] at the time the program
sets IEI. The program
can bypass any scanning if IEI is set when the program sets RQI.

NOTE
The PDP-11 program should not begin a new input
transfer until the previous transfer has been completed, as indicated by the microprocessor dearing
RDYI. The microprocessor does this within 10 __s
after the program has cleared RQI. If the PDP-11

program wishes to begin a new transfer immediately,

it should check that RDYI has been cleared before
setting RQI. This can be done by scanning RDYI
until it has been cleared.
3.4.4 Output Transfers
The microprocessor initiates an output transfer when it has status or error informatio
n to transfer to
the PDP-11 program or it wishes to return a full buffer on reception or an empty buffer
on transmission. The microprocessor can initiate an output transfer at any time the data port is free; that is,
not
assigned to the PDP-11 program for an input transfer and not in use for a previous output transfer.
However, if the PDP-11 has initialized the DMC11 by setting MASTER CLEAR or generating
the
INIT signal on the Unibus, the microprocessor does not generate any output transfer until it
has been
initialized by the PDP-11 program.
The microprocessor loads status or error information into the data port (BSEL4-7) and sets

bits 0-2 of
BSEL?2 to indicate the format and significance of the data. It then sets bit 7 of BSEL?2, Ready
Out
(RDYO), to indicate to the PDP-11 programs that data is available. In response to RDYO
setting, the
PDP-11 program should note the type of output transfer as specified in bits 0-2 of BSEL2 and
read the
data in the data port. When the PDP-11 program has sampled all the data, it must complete the
output
transfer by clearing RDYO. This frees the data port for a subsequent transaction.

If the PDP-11 program wishes, it can enable interrupts on output transfers by setting bit 6 of BSEL?2,
Interrupt Enable Output (IEO). If IEO is set, the DMC1 1 interrupts the PDP-11 (to Vector XX4) after

the microprocessor has set RDYO. Since the PDP-11 program usually does not know when
an output
transfer will occur (for example, when a message will be received) an efficient PDP-11 program ordinarily enables interrupts on output transfers.

NOTE
The PDP-11 program must respond to RDY
O being
set by reading the data and clearing RDYO. Failure
to do this prevents the data port from being freed. If
the PDP-11 program has requested an input transfer
by setting RQI, it must be prepared to respond to an
output transfer prior to being given RDYI. If the
PDP-11 program fails to respond to RDYO, it never
gets RDYI. The PDP-11 program should not spin on
RDYI in a loop that does not also test RDY
O unless
interrupts on output transfers are enabled, and the
loop executes at a lower priority level than the
DMC11 interrupts level.

3-10

3.4.5 Initialization
The power-up sequence and UNIBUS INIT signal initialize the DMC11. The PDP-11 program can
accomplish the same effect by setting MASTER CLEAR in BSEL1. Each of these procedures restarts
the microprocessor to the beginning of its microprogram. In this state, the microprocessor does not
send or receive messages on the serial line or generate output transfers.
When the PDP-11 program wants the DMC11 to function, it must perform an input transfer that
specifies the base address of a 128 word table in PDP-11 memory, which is called the base table. The
PDP-11 program requests the BASEI transfer by setting TYPEI to 11. In response to RDYI, the
program loads the low-order 16 bits of the address into SEL4 and the high-order 2 bits of the address
into bits 15 and 14 of SEL6. If the DDCMP protocol operation is to be initialized, the RESUME bit

(bit 13 of SEL6) must be clear.

Once the PDP-11 has specified a base address, the 128 word base table belongs to the microprocessor
until the DMCI11 is master cleared by INIT or MASTER CLEAR. The PDP-11 program may examine
the contents of the base table (for example, error counters relating to protocol operation) but must not
alter its contents.
By supplying a base address with the RESUME bit clear, the microprocessor is conditioned to
respond
to the DDCMP start-up sequence received from the remote system. However, the microproces
sor does
not initiate the start-up sequence on its own accord unless the PDP-11 program supplies a buffer of
data to be transmitted.

If the DMCI11 is connected to a half-duplex channel, the PDP-11 program must now perform an input
transfer using the Control In format and set the Half Duplex bit (HD) in SELG6 (bit 10). In addition,
the program must specify whether the DMCI11 is to operate as a half-duplex secondary station
(3second timer) or a half-duplex primary station (1-second timer) by setting or clearing the secondary
bit
(SEC) in SEL6 (bit 11). A half-duplex link must have one primary station and one secondary
station.
The only difference between the two is in the length of time spent before retransmitting in case of
errors. Half-duplex operation may be specified at any time by a Control In transfer to accommodat
e
switching to a half-duplex backup communications channel. The DMCl1 options containing the
integral modem must be specifically strapped for half-duplex operation, in addition to requiring the
Control In transfer.
3.4.6 DDCMP Start Up
Before data messages can be transmitted or received, the DDCMP start-up sequence must
be completed to make certain both ends of the link are correctly initialized and to place the protocol
in the
running state. Either end may initiate the start sequence or both ends may do so simultaneous
ly. If the
PDP-11 program supplies a buffer of data to be transmitted, the local DMC11 initiates
the start

sequence.

The PDP-11 program may ignore the details of the start sequence. However, one important property
of the sequence is significant. Once the local DMC11 has entered the running state, it detects and
flags

as an error the fact that the other end has initiated the start sequence. As a result, the PDP-11
program
receives a Control Out transfer with SEL6 bit 7 (DDCMP START REC’D) set. If this happens,
the
PDP-11 program knows that the other end of the link has restarted. The PDP-11
program should
initialize the DMC11 and begin again.

3-11

3.4.7

Data Transmission
When the PDP-11 program wishes to transmit a buffer of data, it clears bits 1 and 0 of BSELO to
indicate a Buffer Address/Character Count In transfer and clears bit 2 of BSELO (INI/0) to specify

that this is a full buffer to be transmitted. It then requests an input transfer by setting RQI. In response
to RDYT, it loads SEL4 with the low-oder 16 bits of the buffer address, bits 15 and 14 of SEL6 with the
high-order bits of the address, and bits 13 to 0 of SEL6 with the 14-bit character count. Buffers from 1
to 16,383 bytes long can be used for local operation. For remote operation, buffers should be limited to
a practical maximum of about 512 bytes, depending on the error rate of the communications facilities.
Each buffer corresponds to a single DDCMP data message.

When the message has been successfully transmitted and an acknowledgement received, the microprocessor Initiates an output transfer with bits 1 and 0 of BSEL2 clear to indicate the Buffer

Address/Character Count Out (BA/CC O) format. Bit 2 (OUT 1/0) is clear to indicate that a success-

fully transmitted buffer has been returned to the program.

The PDP-11 program may queue up to seven buffers for transmission by supplying buffers to the
microprocessor faster than it returns them. An attempt to queue more than seven buffers forces the

microprocessor to delay granting the request for the input transfer until a buffer has been returned.

NOTE
The PDP-11 program should not request an input
transfer that supplies a transmit buffer if seven are
already outstanding, unless it is certain that the other
end of the link can supply enough buffers for reception. In particular, if two PDP-11s connected by
DMCl11s attempt to queue up to eight buffers, while
no receive buffers are queued, they become deadlocked and must initialize their DMCl11s.
3.4.8

Data Reception
When the PDP-11 program has an empty buffer it wishes to fill with received data, it clears bits 1 and 0

of BSELO to indicate a BA /CC I transfer and sets bit 2 of BSELO (IN I/0) to specify that an empty
buffer has been made available for reception. It then requests an input transfer by setting RQI. In
response to RDY], it loads SEL4 and SEL6 with the buffer address and character count in the same
format as for transmission. The character count must be large enough to accommodate the longest
measure expected.

When a message has been successfully received and stored in the buffer, the microprocessor initiates an
output transfer with bits 1 and 0 of BSEL2 clear to indicate the BA /CC O format. Bit 2 (OUT I/0) is
set to indicate a full buffer has been received. SEL4 and SEL6 contain the address of the buffer and the
actual number of characters received.
If a message is received when no receive buffer is available, the microprocesor informs the PDP-11 by
means of a Control Out transfer, with bit 2 of SEL6 (O’RUN ERR) set. The other end of the link is
informed of the error and automatically retransmits the message. The PDP-11 program should supply

a buffer as soon as possible.

3-12

The PDP-11 may queue up to seven empty buffers for reception by supplying them to the microprocessor faster than it returns buffers. An attempt to queue more than seven buffers forces the microprocessor to delay granting the request for input transfer until a full buffer has been returned.

NOTE
The PDP-11 program should not request an input
transfer that supplies a buffer for reception if seven
are already outstanding, unless it is certain that the
other end of the link is supplying buffers for
transmission.
3.4.9 Control Out Transfers
The microprocessor informs the PDP-11 program of unusual or error conditions involving the communications channel, remote end of the link, DMC11 hardware, or PDP-11 program by means of an
output transfer with bit 1 of BSEL2 clear and bit 0 set indicating a Control Out (CNTL O) transfer.
SEL6 contains bits that indicate the error condition. Some errors are advisory in nature and normal
operation may continue. Others are fatal and require the PDP-11 program to initialize the DMC11.
Bit 0 (DATA CK) indicates that a retransmission threshold has been exceeded. (More than seven
consecutive retransmissions have occurred for transmission or reception.) This indicates a defective
communications channel or that the other end of the link has failed to supply a buffer for reception.

The PDP-11 can examine error counters in the base table for more details of the error. This is a nonfatal error. Should the cause of the error be corrected, normal operation continues with no messages
lost in either direction. This error may appear repeatedly until the condition is corrected or until the
DMCI1 is initialized. Transient errors corrected before seven retransmissions are not reported to the
PDP-11 program but are counted in the base table.

Bit 1 (TIME OUT) indicates that the microprocessor has received no response from the remote end of
the link for a specified period (21 seconds). This indicates a broken communications channel or a
failure at the other end of the link (possibly a power failure). Like DATA CK, this is a non-fatal error
that can occur repeatedly.

Bit 2 (O’RUN ERR) indicates that a message was received but no buffer was available. This is a nonfatal error. The PDP-11 program can prevent this error from recurring repeatedly by supplying a
buffer.
Bit 3 (DDCMP MAINT REC’D) indicates that a message in the DDCMP maintenance format was
received and that the protocol operation has entered the maintenance state.
Bit 4 (LOST DATA) indicates that a message was received that is longer than the buffer supplied by
the PDP-11 program. This is a fatal error.
Bit 6 (DISCONNECT) indicates than an on to off transition of the modem Data Set Ready
lead has
been detected (remote operation only). This is a non-fatal error. For dial-up operation, the PDP-11

program must consider the possibility that a new caller has connected to the DMC11,

by security considerations.

Bit 7 (DDCMP START REC’D) indicates that

if this is required

a DDCMP Start message was received when the

protocol was in the running or maintenance states. This indicates that the remote computer
has

initialized its end of the link. This is a fatal error. The PDP-11 program may initialize the DMCI1
wishes to start over and complete the start-up sequence.

3-13

if it

Bit 8 (NON EX MEM) indicates that a Unibus address time-out has occurred. This could have been
caused by the PDP-11 program specifying an invalid base address, buffer address, or count, which was
stored illegally in the base table or the PDP-11 memory, is defective. This is a fatal error.

Bit 9 (PROC ERR) indicates a procedure error on the part of the PDP-11 program. The requested
input transfer cannot be honored due to a programming error. This error can be caused by requesting

a BA /CC before supplying a base address, requesting a base address a second time, or specifying an
invalid code in BSELO bits 1 and 0. This is a fatal error.
3.4.10

Maintenance Messages
A special DDCMP message format, the Maintenance message, is used for down line loading, restart-

ing, or otherwise maintaining satellite computer systems. Messages in this format are subject to error
checking but are unsequenced, unacknowledged, and not retransmitted automatically by the DMCI11.
Transmission is always half-duplex.

Maintenance messages can only be sent and received while the microprocessor is in the DDCMP
maintenance state. The PDP-11 program may cause the microprocessor to enter this state by a CNTL I
transfer with bit 8 of SEL6 (DDCMP MAINT) set. The microprocessor enters the maintenance state if
a maintenance message is received. In this case, the microprocessor performs a CNTL O transfer with
DDCMP MAINT REC’D set in SEL6 to indicate the state change and availability of a maintenance
message.

Once in DDCMP maintenance mode, maintenance messages can be sent and received similarly to data
messages. On transmission, the data portion of the message is taken from the buffer with the DMC11

generating the header and CRCs. On reception only, the data portion is placed in the buffer. Messages
not in DDCMP maintenance format or having incorrect CRCs are simply discarded.
The data portion of the maintenance message may contain any data that is desired, but ordinarily it

conforms to the DIGITAL Maintenance Operation Protocol (M OP) formats. When a host computer
wishes to restart a satellite computer system, it must send the appropriate MOP messages as described
in the following paragraph.
[n order to leave Maintenance mode, the PDP-11 program must initialize the DMC11 and supply a
base address with the RESUME bit clear.
3.4.11
Remote Load Detect and Down Line Load
Whenever the microprocessor is running, it is constantly scanning the serial line for

a DDCMP

maintenance message containing an ENTER MOP MODE data field. What happens when this particular message is received depends on the setting of two switch packs on the DMCI11 line unit.

Depending on the setting of these switches, the DMCI11 will either commence down line loading in
MOP mode, trigger the PDP-11 to begin executing a program in a read only memory (ROM) bootstrap (BM873, M9301, etc.), or simply pass the data to the PDP-11 as an ordinary maintenance message. In case a ROM bootstrap is triggered, switches on the line unit specify an 8-bit word offset to the
bootstrap address space.
The data portion of the ENTER MOP MODE message is 5 bytes long. The first byte contains the
decimal number 6. The remaining 4 bytes contain the same 8-bit value. This value is specified by a

switch pack on the DMCI1 line unit and serves as a password to protect against inadvertent recognition of the ENTER MOP MODE message.
If an ENTER MOP MODE message is recognized and the switches specify to commence down line
loading, the DMC11 microprocessor takes over the PDP-11 computer system. All peripherals on the
system are initialized by an INIT sequence and the processor is placed into a tight loop where it
remains until control is transferrred to a program loaded down the line.

3-14

In response to the ENTER MOP MODE message, the DMC11 sends a REQUEST MOP SECONDARY MODE message in DDCMP maintenance format containing a data field 3 bytes long that

contains the decimal numbers 8.12.1. This informs the remote end that the ENTER MOP MODE
message was received.

The remote end should now send a MEMORY LOAD WITH TRANSFER ADDRESS message in
DDCMP maintenance format. The firt 2 bytes are zero, the next 4 bytes are an 18-bit memory address
right justified, followed by a memory image to be loaded and 4 bytes of transfer address.

Once this message has been successfully received, the DMCI11 starts the PDP-11 program at the specified transfer address. The DMC11 must be initialized before it does anything else except recognize a
subsequent ENTER MOP MODE maintenance message.
3.4.12 Power Fail Recovery
The DMCI1 keeps all data necessary to recover from a power failure in its base table. When the PDPI'l program detects a power failure, it should cease requesting input transfers and not respond to

output transfers. When power has been restored, the PDP-11 power recovery program can tell the
DMCI11 microprocessor to recover from the error by performing a BASE I transfer with the
RESUME bit set. The original base address must be specified and the contents of the base table must

be the same as they were when power was lost; otherwise, the program must start over (RESUME bit
clear). As part of the power recovery, the PDP-11 program must repeat an uncompleted input transfer.
It must set IEI and IEO as desired. The microprocessor repeats an uncompleted output transfer.

3.4.13 Data Set Control
If the switches on the DMC11 line unit specify bootstrap ROM triggering or down-line loading, the
microprocessor maintains Data Terminal Ready continuously, dropping it for a 1-second period following an on to off transition of Data Set Ready. Otherwise, the DMC11 does not turn Data Terminal
Ready on until it has received a base address. It drops Data Terminal Ready when initialized by INIT
or MASTER CLEAR and it drops it for 1 second following an on to off transition of Data Set Ready.
An on to off transition of Data Set Ready provides a CNTL O transfer as previously described, if the
DMCI11 has been given a base address.

3.5

MICROPROCESSOR CONTROL AND STATUS REGISTERS

3.5.1
Introduction
The Unibus CSRs described in Paragraph 3.4.2 are physically located in the multiport RAM. The
RAM capacity is 128 bits arranged as 16 8-bit bytes, which is equivalent to eight 16-bit words. The
RAM can be accessed simultaneously from two sources. One source is the Unibus and the other is the
microprocessor. Therefore, when these Unibus CSRs (BSEL1-BSEL7) are viewed from the micro-

processor, they are called Microprocessor CSRs. Specifically, they are identified as QUTBUS* /INBUS*
registers 0-7 (octal).

The remaining multiport RAM capacity, which is 8 8-bit bytes, contains the NPR Data and BA
registers. These registers are also called Microprocessor CSRs and are specified as QUT BUS /IN BUS

registers 0-7 (octal).

There are two additional byte sized hardware registers that are listed in the OUT BUS* /IN BUS*

category. They are the NPR Control register (105) and the Microprocessor Miscellaneous register

(11s).

3-15

The microprocessor has the capability of addressing 32 byte sized registers. As a convention, it has

been decided to show 16 assigned addresses under each category; that is, OUT BUS* /IN BUS* and
OUT BUS/IN BUS. As a result, six undefined registers 12-17 (octal) are listed under OUT BUS* /IN
BUS*. These registers do not exist physically. The line unit device registers, 10,17, have been added to
the OUT BUS/IN BUS category. These registers are physically located in the line unit. Address 10; is
listed twice because two line unit registers use the same address. The In Data Silo is read only and the
Out Data Silo is write only. Therefore, there are nine registers in the line unit.
The arrangement of the Microprocessor CSRs is shown in Figure 3-2.

]

BYTE 0

BYTE 1

BYTE 2

BYTE 3

3 | UNIBUS CSRs
AS VIEWED FROM

BYTE /

XFER /
BUS
RQ

;ECT
XX4

MICROPROCESSOR.

BYTE 4

BYTES

BYTE 6

BYTE 7

out | INBA | INBA

NPR (17

NPR

|16 | RMW | pa |1ONPRCONT

/ PGM | ouT | ouT | Ac | NON
o 11 4P MISC
A

CLK | BA17 | BA 16|

MEM

UNASSIGNED.

14 | ADDRESSABLE

>aur NOT

PHYSICALLY

15 | PRESENT.

16 REGISTERS ASSIGNED TO OUTBUS*/INBUS* CATEGORY
11 -4370

Figure 3-2

Microprocessor Registers

3-16

The detailed discussion of the Line Unit CSRs is contained in Paragraph 3.6.
3.5.2

OUT BUS*/IN BUS* Registers 0-7
These eight registers are identical to those described in Paragraphs 3.4.2.1 through 34.2.5.

3.5.3

NPR Control Register (OUT BUS*/IN BUS* 10)

Bit

Name

Description

NPR REQUEST
(NPR RQ)

This bit can be set only. It is automatically cleared by
the hardware when the NPR has been completed. When
set, this bit requests an NPR via the Unibus to the PDP11 memory. If OUT NPR (bit 4) is cleared, data is transferred from the PDP-11 memory. If OUT NPR is set,
data is transferred to the PDP-11 memory. Bit 7 (BYTE
XFER) controls word/byte selection.

For an IN NPR, the PDP-11 memory address is in OUT
BUS/IN BUS registers 4 and 5. For an OUT NPR, the
address is in OUT BUS/IN BUS registers 6 and 7. The
data that is associated with the transaction comes from
OUT BUS/IN BUS registers 2 and 3 for OUT DATA
and from OUT BUS/IN BUS registers 0 and 1 for IN
DATA. OUT NPR (bit 4) is Unibus Control line C1 and
BYTE XFER (bit 7) is Unibus Control line C0. When
BYTE XFER is set, the state of the BA least significant
bit (0) is used to select the byte. The truth table for the
type of transaction, as selected by these bits, is shown
below.
OUT NPR
(C1)

BYTE XFER
(CO0)

BAO

Unibus
Transaction

DATI

Illegal

DATO

DATOB (Low

Byte)
1

READ/WRITE (R /W)

1
Byte)

DATOB (High

This read/write bit provides no function and may be
treated in the microcode as a flag or state indicator.

3-17

Bit

Name

Description

2,3

IN BA 16 and
INBA 17

These are the PDP-11 memory extension bits used during an IN NPR (C1 = 0) transaction.

OUT NPR

This bit is used in association with NPR RQ (bit 0). The

details of the inter-relationship between these bits are
covered in the description of NPR RQ (bit 0).
5,6

RESERVED

BYTE XFER

This bit is used in association with OUT NPR to

indicate a byte transfer to the PDP-11 memory. When
this bit is set, the PDP-11 uses address bit A0 for byte
selection. If AOis a 0, OUT DATA 7-0 is stored in the
low byte of the PDP-11 memory. If A0 is a 1, OUT
DATA 7-0 is stored in the high byte of the PDP-11
memory.

If BYTE is cleared during an OUT NPR operation,
OUT DATA 15-0 is transferred to the PDP-11 memory
as a word.
3.5.4

Microprocessor Miscellaneous Register (OUT BUS*/IN BUS* 11)

Bit

Name

Description

NON-EXISTENT
MEMORY

During an NPR, this bit is set approximately 20 us after
a non-existent memory location is addressed by the
microprocessor. At this time, the NPR logic releases the
Unibus.

(NON-EX MEM)

ACLOW

This bit is a set only bit. When set, it triggers a 1-shot

with a pulse duration of 0.5 second. This pulse goes to
the Unibus and initiates a power fail recovery procedure
in the PDP-11 processor.
2,3

OUT BA 16 and
OUT BA 17

These are the PDP-11 memory extension bits used dur-

ing an OUT NPR transfer.

PROGRAM CLOCK | This bit acts as a timer for the microprocessor. It can be

(PGM CLK)

read to determine lapse time for time-out, flag testing,
etc.

This bit is the 0 output of a retriggerable 1-shot with a 1
second pulse duration. As long as the triggering pulses
come along at less than 1 second intervals, the 1-shot
remains asserted and this bit is read as a 0. If the 1-shot
times out, this bit is read as a 1.
5

RESERVED

3-18

Bit

Name

Description

VECTOR AT XX4

If this bit is set when BR RQ (bit 7) is set, vector address
XX4 is generated. If it is cleared when BR RQ is set,
vector address XXO0 is generated. Address XXO is associated with RDYI and address XX4 is associated with
RDYO.

BR REQUEST
(BR RQ)

When set, this bit initiates a Bus Request via the Unibus
at BR level 4, 5, 6, or 7. The microprocessor is shipped
with a BRS priority card installed. This bit can be set
only and is cleared by the hardware after the BR has
been completed.

3.5.5

NPR Bus Address and Data Registers (OUT BUS/IN BUS 0-7)

Name

0, 1

IN DATA

Description
Low byte (register 0) and high byte (register 1) of data to

be transferred from the PDP-11 memory.
2,3

OUT DATA

4,5

IN BA

Low byte (register 2) and high byte (register 3) of data to
be transferred to the PDP-11 memory.
Contains Bus Address (BA) bits 0-15 during an NPR

transfer from the PDP-11 memory. Bit 0 of register 4 is
BA bit 0 and bit 7 of register 5 is BA bit 15.
6,7

OUTBA

Contains Bus Address (BA) bits 0-15 during an NPR

transfer to the PDP-11 memory. Bit 0 of register 6 is BA
bit 0 and bit 7 of register 7 is BA bit 15.
3.6

LINE UNIT REGISTERS

3.6.1
In/Out Data Silo Registers (10)
The In Data Silo is loaded with eight bits of received data from the Receiver Data register. When the
microprocessor performs a read operation on this register, the data is presented to the IBUS.
Physically, the In Data Silo is in the form of a 64 word by 12 bit silo. The other four bits are considered
to be part of the In Control register.
When the microprocessor performs a write operation on the In Data Silo, nothing happens to this
register. However, the eight bits of data to be transmitted are taken from the OBUS and are presented

to the input of the Out Data Silo, which is a 64 word by 12 bit silo. The other four bits are considered
to be part of the Out Control register.

3-19

3.6.2

Out Control Register (11)

Bit

Name

Description

TSOM
(Transmit Start
of Message)

This bit is used to initiate the start of a new message.
DDCMP Mode: The Sync character must be loaded
into the Out Data Silo along with TSOM bit. This character is transmitted as the Sync character until TSOM is
cleared. Until it is cleared, the characters are not included in the CRC accumulation. When TSOM s cleared,
the present Sync character is transmitted and is followed
by data. All data is included in the CRC accumulation,
if CRC is enabled. Once TSOM has been set, the CRC
accumulation cannot be inhibited unless the line unit is
initialized.

Bit Stuff Mode: When TSOM is set, a flag character is

automatically transmitted. The character that is loaded

with the TSOM bit is lost. Flag characters are automat-

ically transmitted as long as TSOM is set. When data is
to be transmitted, TSOM is cleared and data is loaded
into the Out Data Silo. At the completion of the current
flag character, the actual transmission of data begins.
All information to be transmitted is included in the
CRC accumulation, if the CRC function is enabled.
This bit is program write only. It is cleared by the

_initialization logic and by the fact that data was loaded
into the Out Data Silo. It is loaded into the silo and
passed to the transmitter through the silo.

TEOM

(Transmit End
of Message)

This bit is used to terminate the message in progress and
control the transmission of the CRC character, if the
CRC function is enabled.
DDCMP Mode: When TEOM is set, the CRC character

is transmitted. If no more messages are pending (TSOM
cleared), the transmitter is shut down.

Bit Stuff Mode: When TEOM is set, the character
loaded with it is lost. The CRC character is transmitted.
If no more messages are pending, the transmitter is shut
down by having a second TEOM in the silo. This generates a single closing or intermessage flag.
This bit is program write only. It is cleared by the
initialization logic and by the TSIP flip-flop, which is set
whenever data is loaded into the Out Data Silo.

3-20

Bit

Name

‘Description

2,3

Reserved

These bits are program write only. They are cleared by
the initialization logic and by the TSIP flip-flop, which
is set whenever data is loaded into the Out Data Silo.
These bits and bits 0 and 1 are passed to the transmitter
through the silo every time register 10 is written into;
therefore, if the CONTROL IN format is to be sent,
these bits must be written before register 10 is written
into.

OUT RDY
(Out Ready)

When asserted, this bit informs the microprocessor that
the transmitter is ready to accept data. It indicates that
space is available in the Out Data Silo. The microprocessor loads the Out Data Silo and then reads OUT
RDY. The speed of the microprocessor allows OUT
RDY to be read and interpreted as true before the silo
has loaded the data. Therefore, one cycle must elapse
between loading the silo and reading OUT RDY.

This bit is read only.
Reserved

Read only. Physically, this bit is a switch.

OUT ACTIVE

OUT ACTIVE informs the microprocessor of the status
of the transmitter. When it is set, the transmitter is
active.
This bit is read only. It is set by the hardware and
cleared by the initialization logic.

OCLRP

(OUT CLEAR)
3.6.3

This bit is used to clear all the transmitted functions.

OCLRP is program write only.

In Control Register (12)

Bit

Name

Description

BCC MATCH
(Block Check

BCC MATCH is the output of the receiver CRC error
logic that monitors the contents of the CRC register.

Character Match)

With the CRC function enabled, BCC MATCH is
asserted at the end of an errorless message. In the
DDCMP protocol, the contents of the Receiver CRC
register equal zero when an errorless message has been
received. In the SDLC protocol, the contents of the
Receiver CRC register equal 016417.

This bit is read only and is updated everytime register 10
is read.

3-21

Bit

Name

Description

BLOCK END

BLOCK END is used to inform the microprocessor, in
SDLC mode, that a terminating flag has been received.
This flag may be the leading flag for the next message.
The BLOCK END bit is loaded with the high byte of the
CRC character; therefore, the BLOCK END bit, along
with the BCC MATCH bit, should be used to indicate
reception of a good message.
This bit is read only and is not used in the DDCMP
mode. It is updated everytime register 10 is read.

2,3

Reserved

When asserted, this bit informs the microprocessor that
received data is ready for processing. It indicates that
data is available at the output of the In Data Silo.
This bit is read only.

ALT LU LOOP
(Alternate Line
Unit Loop)

During maintenance, this bit is set to loop the receiver
on the transmitter with no connection to the modem
control lines.

This bit is program read /write.
IN ACTIVE

When asserted, this bit informs the microprocessor that
the receiver is in the data reception mode; that is, it is
receiving data or CRC characters.

DDCMP Mode: IN ACTIVE is asserted upon receipt of
the first non-sync character.

SDLC Mode: IN ACTIVE is asserted upon receipt of
the first data character.
ICLRP
(In Clear)

This bit is used to clear all the receiver functions.
ICLRP is program write only.

3.6.4

Modem Control Register (13)

Bit

Name

Description

SECURE

The function of this bit is reserved for future use. This
read only bit is selected by a switch. SECURE is
asserted when the switch is OFF (open).

The function of this bit is reserved for future use. This

read only bit is selected by a switch. SW is asserted when
the switch is OFF (open).

3-22

Bit

Name

‘Description

CS
(Clear to Send)

The CS bit informs the microprocessor of the state of
the modem Clear to Send line. This bit and MODEM
RDY (bit 3) must be asserted simultaneously to generate
SEND, which is the transmitter enabling signal.
This bit is read only.

MODEM RDY
(Modem Ready)

The MODEM RDY bit informs the microprocessor of
the state of the Modem Ready line. On the M8201 L ine
Unit, this signal can be held asserted permanently
through the use of a jumper. On the M8202 Line Unit,
this signal is asserted when power is turned on.
This bit is read only.

HDX
(Half Duplex)

The HDX bit is used to put the line unit in the halfduplex mode. When this bit and the Request to Send bit
are asserted, the receiver clock is inhibited, which blinds
the receiver during operation in the half-duplex mode.
This bit is program read/write and can be directly
cleared by the clear signal from the microprocessor.

RS
(Request to
Send)

The RS bit informs the microprocessor of the state of
the modem Request to Send line. This bit is controlled
by the line unit logic and not by the microprocessor. It is
cleared by absence of data or by the initialization logic.
This bit is read only.

DTR
(Data Terminal
Ready)

The DTR bit enables the modem via the Data Terminal
Ready line. This bit is program read /write. It is directly
set by the initialization logic but it can be cleared only
by writing a 0 into it.

RING

The RING bit informs the microprocessor of the state
of the modem Ring line. RING is inhibited on the
M8202 Line Unit.
This bit is read only.

3.6.5 Sync Register (14)
The Sync register is an 8-bit program read/write register.
DDCMP Mode: The register is loaded with a program selectable sync character.

Bit Stuff: In the secondary mode, this register is loaded with secondary station address. This 8-bit
character follows the initial flag in the SDLC message format.

3-23

3.6.6 Switch Selectable Registers (15 and 16)
Both of these registers are DIPs containing eight switches each. The program determines the function
of both registers.
3.6.7

Maintenance Register (17)

Bit

Name

Description

MODE

The MODE bit selects the protocol (DDCMP or Bit

Stuff families). When set, DDCMP is selected; when
cleared, Bit Stuff is selected.

During initialization, the CLEAR signal from the
microprocessor sets this bit to select DDCMP. This bit
can be cleared (SDLC selected) only by writing a 0 into
it.

This bit is read /write.
|

ESC
(Internal Clock)

ECS is the output of the internal RC clock (approximately 10 kHz). This bit is read only.

Reserved

Read only.

ICIR
(In Composite
Input Ready)

When asserted, this bit indicates that the In Data Silo is
ready to accept data.

This bit is read only.
4

OCOR
(Out Composite
Output Ready)

When asserted, this bit indicates that data is ready at the
output of the Out Data Silo.

This bit is read only.
5

(Serial Input)

SI is the serial input data from the modem.

This bit is read only.
6

(Quotient In)

QI is the least significant bit of the Receiver CRC

This bit is read only.
7

(Quotient Out)

QO is the least significant bit of the CRC register.

This bit is read only.

3.24

APPENDIX A
PDP-11 MEMORY ORGANIZATION

AND ADDRESSING CONVENTIONS

The PDP-11 memory is organized in 16-bit words consisting of two 8-bit bytes. Each byte is addressable and has its own address location; low bytes are even numbered and high bytes are odd numbered.

Words are addressed at even numbered locations only and the high (odd) byte of the word is automat-

ically included to provide a 16-bit word. Therefore, consecutive words are found in even numbered
addresses. A byte operation addresses an odd or even location to select an 8-bit byte.

The Unibus address word contains 18 bits identified as A(17:00). Eighteen bits provide the capability
of addressing 256K memory locations, each of which is an 8-bit byte. This also represents 128K 16-bit
words. In this discussion, the multiplier K equals 1024, so that 256K represents 262,144 locations and

238K represents 131,072 locations. The maximum memory size can be used only by a PDP-11 processor with a memory management unit that utilizes all 18 address bits. Without this unit, the processor
provides 16 address bits, which limits the maximum memory size to 64K (65,536) bytes or 32K (32,768)

words.

Figure A-1 shows the organization for the maximum memory size of 256K bytes. In the binary system,
18 bits can specify 2!8 or 262,144 (256K) locations. The octal numbering system is used to designate the
address. This provides convenience in converting the address to the binary system that the processor
uses as shown below.
The highest 8K address locations (760000-77777) are reserved for internal general registers and peripheral devices. There is no physical memory for these addresses; only the numbers are reserved. As a
result, programmable memory locations cannot be assigned in this area; therefore, the user has 248
bytes or 124K words to program.
A PDP-11 processor without the memory management unit provides 16 address bits that specify 216 or

65,536 (64K) locations (Figure A-2). The maximum memory size is 65,536 (64K) bytes or 32,768 (32K)
words. Logic in the processor forces address bits A(17:16) to 1s if bits A(15:13) are all 1s when the

processor is master to allow generation of addresses in the reserved area with only 16-bit control.

]

| ADDREssBIT

BINARY

OCTAL

11 -4401

l15

o8 |o7

00|

le— 16 BIT DATA WORD —|

000001

HIGH BYTE

LOW BYTE

000000

000003

000002

USER ADDRESS SPACE
AMAILABLE USING 18

|
|

ADORESS BITS ON
POP-11 PROCESSOR

MANAGEMENT OPTION.

WITH MEMORY

INCLUDES 248K (253,952)
BYTES OR 124K (126,976)
WORDS.

57777

757776

760001

76 0000

L__—
———]

HIGHEST 8K (8192)

—~
j

BYTES OR 4K (4096)
WORDS RESERVED FOR

DEVICE REGISTER
ADDRESSES.

*7 17777

777776

ALAST ADDRESS IS BYTE NUMBER 262,143,
MAXIMUM SIZE WITH 18 ADDRESS BITS IS

256K(262,144) BYTES OR 128K (131,072) WORDS.
11-1690

Figure A-1

Memory Organization for Maximum Size Using 18 Address Bits

s
oslo7
le— 16 BIT DATA WORD

000001
000003

HIGH BYTE

LOW BYTE

000000
000002

USER ADDRESS SPACE
AVAILABLE

USING 16

ADDRESS BITS ON

|
)

PDP-11

—

PROCESSOR

WITHOUT MEMORY

)

MANAGEMENT OPTION.
INCLUDES 56K (57,344)
BYTES OR 28K (28,672)
WORDS.

157777

157776

160001

160000

fi
ADDRESSES 160000-

177777 ARE CONVERTED
TO 760000 -777777 BY
"

THE PROCESSOR. THUS,

THEY BECOME THE
HIGHEST 8K (8192) BYTES

OR 4K(4096) WORDS

*177777

177776

RESERVED FOR DEVICE
REGISTER ADDRESSES.

LAST ADDRESS IS BYTE NUMBER 635,535,
MAXIMUM SIZE WITH 16 ADDRESS BITS IS 64K (65,536) BYTES OR 32K(32,768) WORDS.
It-1689

Figure A-2

Memory Organization for Maximum Size Using 16 Address Bits
A-2

Bit 13 becomes a 1 first at octal 160000, which is decimal 57,344 (56K). This is the beginning of the last
8K bytes of the 64K byte memory. The processor converts locations 160000-177777 to 760000-777777,
which relocates these last 8K bytes (4K words) to the highest locations accessible by the bus. These are
the locations that are reserved for internal general register and peripheral device addresses; therefore,
the user has 57,344 (56K) bytes or 28,672 (28K) words to program.
Memory capacities of 56K bytes (28K words) or under do not have the problem of interference with
the reserved area, because designations less than 160000 do not have a binary 1 in bit A13. No address-

es are converted and there is no possibility of physical memory locations interfering with the reserved
space.

PDP-11 core memories are available in 4K or 8K increments. The highest location of various size core
memories is shown below.

Memory Size
K-Words
K-Bytes

4
8
12
16
20
24
28

8
16
24
32
40
48
56

Highest Location

(Octal)
017777
037777
057777
077777
117777
137777
157777

A-3

DMC11 IPL MICROPROCESSOR

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