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Document:	DMC11 IPL Synchronous Line Unit Maintenance Manual
Order Number:	EK-DMCLU-MM
Revision:	001
Pages:	218
Original Filename:

OCR Text

DMC11 IPL
synchronous line unit
maintenance manual

dlifgliltiall

EK-DMCLU-MM-001

fl.d‘""

DMC11 IPL
synchronous line unit
maintenance manual

digital equipment corporation - maynard, massachusetts

Preliminary Printing, May 1976

The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in US.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC

DECCOMM

DECUS

DECtape

PDP

DECsystem-10

DIGITAL

TYPESET-8

DECSYSTEM-20

MASSBUS

RSTS
TYPESET-11

UNIBUS

- et

CONTENTS
Page

CHAPTER 1

INTRODUCTION

1.1

SCOPE

DMC1l1l LINE UNIT GENERAL DESCRIPTION
DMC11l LINE UNIT SPECIFICATIONS
1.4

GENERAL DESCRIPTION

1.4.1

Introduction

1.4.2

Operating Modes

1.4.3

Microprocessor-Line Unit Data Path

1.4.4

Transmitter

1.4.5

Receiver

1.4.6

Signal Conversion and Maintenance Logic

1.5

BASICS OF CYCLIC REDUNDANCY CHECKING

1.5.1

Mathematical Background

1-10

1.5.2

Hardware Implementation of CRC

1-13

1.5.3

CRC Operation in DDCMP Protocol

1-14

1.5.4

CRC Operation in SDLC Protocol

1-15

CHAPTER 2

INSTALLATION
SCOPE

UNPACKING AND INSPECTION

PREINSTALLATION SETUP PROCEDURE
INSTALLATION AND CHECKOUT

JUMPER AND SWITCH CHECKLIST
LOCAL LINK CABLE

CONTENTS

2.6.1

Selection

2.6.2

Installation

2.6.3

Maintenance

2.7

CHAPTER

FULL DUPLEX/HALF

(CONT)

DUPLEX OPERATION

PROGRAMMING

3.1

INTRODUCTION

3.2

3.3

3.3.1

Data

3.3.2

Out

3.3.3

3.3.4

Modem Control

3.3.5

Sync Register

3.3.6

Switch

Silo Registers
Control

Control

(R15
3.3.7

CHAPTER

DETAILED

Registers

and R16)

PROGRAMMING

Selectable

Maintenance

3.4

PROCEDURES

DESCRIPTION

4.1

INTRODUCTION

4.2

FUNCTIONAL DESCRIPTION

4.2.1

Logic

Description

4.2.2

Major

Operating Features

4.3

DETAILED DESCRIPTION

4.3.1

4.3.2
4.3.3

Introduction

Registers
Out

SELECTION

Control

Logic

CONTENTS

(Cont)

In Bus Control Logic

Transmitter Control Logic
Receliver Logic
4-107

CRC Logic

Data Set Interface Logic

(M820l1 Only)

4-122

Maintenance Logic

4-127

4.3.10

Initialization Logic

4-135

4.3.11

Integral Modem

4-136

CHAPTER 5

(M8202 Only)

MAINTENANCE

SCOPE

MAINTENANCE PHILOSOPHY
PREVENTIVE

MAINTENANCE

TEST EQUIPMENT REQUIRED
CORRECTIVE MAINTENANCE

CHAPTER

INTRODUCTION

1.1

SCOPE

te
This manual provides the information necessary to install, opera
ers
and maintain the DMC11 Line Unit. It is organized into five chapt
and one appendix as

follows.

Chapter

Introduction

Chapter

Installation

Chapter 3 - Register Descriptions and Programming Information
Chapter 4 - Detailed Description
Chapter

Maintenance

Appendix A - Integrated Circuit Descriptions

This chapter provides a general description of the two basic

variations of the DMC11 Line Unit.
and the local unit (M8202).
Redundancy Checking

1.2

DMC11

They are the remote unit (M8201)

Some background material on Cyclic

(CRC) methods is presented also.

LINE UNIT GENERAL DESCRIPTION

The DMC11 Network Link consists of a synchronous line unit that is
controlled by a microprocessor.

The DMC11 is used to interconnect

PDP-11 computers in local and remote network applications.

This

manual

circuitry

covers

they

are

only

DDCMP.

controlled

and

module

contains

EIA/CCITT

and

the

for

both

and

level

with

both

V24

shipped

speed

the

56K

bps.

DMC11-MA

and

DMC11-MD

these

6000

speed

not

LINE

and

CCITT

that

with

Units

(Local)

built-in

option

coaxial

speed

18,000

SPECIFICATIONS

handles

56K

feet.

that

and

the
bps

The

the

speed

maximum

module

operates

maximum

DMC11-MD
over

The

only

that

has

maximum

cable

for

M8201.

interfaces.

M8202-YA.

cable

V35

modems.

designation

UNIT

contain

However,

accommodates

shipped

Line

logic

has

either

Mode

Format

cable

with

Line

and

interface

module

which

units

conversion

V35

distance

DMC11-MD

line

CCITT

over

operates

maximum

Operating

Data

these

unit

have

all

protocols.

line

DMC11-MA

bps

The

units

the

feet.

included

DMC11

DMC11-MA

for
of

M8202-YB.
up

line

Stuffing

They

(Remote)

V24

This

DMC11-FA

only

with

interface.

The

designation

EIA/CCITT

unit.

Microprocessor

designation

bps.

DMC11-AD

control

line

Bit

Units

accommodates

Both

1.3

DDCMP

the

Line

DMC11-DA

19.2K

DMC11-FA

modem

compatible
The

models

accommodate

DMC11-DA

The

four

distance

option

coaxial

cable

option.

Units

(Local)

Half

duplex

(single

full

duplex

(two

Synchronous

/-2

cable),

cables)

serial

bit,

LSB

first

Size

Character

Check

Block

bits

CRC-CCITT

modified
Data

Distance

Maximum

Modulation

Timing

Transmitter

bps

(DMC11-MD)

6,000

feet

(DMC11-MA),

Line

Common

Mode

Transmitter
Receiver
Cable

RC Osc.,

trimmable 5%

Rejection

500

Signal

received

(min.)

P-P

(min.)

Type

AMP

20606X

Mounting

Space

One

hex

SPC

backplane

Consumption

and

Operating

in.)

Size

Channel

use

end

modules

slots

cut-

low height

the M930.

-15

.018

+15

(Remote)
or

half

duplex

Private

wire

Ssynchronous,
8

C or D),

provided the Unibus

contain

(DD11B,

well,

.046

Full

Mode

Format

Character

(€ 2.5

DMC11-FA Line Units

Communications
Data

slots

slot

in/out

3.0

(not supplied)

series

out permits

DMC11-DA

P-P

Belden 8232 or equivalent

Type

Connector

Power

signal

coupled

volts

150

Signal

NR2Z

freg.)

(double

Transformer

interface

(DMC11-MD)

feet

Diphase

From

Timing

(DMC11-MA),

56,000

18,000

Receiver

bps

1,000,000

Rate

and

CRC-16

bit polynomials:

bits

/-3

switched

serial

by bit,

LSB

first

Block

Check

bit

polynomials:

modified
Data

Rate

Interface

CRC~-16

CRC-CCITT

19,200

bps

(DMC11-DA)

56,000

bps

(DMC11-FA)

RS232C

and

CCITT

(DMC11-DA),

V.24

CCITT

compatible

V35

compatible

(DMC11-FA)
Modems

Bell

208,

209

equivalent

(DMC11-DA)
Signals

Supported

Cable

Mounting

Space

transmit

serial

clock

receive

data

serial

clock

data

set

data

terminal

request

clear

ring

One

data

foot

with

EIA

hex

SPC

slot

permits

ready

connector

supplied

(DD11B,

use

well,

M930.

3.2

.31

=15

.03

+15

end

in.)

D),

slots

provided

(S 2.5

the

/-4

(SCR)

send

in/out height

Consumption

(SCT)

ready

send

backplane

Power

receive

cutout

transmit

the

Unibus

modules

1.4

1.4.1

This

GENERAL

DESCRIPTION

Introduction

section provides a general description of the M8201

A more detailed description at the function level

Line Units.
in

The DMC11

Line Units

Serial

In addition,
Modem

Cyclic

and M8202)

perform the standard functions

communications device.

data

conversion.

parallel

data

conversion.

SYNC

1is

Description.

serial

character

Leading

(M8201

synchronous

associated with a
Parallel

Detailed

Chapter

contained

SYNC

and M8202

They are:

detection.

character

stripping.

the line units can perform the following functions.

control

and

monitoring

redundancy character testing.

Zero

bit

stuffing

Zero

bit

stripping

Automatic

flag

transmission.

Automatic

flag

recognition.

Automatic

abort

sequence

transmission.

Automatic

abort

sequence

recognition.

Automatic

pad

character

transmission.

1.4.2

Operating

The

line

units

The

modes

are:

DDCMP

Modes

may

mode

using

the

using

data

set

1.4.3

The

following

the

8-bit

highly

microprogrammable

byte

mode

efficient
Message

byte

modes.

operation.

oriented.

Protocol

(DDCMP)

polynomial.

This

designed

for

the

and

abort

flag

two

bit

oriented

sequences

mode

message

and

the

operation.

protocols

modified

polynomial.

local

data

link)

discussion

path

and

Line

between

vice

Unit

keyed

the

microprocessor

and

versa.

Data

Path

the

block

diagram

shown

4-1.

microprocessor

unidirection
from

the

provides

(or

either

Communications

mode

Microprocessor

Figure

The

unit

for

CRC-16

CRC-CCITT

line

This

Data

Bitstuff

The

designed

Digital

operate

the

data

and

line

paths.

microprocessor

The

line

unit

Unit

the

line

Bus

control

the

ALU

line

registers.

signals

IBUS).

communicate

Signals

communicates

(LU

unit

The

CROM

with

unit.
The

0-3.

the

0-7

/=6

two

comprise
The

data

Signal

the

line

unit

passed

OBW

microprocessor

registers.

through

controls

data

path

appears

the

strobe.

through

all

correct

the

reading

Line

signals are passed to the Maintenance and

Various maintenance

receiver

and

signals

These

logic.

Miscellaneous

transmitter

the

control

maintenance

functioning

the

mode.

Transmitter

1.4.4

The transmitter portion of the line unit consists of three functional
groups

logic.

They

Out

Transmitter

Control

Transmitter

CRC

The

functions

are

The

Out Data

Silo

silo

Logic

specific parts of the transmission function.

explained

seen

below.

a write only register to the micro-

The Transmitter Control

processor.

the

Silo

Data

logic performs

This

arez:

word

Transmitter

The hardware

deep data path between

Control

The

devices.

(First

In/First

of the

speed difference between

data available
which

every

characters
one

can be

timers

effect

silo

load

characters

and

order

is necessary because

Because of the

the

speed

know when

/=7

at which

there must be

relieve

speed with

(conceivably,

facilities,

(using dial up

order

FIFO

serialization process and the

160 microseconds),

and

is through the use of

silo

the

nanoseconds)

Additionally,
have

could

serialized

character every

buffer.
need

300

The

a buffer.

the microprocessor

from the microprocessor.

the microprocessor

character

it as

logic.

implementation of this
Out)

sees

logic

the

approximately

a multicharacter

the microprogram
to

load

one

the

another message

Oor

when

end

Message

and

EOM

typical

message,

sequence

End

the

transmitter

Message)

operation

Microprogram

loads

SOM

Microprogram

loads

data

The

Request

into

detects

send

siloed

bits

(SOM

Start

also.

is:

Transmitter

are

control

the

into

Out

the

Control

Out

Data

Silo.

SOM

the

silo

asserted

the

transmitter,

output.

automatically.

Clear

The

long

Send

and

transmitter

the

SOM

bit

Data

Set

enabled.

true,

the

included

the

When

Control

detects

SOM

set,

includes

it,

the

without

the

characters

When

EOM

CRC

The

detected,

computation

1.4.5

bit

(called
is

come

true.

Serialization

data

being

begins.

serialized

not

computation.

following

Character

CRC

Ready

the

BCC).

character

CRC

available

that

from

character,

the

and

silo

all

the

computation.

Control

transmits

data

the

follows

CRC
the

Check
EOM,

new

begun.

Receiver

receiver

groups

portion

the

logic.

They

Silo

Receiver

Control

Receiver

CRC

Data

line

unit

are:

Logic

/-&

consists

three

functional

This logic performs specific parts of the receive function.

The

functions are explained below.

seen by the microprocessor as a read only
The Rx Control sees it as an output buffer. The silo

The In Data Silo is
register.

is a 64 word deep data path between the Rx Control and the
microprocessor.

The hardware implementation of the silo is similar to that used
in the transmitter. Input to the In Data Silo is controlled by the
Rx Control while output is controlled by the microprogram. The
silo is present for the same reasons mentioned in the discussion
of

transmitter.

the

A typical sequence of operations is:

The receiver becomes active after detecting the first
data character preceded by two or more synchronizing

sequences (one flag sequence in the case of Bit Stuff
.
mode)

The data character is included in the CRC computation
automatically.

The data character is loaded into the silo by the Receive
Control.

The microprogram detects (by bit testing) both In Active
and In Ready (bits 6 and 4, respectively, of the In

Control register).

/--_9

The

microprogram

The

silo

7 .

The

microprogram,

1.4.6

The

the

BCC

the

bit

Bit

Stuff

with

Signal

signal

clock

receiver

data

BASICS

1.5.1

the

code

Block

Check

equal

the

data

bit

Silo.

with

each

subsequent

determined

(bit

message

mode,

the

Block

Match

and

bit,

the

had

the

bit

Maintenance

maintenance

for

End
if

when

the

character.

message

Control

detected

(Bit

errors

errors.

were

ends,

R12)

detected.

Logic

logic

transmitter

provide
and

automatic

receiver,

and

modem
the

REDUNDANCY

consists

Character

then

CHECKING

Background

message

total

bits;

having

Data

the

and

CYCLIC

Mathematical

cyclic

Rdy

source.

the

set,

BCC

sources

Match

Conversion

conversion

control,

1.5

presents

checks

set

reads

(BCC)

number

n-k

that

bits

equals

the

/=10

specific

number

computed

the

number

message

bits

the

and

data

CRC

bits

and

logic.

Let

equal

the

BCC.

the

number

The code message is derived from two polynomials which are algebraic
representations of two binary words, the generator polynomial P (X)
and the message polynomial G(X).
type of code used

The generator polynomial is the

(CRC-12, CRC-16, CRC-CCITT etc.);

polynomial is the string of serial data bits.

the message

The polynomials are

usually represented algebraically by a string of terms in powers of

X such as XD...+ X3 + X2 + X + XO (or 1).

In binary form, a 1 1is

placed in each position that contains a term; absence of a term 1is
The convention followed in this manual is to

indicated by a 0.

place the least significant bit (XO) at the right.

For example, 1if

a polynomial is given as x4 + X + 1 its binary representation is
10011

(3rd and

2nd degree terms are not present).

Given a message polynomial G(X) and a generator polynomial P (X), the
objective is to construct a code message polynomial F (X)
evenly divisible by P (X).

bits

the

BCC.

The resulting product xh-k [Gg(X)] is divided by the
generator

It is accomplished as follows:

Multiply the message G(X) by xN-K yhere n-k is the number
of

that 1is

polynomial

P (X).

The quotient is disregarded and the remainder C(X)

1is

added to the product to yield the code message polynomial

'as xN-K [g(x)] + C(X).
F(X), which is represented

/=//

The

division

this
The

case,

the

remainder

therefore,
number

simple

performed

remainder
is

bit

bits

example

always

BCC

and

the

divisor

length

the

BCC

the

generator

explained

polynomial

Generator

one

bit

carries

less

than

the

always

borrows.

the

generator

one

less

polynomial;

than

the»

below.

P(X)=11001

G(X)

contains

data

bits

P(X)

contains

bits

and

Multiplying

binary

and

This

will

the

message

(x4

yield

BCC

x
+

XO)

with

bits;

G (X)

this

product

1100110000.

xn-k

gives:

(x5 + x4 + x + x0)=x9 + x8 4+ x5 4+ x4

equivalent

product

n-k=4

1g(x)1=x%

The

(X5

divided

P (X)

/=/2

contains

divisor.

polynomial.

G(X)=110011

polynomial

therefore,

without

Given:

Message

binary

the

bits

t
01
mgg—=s quotien
1000

P (X)=$*11001

F1001100£4—-xn‘k [G(X)]
11001
10000

11001

r=C
(X)=BCC
1001 sg—~—= Remainde

The remainder C(X) is added to xn"k [G(X)] to give
F(X)=1100111001.

The receiving station

The code message polynomial is transmitted.

divides it by the same generator polynomial;

if there is no error,

the division will produce no remainder and it is assumed that the
message 1is correct. A remainder indicates an error. The division
is

shown

below.
100001
e
e

P(X)~911001

[1100111001 @ — F (X)
11001

Syl

11001

Snsssmsmtepssannih

00000 @~

1.5.2

remainder

Hardware Implementation of CRC

The BCC is computed and accumulated in a shift register during
transmission. Another shift register is used during reception to

examine the received data and BCC.

In each register, the number of

stages is equal to the degree of the generating polynomial. In the
line unit, the registers have 16 stages because 16 degree generating

polynomials are used.

SDLC uses code CRC-CCITT whose generator

/=13

polynomial
generator

Both

the

that

Under

x12

and

the

and

only

protocol

jindicates

errors

1.5.3

CRC

Operation

Under

DDCMP

Os.

the

bit

transmitter

the

BCC

does

registers

for

character

the

message

even

sending

DDCMP

control,

CRC

1.3.4.1

operation

Mathematical

being

transmitted

information

has

receiver

BCC),

the

flag

been

code.

received,

error

CRC

not.

locate

the

errors.

requested

CRC

the

reads

and

exactly

that

are

initialized

CRC

accumulates

transmitted,

the

BCC.

contents

all

accepts
When

the

transmitted.

the

message

been

are

station,

plus

asserts

logic

selected

control

Background.

transmitter

logic

the

whose

Protocol

station,

read

have

station

sending

the

CRC-16

enumerate

registers

CRC

code

CRC

should

the

CRC

configured

whether

the

receiver

(information

present,

and

receiving

examined

nor

Paragraph

information

last

x15

uses

message.,

protocol

transmitter

DDCMP

receiver

discipline,

the

The

X106

+1,

accompanying

re-transmit

registers

correct

described

transmitter

message

not

logic

does

polynomial

allows

When

CRC

information

contents
1is

non

the

1€

bit

BCC

the

end

the

message

the

errorless.

plus

receiver
The

CRC

the

flag

not

and

/=/F

error

reads

error

detection

asserted.

The

line unit does not count characters so it is the program's

responsibility to look for the CRC error flag at the proper time.

1.5.4

CRC Operation

in SDLC Protocol

Under SDLC protocol control, CRC operation is slightly different than
that described in Paragraph 1.3.4.1 Mathematical Background.
differences

The

are:

The factor x X (X15 + X14...+ X + 1) is added to Xn—k[G(X)]
which corresponds to initializing the transmitter CRC
register to all

1s.

This function 1is equivalent to

inverting the first 16 bits of G(X).

This allows detection

of the addition or delefiion of 0s at the leading end of the
message

due

erroneous

flag

characters.

The accumulated BCC, which is called Frame Check Sequence

in the SDLC mode,

(FSC)

This results in a unique non-0 remainder

transmitted.

(016417g)

is complemented before being

at the receiver.

This allows detection of the

erroneous addition or deletion of 0s at the trailing edge
of

the

message

due

errors.

At the receiving station, the receiver CRC register is
initialized to all

1s.

The information plus the FCS

constitutes the message and it is added to x X
(x12> + x14. .4 X + 1) and divided by P(X)
if the transmission is errorless.
the

flag

asserted.

/=/5

to give 016417g,

If an error is present,

—

CHAPTER

INSTALLATION

2.1

SCOPE

This chapter provides information for installation and checkout of
the

2.2

M8201

line

M8202

and

INSPECTION

AND

UNPACKING

units.

The line unit comes in four versions which are described below.

DMC11-DA

EIA/CCITT V24

(For

Line

M8201

BC05C-25

DMC11-FA

(For

M8201

or
-

DMC11-MA

Interface)
Module

Unit

BC08S-1
Modem

Test

(Local

Interconnect Cable

Cable

CCITT V35

BC05Z~-25

Connector

Line

BCO8R~-1
H

Modem

Test

H325

Module

Unit

BCO08S-1

BCO8R-1

Interface)

Interconnect

Connector

1M bps)
Line Unit

Module

M8202-YA

BCO8R~-1

BC08S-1

Interconnect

12-12528

Coaxial

Test

DMC11-MD (Local
M8202-YB BCO8R-1 or
12-12528

Inspect these parts
immediately to

the

Cable

bps)
Unit
BC08S-1 -

Cable

Connector

56K

Line

Coaxial

Module

Interconnect

Test

Cable

Connector

for visible damage.

Report any damage Or shortage

shipper and the DEC representative.

2.3

PRE-INSTALLATION

SETUP

PROCEDURES

NOTE
The

line

unit

DMC11~-AD
assumed

and

‘"/j

cannot

function

Microprocessor
that

checked

the

Installation

(M8200).

DMC11-AD

out

without
It

the
is

has

been

installed

accordance

with

Chapter

Microprocessor

manual

(EK-DMCUP-MM-001)
.

Before
be

sure

installing
that

they

line

are

unit,

the

check

normal

the

jumpers

and

switches

configuration.

Jumpers

The

M8201

M8202

Line

Unit

the

components

the

jumpers.

contains

location

five

six

drawing

normal

2-1

for

the

Switch

Packs

No.

and

No.

Switch

packs

no.

and

no.

are

and

Table

pack

no.

the

Unit.

the

M8201

Switch

location
on

E88

M8202

Line

Unit

pack
on

no.

the

ILine

Jumper

M8201

and

2-2

(W1-W5).

(W1-W6).

the

Table

set

for

switch

installed

location

Unit

are

2-2

both

E90

and

The

Refer

configurations

Line

Unit.

jumpers

The

the

locate

described

M8202.

DIPs.

Switch

location

the

ES87

M8202

installed

location

E91

Line

2-1

Table
M8201

rr"»

Jumper

Normal

Number

Configuration

Installed

Configurations

Jumper

Function

character

CRC

and CCITT under

CRC-16

and Bit Stuff

DDCMP

discipline of

the

proper

ensure

1in

codes

operation of
b

gate.

must

jumper

This

the CRC

inverted by

not

output

the transmitter

installed,

jumper

With this

protocols.

the

character

Jumpers

Removed

With W2

installed

Data Set Ready

With W3

feature

]

Data

installed

and

are

Installed

Jumpers

Removed

With W4

installed

controls
Send

With W5

installed

Request

This

feature

require

this

2-3

This

asserted.

that require

continuously.

used

and W5

the

signal

together.

removed,

state

signal

the

modem

line.

Request

Send

the modem

state of

the

removed,

is always

also.

fail

and W2

Ready

DTR H

CRC

removed,

accommodates modems

Set

some

together.

used

controls

RDY

MODEM

D15

the

and W3

line

D16 MODEM RDY H
'

CRC

are

and W3

Installed

D16

Transmitter

inverted by

signal

for

The diagnostic will

output gate.

/ah

the

reason,

special

jumper

this

removes

user

and W4

line

removed,

continuously.

accommodates modems
condition.

the

that

Table

M8202

Jumper

2~2

Configurations

Normal

Number

Configuration

Installed

Function

With
CRC

this

jumper

character

This

operation

the

output

jumper

installed,
not

codes

discipline

inverted

transmitter

the

CRC

gate.

must

the

CRC-16

DDCMP

ensure
and

and

proper

CCITT

Bit

under

Stuff

protocols.

the

special

user

reason,

character
output

W2,

Removed

When

Removed

The

installed,
is

When

installed,

Installed

only.

2-4

for

Transmitter

CRC

modem

the

modem

transformer

for

disabled.

recommended.

Installation

Removed

jumper

the

diagnostic

the

not

protection

the

this

inverted

gate.

transformer

W4,

removes

CRC
will

some

receiver

also.

protection

Installation

transformer
disabled.

not

recommended.

1-wire

half-duplex

operation

When the line unit module is shipped,

all switches in both
(3778).

This is the default status

packs are OFF.

These switches are a function of the down-line loading
feature of the DMC11.

After installation, the switches

can be positioned to accommodate the users requirements.
For details,

refer to Chapter 3 in the microprocessor

manual.

No.

Switch pack no.

Switch Pack

is an 8 switch DIP that is

installed

location E26 on the M8201 Line Unit and in location E29 on
the

M8202

Line

For the M8201,

Unit.

all switches except no.

M8202, all switches except no. 4,

5 are

For

used.

5, and 8 are used.

the

The

——

ON and OFF positions and the switch numbers are marked on
the package.
to

the

desired

The switches are the rocker type and are pushed
position.

Table 2-3 describes the normal configuration
no.

2.4

switch

pack

INSTALLATION

The M8201

for

AND

CHECKOUT

and M8202 Line Units are hex modules.

They

not

interface

with the Unibus so module edge connectors A and B are

not

required.

a result, the corner of the module in the vicinity of

the

2-4

and

Table

Configuration
Switch

Normal

Number

Position

OFF

Switch

With

OFF,

signal

the

following

Decode

Receiver

Function

OFF,

With

ON,

With

OFF,

which

the

With

only

OFF,

and

Modem
to

EIA/CCITT

V24

This

D14

the

high

This
Bit

mode

Stuff

Data,

unit

low

unit

is
protocols.

Modem

Clock

enabled.

inhibited.

line

Receive

are

through

the

interface.

V35

2-6

the

CCITT

Used

1low,

Transmit
line

the

CRC

MODE

signals

switch

module

GRTP

SEC

these

Unit.

Not

the

D14

function

ON,

——————

through

mode.
in

automatic

function

Received

presented

With

D14

operation

secondary

Clock,

CRC

the

ROMs.

CRC

signal

inhibits

applicable

OFF

the

ROM

signal

these

the

which

ROM

ON,

signal

allows

low

ROM

with

disables

which

Decode

Receiver

servicing

GRTP

ROMs.

Data

With

D14

Transmitter

which

OFF

Function

tester,

No.

Transmitter

During

OFF

Pack

Function

enables

2-3

used

are

received

interface.

only

the

M8201

Line

(Cont)

2-3

Table

configuration of Switch Pack No. 1
Switch

Normal

Number

Position

OFF

Function

Signal D14 SECURE 1s associated with this
Tt is bit 0 of the Modem Control
switch.
This bit is reserved and is

Module
Dependent

only.

Signal D14 SW 1is associated with this switch.
It is read only bit 1 of the Modem Control
It is read by the diagnostics
Register.
and indicates the type of line unit.
With an M8201
(D14

Line Unit,

low).

With an M8202 Line Unit,
i

(D14

S7 should be ON

S7 should be OFF

.
high)

the internal RC clock is sent
to the modem cable connector (J1) on the

With S8 ON,
M8201

Line

Unit.

During servicing with the H325 test
7~

connector installed on the modem cable, the
RC clock is sent back to the line unit as
the transmit and receive clocks.

During normal operation, the switch should
remain

ON.

This switch is used only on the M8201 Line
Unit.

e-7

connectors

installed

Units.
over

Proceed

The

the

Unibus

has

been

the

end

module

Unibus

plugs

Interconnect

are

unit

and

the

and

M8202

the

M8201

the

Line

J1.

H325

connector.

Line

connector

which

These

3-foot

Run

two

the

M8201
Unit

the

cables

MAINDEC-11-DZDME

and

-8

and

microprocess

each

and

Line
is

end

fits
2-1/2

in.)

follows.

connectors

line

Unit

unit

this

using

cable

conductor

end.

The

H854

connector

flat
mating

designated

J1.

the
of

BCO05C-25
this

the

coaxial

soldered

DZDMF

operation.

(approx.

Interfacing

and

install

are

long

install

two

and

one-foot

other

Unit,

ties

M8202

System

microprocessor

Unit,

connector

M8202

female

the

Unit.

microprocessor

J1.

length

checkout

line

H856

M8201

connectors

the

with

test

Line

cable

short

M8202

connector.

the

and

designated

connectors

which

the

DD11-B,

M8201

BC08S-1

the

allows

installed

connector

into

the

and

Install

male

installation

BCO8R-1

This

connectors

that

the

mylar

slots

cable

terminator

with

removed.

cable

cable,

12-12528

verify

the

connect

coaxial

pig-tails

to
the

test

together.

M8202.

correct

line

unit

—

Run MAINDEC-11 D2ZDMG to verify correct line unit/microprocessor
system operation.

Remove the test connector from the line unit.
M8201 - Connect the BC05C-25 Cinch connector to the customer
supplied

modem.

M8202 - Connect the coaxial pig-tails to the customer

/’“

supplied

coaxial

cables.

CAUTION

The maximum allowable length for the BCO05C
or BC05Z cable is 50 feet.

2.5

JUMPER AND SWITCH CHECKLIST

M8202
Table 2-4 represents a concise checklist of the M8201 and
ed.
Line Unit switch settings and Jjumper configuration as shipp

Table
Jumper

and

Switch

Jumper
Jumper

2-4

Configuration

DMC11-DA

Desig.

Checklist

DMC11-FA

M8201

DMC11~-MA/MD

M820 1

M8202

ourT

OouUT

OouT

ourT

ouT

Settings

For

Switch

Pack

No.

OFF

S1-88

for

Switch

Pack

OFF

Nos.

Settings

FOR

and

OFF

NOTES
:

Switch

Pack

Locations

SP1-E26

M8201

and

SP2-E87

E29

M8201

M8202

and

SP3-E88

E90

MS8201

M8202

and

E91

M8202

All

switches

OFF

status.

Reference

details

the

use

SP2?

and

SP3

represents

the

DMC11

Microprocessor

these

switches.

2=/0

the

default

Manual

for

2.6

LOCAL

LINK

CABLE

enance
This section discusses the selection, installation, and maint

poses. The link
pur
two
ve
ser
t
mus
le
cab
s
Thi
le.
cab
k
lin
al
loc
the
of
with sufficient
er
eiv
rec
the
to
nal
sig
ted
era
gen
the
r
ive
del
t
mus
le
cab
amplitude to exceed the receiver threshold and it must

shield the

signal from external electrical noise.

Selection

2.6.1

For use in the DMC11, Digital recommends the Belden 8232

double

al
shielded (triaxial) cable, or 1its equivalent. The electric
ns are
characteristics are listed below. The nominal specificatio
given unless otherwise stated.

0.097 microhenrys/ft
(.318 microhenrys/meter)

Inductance

17.3 pF/ft

Capacitance
Vel.

78%

Prop.

Impedance

Attenuation

(MHz)

ohms

dB/ft
.25

100

Voltage
Sweep

Rating

175

Test

Conductor DC

(56.7 pF/meter)

resistance

Shield DC resistance
(each shield)

Vrms

min.

34.5 ohms/1000 ft
(111.5 ohms/km)
2.6 ohms/1000 ft
(8.53 ohms/km)

2-//

The

required

physical

characteristics

are:

Triaxial
Cellular
20

The

center

Belden

8232

provides
and

polyethylene

AWG

the

rejection.
cellular

The

not

communications
conductor)
cannot

When

selecting

cable

The

over

the

rate,

and

room

center

the

after

good

other

(i.e.,

foot

nominal,

could

years,

attenuation.
become,

worst

after

has

cable

transmitter

excellent

signal

noise

and

loss

and

weather

and

dielectric.

typical

factors
given

being

Thus

fair

Other

59/u

dielectric

must

the

cable

subject

temperature

(122° F)

specification

causes

could

resistance,

coax
and

flexibility
typical

with

single

AWG

shield

connection.

with

low

The

conductor

excellent

chemical

the

temperatures

AWG

provide

jacket

value

temperature

unit

provides

several

increases

line

shield

polyethylene

6000

the

double

types

The

requirements.

—

very

solid

these

match

(0.11%/°
F). at 50° ¢

and

dB/1000

Its

dielectric

cable,

elevated

increase
loss

for

attenuation

0.20%/° ¢

use

cable

attenuation.

temperature

ohm

contaminate

using

used

all

polyethylene

resistance,

does

combination

polyethylene

abrasion

meets

circuits.

The

distortion.

and

cable

required

receiver

insulation

conductor

the

years

case.

2-/2

determining

vendor

for

deviation

can

yet

initial
use

room

20%.

approximately

an additional loss of 5%

aging

produce

considered

expected.

faster

another

nominal

high

Finally,

than

normal

permanent

2.6

dB/1000

temperature,

5.2

10%

2.6.2

Installation

The characteristics of the local link cable should be measured
prior to installation. In particular there are two parameters that
are
the user should measure and note for future reference. These
the propagation time delay, which can be measured with a pulse

generator and an oscilloscope, and the dc resistance of the cable

.
with the far end of the center conductor shorted to the inner shield
For the Belden 8232, these parameters can be expected to be nominally
1.30 ns/ft and 32 ohms/1000 ft. Once the cable is installed, and
both ends are therefore not available at the same place, the latter
parameter can still be measured easily, and the former can be
measured by use of the TDR method described in Paragraph 2.6.3.
While installing the cable, make a complete map of its layout,

showing the position of the cable with respect to buildings,

equipment and so forth, and also the locations of all access points,
including not only splices and in-line connectors, but pull boxes
also. Carefully measure and record cable lengths between landmarks.
Such a map will greatly facilitate maintenance.

The user must take the following factors into account when installing
the

local

link

cable.

TEMPERATURE - The polyethylene used as the dielectric material in

most coaxial and triaxial cables begins to soften above 80O C. As

the conductor moves off center, variations in cable characteristics

2-13

occur.

may

installed

short

should

during

closed

MOISTURE

cable

the

improperly

cuts

water,

condensed

from

length

cable,

installed

into

This

resistance

with

installation

installation.

Moisture

through

tension

sharp

Additionally,

after

circuit

condense

shield.

measured

incurred
The

under

the

connectors.
which

polluted
shorten

can

ensure

against

shorts

outer

Minute

migrate

atmosphere
its

resistance

along

may

jacket

20K

the

enter

ohms.

braid.

seriously

the

through

water

contaminate

and

ohms/ft.

amounts

can

lifetime,

should

impurities

the

conductor

circuit

36.
1

moisture-related

the

open

resistance

should

scratches

berds,

vapor

will

Water

the

entire

degrade

performance.

PULLING

TENSION

For

most

preferred

that

the

cable

the

must

pulled.

the

AWG

cable

tension

environmental

installed

During

center

conditions

conduit,

installation,

conductor

must

generally

through

which

total

pulling

the

not

exceed

pounds

.
(8N)

v
For

ease

For

long

cable

every

100

feet

maintenance

feet

agent

with

the

level

best

conduit,

equivalent.

straight

antifriction
compatible

runs

used

cable

divide

convenient

degree

conduit.

during
jacket

conduit

cable

material.

provided

into

have

bend

recommended

pulling,

2-/4

the

that

the

sections.

pull

equal

agent

box

SPLICES AND CONNECTORS - The cable layout should provide access

points for test purposes and for replacing defective sections.
(See Paragraph 2.6.2.1.)
splices

and

in-line

Strain relief must be provided at all

connectors.

RECOMMENDED WIRING PRACTICES - Chapter 8, Article 800 of the National
Electric Code defines wiring rules for communications circuits.
These rules must be observed for safe operation of the DMC11.
particular,

note

these provisions of the code:

"Communication conductors shall not be placed in a raceway,

compartment, outlet box, junction box or similar fitting with
conductors

for

light and power.

"Communication conductors may be run in the same shaft with

conductors for light and power provided the conductors of the two
systems are separated by at least two inches."”

"Suitable protective devices must be employed for wiring between
buildings."”

SURGE WITHSTAND CAPABILITY - The receiver has no provision for

protection against normal mode voltage surges exceeding 30 V.
surge withstand is required,

the user must install a separate

circuit to condition signals to the receiver.

2-15

NOISE

The

ratio

500:1.

M8202

suppression

2.6.2.1

designed

Cable

are

selection,

means

Connectors

use

1in

the

M8202

pigtails.

2-1,

are

manufactured

joining

cable

Digital

which

Harrisburg,

Part

the

are

Number

AMP

Part

Male

12-12001

66536~2

Female

housing

12-12526

206060~1

Female

12-12000

66594-2

crimper

can

install

ejector,

working

with

and

in
a

hole

the

AMP

set

remove

ejector

holes

then

for

the

pins

the

crimping
Type

Vi,

that

and

always

2-/6

been

orient
and

pins

without

it
the

to
It

the
is

AMP

are
so

Figure

cable;

very

the

unlikely

the

use

incorrectly;

305183.

numbered.

that

holes

requiring

inserted

the

receptacle

bottom,

have

pins

the

90293-1.

connectors

above

housing

connector,
4

for

Pennsylvania.

206152-1

installed

cable

shown

12-12527

are

noise

recommended

housing

The

Inc.,

are

connecting

components

rejection

rates.

Male

proper

are

AMP

for

and

206062-1

the

top,

these

grounding

components

also

mode

12-11430

one

and

error

common

clamp

recommended

line

Cable

connectors

that

with

installation

following

sections
All

operate

reducing

The

Component

The

hole

either

When
is

side

the

70 BE SUPPL/IED

Figure

2-1

Local

Link

217

Cable

Connectors

The

cable

clamp

screws,

and

largest

cable

the

assembly

three

supplied

shell,

one

for

clamps,

which

the

should

used.

Slide

size

the

two

the

shell

onto

cable.

Dress

the

center

into

with

well

the

another

half

inch,

about

quarter

center

and

its

Pull

hole

so
inch

inner

insert

outer

shield,

taper

its

pins

shield

insulation

its

both

fits

the

half

into

two

parts,

into

holes

inch

insulate

and

as
about
of

the

pin,

and

along

with

the

hole

conductor
1.

attach

and

fit

back

the

both

it,

will

connector,

the

shields

tip

together,

final

insert

shield

enough

the

into

Crimp

and

crimp

Dress

fits

the

back

crimped

that

conductor.

the

and

the

inner

and

insulation,

Separate

them,

conductor.

insulation

the

conductor

the

inner

pins

from

the

insert

the

screw

the

clamp

Screw

the

shell

into

the

housing,

and

shell.

After

male

and

female

Screw

the

other

ring

connectors
of

the

housing.

2-/8

have

female

been

housing

plugged
over

the

together,
male

Both M8202 pigtails have female connectors, therefore, the local
1ink cable must have a male connector. The connectors at the ends
of the cables are installed in the same manner described above
except that at the ends the outer shield must be grounded as

e
described in Paragraph 2.6.2.2. The male connector shown in Figur
2-1 is made up for the computer connection. The wire sticking out
the back end of the connector is the outer shield.

2.6.2.2

Grounding - The outer braided shield of the cable must

be grounded near, but not to, the computer system chassis. The
grounding conductor should be connected to a water pipe electrode,

or if none is available, to the power service conduit, service
equipment closure, or grounding electrode conductor where the
grounding conductor of the power service is connected to a water
pipe electrode

at the building.

When neither of the above means of grounding is available, it is
permissible to connect the grounding conductor to the service
tor,
conduit, service equipment enclosure, grounding electrode conduc
or grounding electrode of the power service of a multigrounded
neutral

power

systemn.

If it is impossible to ground the cable shield by one of the above
methods, connect the grounding conductor to one of the following:

2-/9

concrete-encased

bare

near

copper

least
the

inches

direct

effectively

where

conductor,

bottom

contact

continuous

the

ground

and

concrete,

the

having

less

than

and

feet

AWG,

located

foundation

encased

within

footing

and

that

earth.

metal

both

pipe

not

smaller

concrete

with

extensive

authority

rod

grounded

acceptable

electrode

structure.

underground

the

gas-piping

servicing

gas

system,

supplier

and

jurisdiction.

driven

into

permanently

damp

earth,

WARNING

Under

circumstances

conductor
water
or

pipe,

rod

For

lightning

rod

grounding

neutral

power

the

grounding

steam

hot

conductor,
other

pipe

than

circuits.

Maintenance

maintenance

purposes,

cable

characteristics,

short

circuit

Paragraph

signal

electrodes

multiground

2.6.3

connected

shall

line

2.6.2.

amplitude

user

should

particularly

resistance

Once

the

system

M8202.

the

Then

record

propagation

indicated
is

keep

the

operational,

repeat

this

time

delay

beginning
record

the

measurement

initial
and

of
received

every

2-20

scheduled PM date (at least four times per year). If a deviation
of 20 percent is observed 1in the signal amplitude, disconnect both

ends of the cable from the M8202 and measure both the open circu
open
and short circuit resistance of the line. If the measured

for
circuit resistance is less than 20 megohms, inspect the cable
contamination of the dielectric, and for adverse effects of sharp
the
bends or stress points, elevated temperatures, oOr aging. If
line resistance with a shorted end increases above the value
ctors,
measured at installation, inspect the cable for loose conne
contaminated connectors, and excessive tension.

ose
LOCATING A DEFECTIVE SECTION - An ohmmeter can be used to diagn
on
an open line or a low impedance shorted line, by checking one secti
at a time until the faulty section is located. If the cable is not
partitioned into small enough sections, the distance to the fault

can be measured by making use of time domain reflectometry (TDR).

,
Although TDR cable testers are available from Tektronix and others
a pulse generator and oscllloscope can be used for approximate

measurements. Disconnect both ends of the cable, and drive one end
with a 5 V peak, 100 ns wide pulse with a repetition rate below 10
kHz. Measure the time interval between the leading edge of the
driven pulse and the leading edge of the first reflection. The
reflected pulse will be in the 10 mV to 1 V range. It will be

normal for a line open, but inverted for a line short. Figure 2-2

shows typical oscilloscope traces for both cases. The time interval
represents the propagation time delay for a round trip from the signal

2-2/

_aV

(

—

S00NS \/
I

]

7/'3

SHORTED LINEF

OPEN LINE

Figure

2-2

Signal

Reflections

2-22

from

Line

Fault

generator to the fault and back again. The distance D to the fault
in

(meters)

feet

1is

=T /2p
P

Where Tp is the measured time delay in nanoseconds, and p is the
propagation time in nanoseconds per foot (meter) recorded before
the

cable

2.7

was

installed.

FULL DUPLEX/HALF

The DMC11

DUPLEX OPERATION

is capable of either full-duplex or half-duplex operation,

The microprogram controls the transmitter-receiver interaction in

half-duplex mode in order to minimize the line control contention
problems.

While there are few considerations required when selecting half-duplex
operation of the DMC11-DA or DMC11-FA Line Units,

careful thought

should be given to the selection of full or half-duplex operation
of the DMC11-MA-DMC11-MD Line Units.

Full- or half-duplex operation of the DMC11-DA/FA requires selecting

the proper data set and informing the microprogram that half-duplex
mode

has

been

Operation of

selected.

the DMC11-MA/MD Line Units require hardware

considerations.

link cables.

Full-duplex opeation requires two separate local

Half-duplex operation requires only one. The two cable

requirement for full-duplex operation cannot be eliminated through
the

use

dual

Coax/Triax

cable.

2-23

While
full

full-duplex
throughput

throughput

factors

half-duplex

The

local

the

two

Half-duplex

requires

considered

Flow

data

flow

nearly

Data

Rate

and

but

requires

operation

only

when

cables,

one

provides

implies

cable.

selecting

also

The

half

the

following

full-duplex

operation.

Traffic

unit

potential.

potential

should

operation

the

Expense

worth

the

link

line

pigtail

for

the

equal

both

necessary

foreseeable

Cable

jumper

most

the

going

one

way

directions?

use

maximum

data

rate

now

future?

two

cable

full-duplex

operation

expense?

units

(DMC11-MA/MD)

half-duplex

data

used

require

operation.

the

output

This

installation

allows

connection

either

the

line

local

1link

cable.

The

connection

the

transmitter

pigtail

through

local

the

link

the

case

cable

local

link

connected

cable

half-duplex

made

with

1link

cable
to

the

(Figure

operation,

either

2-24

the

made

distant

that

the

receiver

local

pigtail

2-3).

the

connection

pigtails

(Figure

the

2-3).

local

TRANSMITTER
PIGTA/L

[

HE >

MAIMD

LOICAL
LINE
UNIT — ——

RECEIVER
PIGTAIL

—

DMC//-

RECEIVER
PIGTA/L

MA MO

LOCAL LINK CABLES | LOCAL
[ INE
UNIT
][
L

TRANSMITTER
PIGTAIL

_ _J
FULL DUPLEX

LOCAL LINK CABLE

DPMC//-

MA[MD

LLO/X/Q.‘

CONNECTION TO

RECEIVER PIGTAILS

DMC 1/~

MAIMD

LzfiAc/fif
e

PREFERRED. NO

CONNECTION 70
TRANSMITTER
PIGTAILS.

HALF PDUPLEX
Figure 2-3

Full-Duplex/Half-Duplex Connections

2-25

CHAPTER

PROGRAMMING

INTRODUCTION

3.1

This

chapter

into

two

contains

sections:

general programming

one

lists

other

discusses

programming

3.2

REGISTERS

AND

The

nine

They

are

The

DMC11

address

760010

registers
all

bit

the

are

bit

functions

and

divided
the

procedures.

ADDRESS

the

SELECTION

line

unit

are

shown

in Table

unit)

assigned

3-1.

registers.

plus

floating

address

764000.

The

physically

registers

used

(microprocessor

through

located

DEVICE

the

information.

the

selected

line

space

device

which

address

microprocessor
four

address

includes

signals

device

addresses

selection

module.

logic

The

line

from

the

Figure

1is

unit

microprocessor.

3.3

Bit

assignments

applicable,

illustration
detail.

BIT

the

and

for

ASSIGNMENTS

all

the

registers

are

shown

described

showing

accompanying

table

that

bit

discusses

3-1.

assignment

each

bit

The

cable

that

contains

line

two

unit

buses.

information

connects

the

from

the

line

unit

BUS

(IBUS)

carries

The

BUS

The

microprocessor.

the

microprocessor

Table

Line

Name

Unit

and

OUT

the

microprocessor

information

(OBUS)

line

Registers

Comments

Read only

Out

Data

Write

Out

Control

Read/write

Sync Register

Read/write

Bits

are

Read

only.

Bits

are

Read

only.

Control

Modem

Control

Maintenance

carries

unit.

In Data Silo
Register

—

3-1

Address

Silo

from

\Jj

only

switch

Read/write

J-&

‘0/

|
selectable.

selectable.
)

IN DATA S1L.0 REGISTER (/¥)

7I@TJI4l3Ta1/I¢
PATA

READ ONLY

OUT CONTROL REGISTER (/)

SR |et //7 /) R0Y 7//%7///,/ 7E0M |T50M| FEADIWRITE
OUT DATA S1L0 REGISTER (/P)

N
|

IN CONTROL REGISTER (12)

&% | 4t |ioop | AbY 2/?/////Z/; o AfACTC(/{‘ READJWRITE
MODEM CONTROL REGISTER (/3)

anG |DTR | RS | HD |F8| €S | sw SEme] READIWRITE
|

SYNC REGISTER (14)

SYNC (;/,94 0',q Jf"(jalvfl,‘qfiy IADR51
-

REG/STER /5

BITS ARE SWITCH SELECTABLE |
REGISTER /6

B/lzs A/I?E SW'/T(/; 55416( TA;?LE |

/?EAD/ WAI7TE

READ ONLY

READ oNLY

- MAINTENANCE REGISTER (17)

Qo [@1 ST |ocor |Icik
Figure 3-1

Ll IR FEAO/WRITE

LLine Unit Register Configurations
and Bit Assignments

J-3

3.3.1
The

Data

line

Silo
two

Silo

unit

which
buses

contains

read

(In

Bus

microprocessor

(10
in

octal).
the

data

the

Both

silos

Bus,
an

the

8-bit

are

contain

bits

Out

from

(8-10)
are

Data

that

Data

is
by

the

bit

belong

0-3

these

the

another

the
are

the

same

data

into

1is

the

and

data
an

8-bit

selected

Out

Data

Silo.

transmitted.

silo).

Data

Silo

each

The

address

Data

only.

unit

This

The

0-3

the

line

microprocessor.

Control

bits

the

write

the

When

FIFOs.

the

Bus,

are

data

character

which

selected

writes

Silo

Thev

interconnect

registers

receiver.

(0-7

Silo,

Out

read

bits

the

registers.

microprocessor

silo

Bus)

these

character

data

and

Out

This

these

and

Silo

Out

only

allow

When

two

Data

the

each

Registers

and

case,

Out

the

For

the

(11

octal).

the

Out

Silo

remaining

Data

Control

Data

Silo,
For

the

(12

octal).

Control

read.

Therefore,

they

will

Out

Control

the

silo

control

before

bits

they

0-4

must

are

updated

read

every

before

time

read

is
H

—_—

1lost.

every

time

information

bits

0-4

are

passed

passed,

written

into.

written
these

the

transmitter

into.

Therefore,

bits

must

through

written

into

3.3.2

Out Control Register (Figure 3-2)

Bit

Name

Description

This bit is used to initiate the start of

TSOM

(Transmit

Start

Message)

new

message.

The Sync character must

Mode:

DDCMP

be loaded into the Out Data Silo along
This character 1is
with the TSOM bit.

transmitted as the Sync character until
Until it is cleared, the
TSOM is cleared.
characters are not included in the CRC

When TSOM is cleared, the
present Sync character is transmitted
All data 1is
and is followed by data.
accumulation.

included in the CRC accumulation, 1if CRC
Once TSOM has been set, the
is enabled.

CRC accumulation cannot be inhibited
unless the line unit is initialized.

Bit Stuff Mode:

When TSOM is set,

a flag

character is automatically transmitted.
The character that is
bit

lost.

Flag

loaded with the TSOM

characters

are

automatically transmitted as long as TSOM

is set.

When data is to be transmitted,

TSOM is cleared and data is loaded into
At the completion of
the Out Data Silo.
the current flag character,
transmission of data begins.

the actual
All informa-

tion to be transmitted is included in the
CRC accumulation, if the CRC function 1is
enabled.

Bit

Name

Description

This

bit

cleared

the

TEOM

End

Message)

the

Data

Silo.

the

silo

and

used

the

enabled.

CRC

and

character
messages

are

transmitter

TEOM

shut

character

bit

the

J—6

transmitted.

the

CRC

the

having

second

generates

set,

lost.

pending,

inter-message

This
by

This

function

the

down.

with

silo.

CRC

cleared),

(TSOM

loaded

transmission

pending

character

down

me ssage

TEOM

shut

the

set,

When

are

into

transmitted.

the

transmitter

the

Mode:

messages

and

into

loaded

the

logic

terminate

loaded

the

control

When

Stuff

character,

Mode:

only.

was
bit

passed

progress

Bit

This

silo.

DDCMP

data

the

bit

write

initialization

that

Out

This

(Transmit

program

fact

through

the
The

transmitter

TEOM

single

CRC

the

terminating

flag.

program

write

initialization

only.

logic

and

It
by

cleared

I parallel with

]

OUT DATA S/LD

TM~

4
ey

\le

|5 |\ 4|38

OUT

ouvT

ACTIVE | READY

l
|RESERVED| TRANSMI7 START
OF MESSAGE
( TSOM)

OUT RESERVED RESERVED TRANSMIT END
OF MESSAGE
CLEAR
( TEOM)

NOTE

8ils @-F arcfafisea/ Lo the Cransyylicr

N rouz?b thesifo eycry time reqsecr /@ /5
Wr1Lten 1nta, Therefore, 1 fF coritro/ 10 or-

ed.

malion 1s Lo He

these biZs must

(ntao bc"a%rse /5:7/5&‘6/ /d 15
bhe wrillon
1nto.
wyllen

Figure 3-2

Oout Control Register Format

3=7

Bit

Name

Description

the

TSIP

flip-flop

which

set

whenever

is loadeé into the Out Data Silo.
is

loaded

into

transmitter

and

Reserved

These

are

cleared

and

whenever

silo

through

bits

the

TSIP

data

the

program
the

and

This bit

passed

the

silo.

write

only.

They

initialization

flip-flop

data

loaded

which

into

logic

the

set

Out

Data

Silo.

OUT

RDY

(Out

Ready)

When

asserted,

this

bit

informs

microprocessor

that

the

transmitter

ready

space

1is

available

The

data.

and

the

read

then

the

and

OUT

RDY.

the

silo

one

cycle

must

silo

and

reading

OUT

This

bit

only.

loaded

the

elapse

read

Data

Out

OUT

true

data.

that
Silo.

Data

The

allows

interpreted

has

Out

the

microprocessor

indicates

loads

reads

speed
RDY

before

Therefore,

between

the

RDY.

Reserved

Read

only.

OUT

ACTIVE

informs

the

status

ACTIVE

microprocessor

Silo

the

set,

This

bit

hardware

This

the

is
and

bit

the

switch

selectable.

microprocessor

transmitter.

When

transmitter

active.

read

only.

cleared

the

set

the

initialization

logic.

OCLRP

(Out

This
Clear)

bit

functions.

JF-8

used

OCLRP

1is

clear

all

program

the

write

transmitted

only.

3.3.3

In Control Register

Bit

Name

BCC

(Figure

3-3)

Description

MATCH
Check

(Block

Character Match)

BCC MATCH is the output of the receiver
CRC error logic that monitors the contents

With the CRC function

"of the CRC register.

enabled, BCC MATCH is asserted at the end
of an errorless message.

protocol,

In the DDCMP

the contents of the Receiver CRC

protocol,
Register

In the SDLC

the contents of the Receiver CRC
016417.

equal

This bit is read only and is updated every
time
BLOCK

END

read.

BLOCK END is used to inform the microprocessor,
in SDLC mode, that a terminating flag has

been received.

This flag may be the

The
leading flag for the next message.
BL,OCK END bit is loaded with the high byte
of the CRC character;

therefore,

the BLOCK

END bit along with the BCC MATCH bit should
be used to indicate reception of a good
message.

This bit is read only and is not used in
the DDCMP mode. It is updated every time

ffix

Reserved

read.

only.

Read

and
3

(In

RDY

Ready)

When asserted,

this bit informs the

microprocessor that received data is ready
It indicates that data
for processing.
is available at the output of the In Data
Silo.

This

bit

J-39

read

only.

In paralle/ with

/A DATA S/L0

3,2

/ | o

IN ACTIVE | IN READY |RESERVED | BLOCK CHECKH

CHARACTER MATCH

(BCC MATCH)

IN CLEAR ALTERNATE RESERVED
LINE UMIT

BLOCK
END

L OOP

(ALTLOOP)

NMOTE

B1Zs ¢-—3 ar
po
e’az‘ed every Zyme
Vef’ /5cr /¢ rc?a
TACreRre, they

read

pefore regiséer /g

/5 rm or they wil be ost

Figure

3-3

In Control

JT=/0

Format

Bit

ALT

Description

Name

(Alternate

Unit

Loop)

this bit is set to

During maintenance,

LOOP

Line

loop the receiver on the transmitter with
no connection to the modem control lines.
This bit is program read/write.

ACTIVE

this bit informs the

When asserted,

microprocessor that the receiver is in
the data reception mode; that is, it 1is
receiving data or CRC

characters.

IN ACTIVE is asserted upon

DDCMP Mode:

receipt of the first non-sync character.

IN ACTIVE is asserted upon

SDLC Mode:

the

receipt of

ICLRP

(In

Clear)

This bit is used to
receiver

ICLRP

3.3.4

Modem Control Register

Bit

Name

SECURE

first data character.

clear all

functions.

is program write only.

(Figure 3-4)
Description

The function of this bit is reserved for
future use.

This read only bit is

selected by a switch.
when the

the

switch is OFF

SECURE 1is asserted
(open).

The function of this bit is reserved for
future use.

This

read only bit is

selected by a switch.
when the

switch is OFF

SW is asserted
(open).

7]elsfe]z]2]o0
/
|
DATA

752’;’5‘,’,”‘
(O7R)

RING

HALF

CLEAR

(#0X)

(CS)

OUPLEX | T0 SENO

REQUEST

TOSEND

(RS)

Figure

3-4

MODEM

READY

Modem

Control

JIJ/P

| SECURE

Format

Description

Name

Bit

(Clear

Send)

The CS bit informs the microprocessor of
the state of the modem Clear to Send line.
This bit and MODEM RDY (bit 3) must be
asserted simultaneously to generate SEND
which is the transmitter enabling signal.
This

MODEM

bit

read only.

The MODEM RDY bit informs the microprocessor
of the state of the Modem Ready line. On

RDY

(Modem Ready)

the M8201

Line Unit,

this signal can be

held asserted permanently through the use

of a jumper.

On the M8202 Line Unit, this

signal is asserted when power is turned on.
bit

This

read

only.

The HDX bit is used to put the line unit
When this bit and
in the half-duplex mode.
the Request to Send bit are asserted, the

HDX

(Half

Duplex)

receiver clock is inhibited which blinds
the receiver during operation in the
half-duplex mode.

This bit is program read/write and can be
directly cleared by the clear signal from
the

(Request

Send)

microprocessor.

The RS bit informs the microprocessor of
the state of the modem Request to Send
This bit is controlled by the line
line.
unit logic and not by the microprocessor.

It is cleared by absence of data or by
initialization logic.

the
This

bit

F-/3

read only.

Bit

Name

Description

DTR

The

(Data

Terminal

Data

Ready)

The

Sync

DDCMP

enables

Terminal

Ready

the

can

cleared

The

RING
the

the

This

bit

only

informs
of

the

inhibited

read

via

This

bit

logic

writing

the

directly

initialization

state

RING

modem

line.

read/write.

set

Sync

bit

program

RING

3.3.5

DTR

but

into

microprocessor

modem

Ring

line.

the

M8202

Line

it.

Unit.

only.

Mode:

The

8-bit

program

loaded

read/write

with

program

selectable

sync

character.

SDLC

Mode:

secondary

flag

3.3.6
Both

The

station

the

SDLC

Switch
of

the

these

program

secondary
address.

message

determines

3.3.7

Maintenance

Bit

Name

MODE

This

this

bit

character

loaded

fcllows

with

the

initial

format.

Selectable
registers

mode,

Registers

are

the

DIPs

and

containing

function

(R15

(Figure

both

R16)
eight

switches

each.

registers.

3-5)

Description

The

MODE

(DDCMP
DDCMP

i1s

or
is

bit

selects

SDLC

the

protocol

families).

selected;

when

When

set,

cleared,

SDLC

selected.

During
from

initialization,

the

microprocessor

the

CLEAR

sets

this

signal
bit

43|21

QUOTIENT | OUT CoM- |RESERVED|

MODE

716 |5

oy
(@) | BLs
(9COR)

QUOTIENT

(Q0)

ouT

%s16%_4— INTERNAL

SERIAL

INPUTY

READ

ClLO

(ZCZR)

Figure

3-5

Maintenance

F-/5

Name

Description

select

DDCMP.

(SDLC

selected)

This

bit

only

can

cleared

writing

into

it.
This

ECS

(Internal

Clock)

Reserved

bit

clock

the

read/write.

output

the

(approximately

This

bit

Read

only.

read

internal

KHz).

only.

..._./i
ICIR

(In

When

Composite

Input

the

asserted,
In

Data

bit

Silo

read

only.

indicates

ready

that

data.

Ready)

This

bit

When

asserted,

Composite

data

Output Ready)

Data

Silo.

This

bit

OCOR

(Out

this

(Serial

Input)

(Quotient

QI
In)

(Quotient

the

bit

indicates

output

read

only.

serial

input

bit

the

CRC

This

bit

read

least

Receiver

Out)

ready

this

data

that

the

from

Out

|
—

the

modem.

This

the

read

least
CRC

This

read

significant

bit

the

bit

the

Transmitter

bit

only.

significant
Register.

only.

nw,/’

J/6

3.4

PROGRAMMING PROCEDURES

e proper
The following programming procedures must be used to ensur
operation of the line unit.
1.

of Message
Transmit Start of Message (TSOM) and Transmit End
TSOM
(TEOM) are bits 0 and 1 of the Out Control Register.
oprocessor.
and TEOM are loaded into this register by the micr
These bits are sent from the Out Control Register to the
acter
Transmitter Buffer when the microprocessor loads a char
set,
(sync, data, etc.) 1into the Out Data Silo Register. If

cter.
the control bit (TSOM or TEOM) goes along with the chara
s
However, the Load signal for the Out Data Silo also clock
the TSIP flip-flop which clears the TSOM and TEOM bits in
the Out Control

Therefore, always load the TSOM or TEOM bit into the Out
Ccontrol Register before loading the Out Data Silo. The

control information is cleared from this register automatically
as the Out Data Silo accepts the data.

In the SDLC mode, the data written into the Out Data Silo
with either TSOM or TEOM is lost. This is an internal function
that is performed automatically by the transmitter control
logic. Physically, this is accomplished by inhibiting the
loading of the Transmitter Data Shift Register.

In place of the shift register output, the transmitter

control logic transmits a flag character when TSOM is set
and it sends the transmitter CRC check character when TEOM
If both TEOM and TSOM are set, 16 zeroes are sent.
is set.

317

{d
1B

BCC

MATCH

Control
FIFOs

and

that

bits

BCC

MATCH

part

the

and

the

check

the

BLOCK

END

Control

read

Data

mode,

bits

Physically,

Silo

always

DDCMP

are

Data

the

CRC

END

constitute

Therefore,
reading

BLOCK

and

they

are

the

part

the

3341

Data

Silo.

When

are

read

microprocessor,

are

lost.

the

These

bits

the

are

data

read

the

Control

before

Silo.

the

BCC

character

MATCH

that

flag

produced

presented

the

with

match

information.

the

the
with

Bit

Stuff

terminating
the

the

BCC

used

mode,

flag

the

has

high

byte

MATCH

bit

along

indicate

BLOCK

been

the

CRC

with

reception

J~/8

END

bit

received.
Check
the
an

asserted

This

bit

Character.

BLOCK

END

errorless

bit

when

loaded

Therefore,
should

message.

CHAPTER

DESCRIPTION

DETAILED

4.1

INTRODUCTION

This chapter providse a two level discussion of the DMC11

line unit.

It discusses the line

A functional description is presented first.

unit logic in major functional groups at the block diagram level

second level of discussion is the detailed

The

(Figure 4-1).

description that covers the complete line unit logic at the circuit
schematic

level

shown

the

line

set.

unit print

NOTE

are

There

two

versions
speed

line

The

M8202

high

for

local

network

integral

modem

that

56K bps.

The

M8201

intended
no

It has

EIA

19.2K bps

speeds

56K

must

line

unit

intended

The

bps

speed

network

contains

and

unit

line

applications.
M8201

interface

contains
with

modems

CCITT V35

modems

bps.

unit

used.with

separate manual

unit.

compatible

low

1logic

RS232C/CCITT V24

DMC11

line

operates

integral modem.

speeds

The

the

applications

remote

for

conversion

level

not a

stand-alone device.

DMC11

microprocessor.

(EK-DMCUP-MM-001)

covers

the

microprocessor.

The

first M8200 microprocessors to be

4=/

shipped

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B

OXL

have

their

the

DDCMP

will

have

the

SDLC

line

4.2

(f\

FUNCTIONAIL

ROMs

configured

protocol.
ROMs

can

4.2.1

Logic

For

the

functional

major

sections

Control

Transmitter

’

CRC

Logic

*Data

Set

discussion,
as

shown

only

**M8202

only

protocols.

the

line

unit

logic

Para.

divided

No.

4.2.1.2

Logic

4.2.1.3

Control

Logic

4.2.1.4
4.2.1.5
4.2.1.6

Interface

Logic

Initialization

*M8201

both

M8202

below.

Logic

Control

Maintenance

**Tntegral

and

with

4.2.1.1

Control

Receiver

operate

M8201

with

version

Description

Reéisters
Out

with

DESCRIPTION

Title

/’\‘

The

operate

subsequent

configured

protocol.

units

Modem

Logic

4.2.1.7
4.2.1.8

4.2.1.9
4.2.1.10

into

4.2.1.1

Registers

The

line

eight

bit

unit

registers

Data

The

Silo
Data

Silo

loaded

Data

operation

uses

address

Out

Data

Silo

The

Out

and

sends

address

below.

They

are

all

from

the

Receiver

Silo

Data

transmitter
and

When

the

and

microprocessor

and

read

bits

data

performs

presented

Shift

write

received

with

Transmitter

data

(octal)

loaded

bits

the

read

IBUS.

This

only.

data

This

transmitted
register

uses

only.

message

with

(octal)

Control

This

discussed

registers.

Out

are

\,/

contains

the

operation.

indicates

the

control
It

and

controls

status

status
the

the

information

start

Out

Data

and

end

pertaining
of

Silo.

In Control Register
This

receiver

and

bit

during

?\J/

contains

the

operation.

that

controls

control

also

looping

and

status

contains
of

the

information

receiver

the

CRC

pertaining

error

bit

transmitter

maintenance.

Modem

Control

This

contains

control/status

the

status

information

lines.

pertaining

the

modem
./

Sync

The

Sync

selectable

sync

secondary

station

Bit

mode.

Stuff

Switch
These

registers

serial

controls

the

are

DIPs
the

the

DDCMP

during

Registers

loaded

with

mode.

secondary

R15

and

station

program
loaded

with

operation

the

R16.

containing

function

contains

mode.

data

the

4.2.1.2

and

eight
both

switches

each.

The

registers.

maintenance

and

address

determines

Maintenance

read/write

character

Selectable

program

This

from

choice

status

information

monitors

the
of

modem.

output

of
of

also

use
the

during

the

internal

contains

the

bit

clock

that

protocol.

OufltControl Logic - The out control logic interfaces with

microprocessor

processor

send

output

bus

information

(OBUS)

which

line

unit.

the

used

The

the
out

microcontrol

logic consists of the Out Data Silo, Sync Register, four bits of
the

Out

Control

the

information

transmitted,

Buffer.

address

(Bit

stored

the

protocol)

Sync

the

decoder.

microprocessor

temporarily

information

Stuff

from

and

the

stored

line

sync

4-5

unit

part

the

message

Transmitter

secondary

character

Data

station

(DDCMP

protocol),

dad

4.2.1.3

the

microprocessor

obtain

the

line

unit

4.2.1.4
The

are

from

read

used

and

The

(IBUS)

the

logic

unit.

used

All

this

interfaces

eight

microprocessor.

perform

the

with

microprocessor

registers

Eight

8-input

function.

Logic

logic

controls

network

consists

control

which

line

restrictions

logic

the

message

protocol

seven

transmission
length

determines

functional

format

the

units

bit
imposed

message

that

are

below.

ROM

Sync

read-only

the

The

Control

control
no

bus

unit.

The

described

Three

with

line

format.

ROMs

input

Transmitter

characters

for

can

transmitter

the

Logic

information

multiplexers

Control

Buffer

memories

(ROMs)

are

the

major

controlling

elements

transmitter.

The Functionfb%éfifiifiifiuflifibR}
controls

the

current

state

setting

the

logic

decodes

DONE.

the microprocessor

This

determines

information
the

from

the

inputs

along

event

with
a

and

the

character

basis.

Six

control

signals,

¢§t@M Sync Buffi%i&
the

buffer

the

logic

is
to

including

FDR,

are

stored

the

After the flag or sync characters have been sent,

clocked
set

three

only

for

the

end

character

character.
during

the

This

allows

present

character

while

not

affecting

the

outputs

multiplexes

shift

timing

Clock

Logic

the

CRC

transfers

from

user

mode,

the

transmitter

clock

transmitter

control

modem

transmitter

the

Flip-Flop

The

serialized

output

this

the

flip-flcp

The

Counter

transmitted.

the

maintain

data

the

levels
also

track

Bit
when

received

also

the

logic

clock

shift

the

signals

the

from

controls

uses

maintenance

Stuff

into

the

the
register.

modem

for

logic

internal

transmitted

the

allows

the

clock

comes

from

flip-flop.

flip-flop

The

output

the

and

then

the

mode,

Two

the

this

¢-7

the

The

output

synchronized

TDS

flip-flop

modem.

The

the

with
1is

output

Counter.

consecutive

information

control

outputs

making

number

transmitting

decision

TDS

sent

transparency.

DPCR

replaced

that

clock.

keeps

decisions

the

Silo

clock

group

loaded

logic

protocol

goes

data

buffer.

Counter

transmitter
EIA

Data

the

clock.

and

the

DPCR.

Separate

information
DDR

Out

1logic.

converted

back

derive

clock

flip-flop

modem

the

and

transmitter

single-stepped

and

signals.

characters
the

counter

Counting

used

and

are

fed

make

consecutive

allows

data

the

abort

logic

flag

TCSC

stuffs

number

counter

bits

and

generates

the

SACT,

the

(01111110)

removes

appear

the

data

the

decide

five

bit

whether

character

consecutive

stream,

prevent

the

data

the

stream.

stuffed

number

exclusive of
control

for

all

sending
The

the

receiving

0Os.

transmitter

data

path

DATA

flip-flop

data.

Shift

sets

logic

when

the

Out

for

the

It also counts the

counts

for

synchronizes

the

current

CRC

character,

action

microprocessor.

the

microprocessor
the

the

transmitter

DONE

character

flip-flop

has

been

set,

DONE

still

set

hardware

sets

the

DATA

LATE

character

bit

Silo

data

last

SACT

Data

that

set,

sets

when

transmission,

character,

the

each

0s.

Flip-Flops

informs

When

transmitter

LATE

bits

stuffed

others.

MAX

and

character.

TCSC

SACT

time

the

pulse

DONE

During

counts

transmitter.

character

consecutive

transmitted,

character

that

flag

logic

Counter

that is

The

control

five

automatically

TCSC

The

When

configuration

station

The

character,

stream.

the

transmitter

had

propagate

not

been

through

when

the

4-8

the

active.

ensure

loaded

the

loaded

status

into

end

with

silo.

the

flip-flog.
the

the

continuous

transmitter

the

cleared.

the

current

This

Transmitter

indicates

character

Shift

The

shift

the

information

data,

Bit

Stuff

bit

serializes

data

SER

and

CRC

OUT)

Out

starting

Logic

sync

with
goes

Silo

This

includes

characters.

the
to

Data

LSB.

the

The

Data

with

The

serial

Decode

ROM

logic.

characters

bit

protocol.

The

described

below.

RCS

logic

read-only

the

receiver.

The

Decode

memories

ROM

decodes

characters,

flag

enabling

the

The

Function

the

timing

The

Receiver

DELAYED

the

receiver

accordance

six

the

logic

with

functional

the

controls

the

network

units

that

signal,

selected,

the

are

0Os.

state

the

of
the

synchronizes
them

ACTIVE,

ACTIVE.

4-3

flip-flop

fed

back

the

and

Buffer

controls
Register.

stores

with

and

for

sync

controls

receiver

Receiver

(RCS)

elements

recognizes

clock.

and

controlling

Synchronization

ROM

major

stuffed

characters

Function

Ore

and

Shift

interprets

are

protocol

characters,

Control

clock.

(ROMs)

Receiver

ROM

for

from

consists

The

Flip-Flop

Two

DDCMP

reception

receiver

and

the

transmitted.

shift

Control

signals

from

the

Receiver

and

character

4.2.1.5

ROMs

parallel

characters

the

from

character)

control

loaded

three

the

modem

stored

Clock

Logic

the

clock

user mode,
to

logic.

derive

Counter

The

replaced

looks

Separate

and

Counter

the

receiver

group

clock

maintenance

the

(R1BC)

for

allows
clock

uses

receiver

control

the

the modem

modem

the

receiver

clock

single-stepped

clock.

enabled

data

before

the

CFF

flip-flop.

shifted

into

This

the

flip-flop

Counter.

During Bit Stuff protocol operation, the switch from the idle state
to

the

active

state

must

start

the Bit Stuff flag character
the

Counter

CFF

flip-flop

cleared

only

only
in

the

when

this

set

the

with

signal

the

first

bit

Th&@fi

(01111110).

§3

enables

action

state

receiver

occurs.

where

This

remains

action
until

locks

the

directly

cleared.

&¢p.
flip-flo
The

Counter

counts

consecutive

The

detected.

the

Decode

abort

1s).

state

character

consecutive
protocol

ROM

some

recognize

(eight

This

\_/J

Logic

received

logic

signals

logic

internal

Enabling

clock

and

its

outputs

flag

consecutive

counter

4-/0

when

received

are

used

character

(six

consecutive

1s),

stuffed

provides

operation.

cleared

function

during

inputs

(five

DDCMP

1s),

w,f

Shift

The
in

Receiver
a

Counter

Shift

character,

bit,

control

loaded

exclusive

generates

with

signal

input
a

Physically,

Shift

registers.

its

line

unit

same

the

second

The

8-bit

Data

The

Buffer

the

(Bit

MAX H

that

the

Data

consists

two

the

number

Stuff mode).

goes

the

Function

Silo

should

bits
last

ROM

one

Data
and

Buffer

Received
parallel

for

sync

address

which

called

Buffer.
on

the

Silo

loaded

data

character

sent

(DDCMP

but

the

ADDRS

protocol)

first
+

SYNC

the

protocol).

from

From

output

(SDLC

sent

output

serial

separate

the

LSB

Extended

the

extended

this

buffer,

the

first

Receiver

data

Shift

sent

the

goes

the

microprocessor.

Silo

Data
and

its

4.2.1.6

RSRC

presents

microprocessor.
FIFOs,

0Os

data

parallel

Silo

check

serial

Receiver
Data

8-bit

secondary

The

counts

stuffed

interrelated

comparator

(RSRC)

indicate

Data

and

the

and

Counter

character.

Shift

cyclic

messages

for

received

this

data

Because

this

inputs

CRC

with

and

Logic

outputs

are

The

logic

redundancy
error

the

CRC

checking

detection.

data

IBUS

where

method

constructed

with

3341

consists

=1/

Receiver
read

the

the
is

completely

from

Data

the

independent.

circuit

implementation

encoding
of

and

decoding

Transmitter

CRC

Receiver

associated

with

CCITT

modified

codes

CRC

the
at

the

generate

typical

message

been

016417.

error,

4.2.1.7

unit

the

data

indicated

Data
set

from

for

signals

the

logic

CRC

check

CRC

Stuff

mode,

errorless,

message

specific

flag

the

end

looks
this

determine

the

mode,

DDCMP

(BCC

STATE)

the

must
is

errors.

the

1is
If

flag,

not
the

the

error.

message

protocol

message.

Logic
is

used

program
modem

only

control

and

with

allows

the

also

provides

logic

between

the

line

unit

the

line

and

unit

4-/2

low

uses

level

modem.
TTIL

speed

initiation

monitoring

and

Both

CRC

the

modem.

levels

uses

logic.

the

accumulates

character.

Bit

the

and

transmitted

For

CRC-16.

transmitted

For

that

mode

transmitter

error.

logic

Stuff

code

logic

the

Bit

without

Interface

with

uses

receiver

non-assertion

allows

The

station's

being

receiver

correct

interface

signals

EIA

Set

the

detection

retransmission

communications

uses

detection

characters.

stations

message

indicates

detect

(M8201).

all

mode

character

plus

the

read

error

only

not

requests

The

the

DDCMP

sending

This

error

information

received

read

logic

the

receiving

contents

must

does

check

message

CRC

The

the

This

bit

character.

has

asserted

the

and

CRC

and

received

the

Receiver

code

looks

message.

point,

operation,

check

the

CRC

logic

line

status

conversion
The

data

levels.

set

This
V24

logic
which

uses

supports
uses

single

double

ended

Maintenance

Logic

The
to

maintenance
select

during

the

not

Request

inhibit

the

part

Send

signals.

consists
source

the

line

other

data,

clock

clock,

EIA/CCITT

CCITT

V35

which

and
and

two

multiplexers

control

signals

unit.

the

maintenance

logic,

(RS)

and

Half

(HDX)

clock

One

signals.

for

The

receiver

Duplex

when

the

outputs

flip-flops

half-duplex

mode

are

the
used

operation

selected.

Initialization

Logic

The

initialization

and

the

logic

4.2.2

features

logic

transmitter

Major

the

Operating

Introduction
of

divided

used

section

controlled

4.2.2.1

interfaces.

differential

proper

different

ended

logic

servicing

Although

two

the

line

into

three

clear

separately

Receiver

section

simultaneously.

This

Features

This

unit

paragraph
the

sections

discusses

functional

shown

below.

No.

4.2.2.2

Section

4.2.2.3

Section

4.2.2.4

4-/1F

the

level.

Para.

Control

Transmitter

receiver

microprocessor.

Title
Modem

the

major

The

operating

discussion

4.2.2.2

Modem

line

(M8201)

unit

Contrel

that

This

paragraph

used

for

applies

remote

network

the

low

speed

applications

using Bell 208, 209, or equivalent modems.
The

modem

control

microprocessor.
All

others

some

simply

are

the

flow

modem

must

monitor

All

clock

the

first

interlocked
is

being

used

accordance

with

EIA

RS334.

the

line

unit.

4.2.2.3
the

modem

Transmitter

following

can

the

line

necessary.

The

must

Section

when

from

The

transmitter

Ring

the

modem.

with

data

from

the

clock

|
for

indication.

from

the

modem.

received

microprocessor

modem

transmitter

bit

searching

received

system,

controlled.

unit.

TSOM

starts

signals

external

the

received

emanate

receiver

conjunction

the

used

signals

(DTR)

with

control

the

starts

having

signals

not

without

transmitted

supplied

The

control

controlled

transmission

monitored

Ready

transmitter.

data

When

are

Terminal

handshaking

and

synchronization

The

Data

lines

automatically

enabled
by

status

Only

systems,

detected

and

~~/J

the

and

from

modem

section

in
is

performs

functions.

Buffers

Generates

Creates

Transmits flag, sync and abort/PAD characters.

and

serializes

CRC

check

transparent

data

transmitted.

characters.

data

9-/4-

stream.

\fl)

)

This

discussion

operation

shown

the

sheet

Transmitter

includes

DDCMP

The

and

the

Operation

basic

SDLC

the

DDCMP

Out

Data

Message

(SOM)

SOM

goes

bit

Data

modes.

circuit

microprocessor

into

functional

descriptions

schematic

transmitter

flowchart

set.

selected

sync

Mode

loads

the

Silo.

bit

Out

from

the

the
Out

then

loads

Control

the

character

Start

The
the

Out

Silo.

The

sync

the

Out

(OCOR)

character

Data

bit

character
bit

Data

Silo.

is
in

this

and

SOM

The

asserted
this

case)

are

Out

case)

bit

are

propagated

Composite

indicate

and

ready

the
at

Output

through

Ready

that

data

(the

sync

control

bits

(the

SOM

the

output

the

Out

simultaneously,

the

Silo.

/-\

both

SOM

and

EOM

transmitter

sends

set

End

unit

but

the

hangs

are

asserted

zeros.

Message

up.

4-/5

(EOM)

the

bit

SOM

bit

set,

1is

not

the

line

With

SOM

causes

and

OCOR

Request

asserted,

the

Send

(RS)

transmitter
be

asserted

logic
in

the
g —"y

modem

The

control

line

Modem

With

unit

Ready

both

SEND.

This

these

bit

data

not

Silo,

the

CRC

switch

set

OFF,

data

the

CRC

characters

for

the

and

the

unit

modem.

asserts

transmitter.

CRC

function

cleared).

the

CRC

loaded

starts.

function

are

(CS)

transmit

character

line

the

accumulation

Send

turned

included

signal

set,

CRC

not

with

CRC

ON,

SOM

Data

CRC

signals

(transmit

Clear

the

transmitted

subsequent

signals

enabling

inhibited

the

SOM

for

long

waits

(MR)

logic.

computation.

into
If

the

Out

selected

included

The

—

and

all

transmit

accumulation.

During

transmission,

end

the

which

current

indicates

DONE

character,

that

the

Out

DATA

Data

loaded

with

the

character.

Request

Send

line

being

been

transmitted

unit

reverts

for

the

one

Idle

4-/6

still

LATE

Silo
This

turned

character

state

asserted

off

not

results
after

and

(transmits

the

asserted

has

time

been
in

the

have

line

MARKS).

The

normal

ending

microprocessor

10.

EOM

bit

and

Out

Data

sets

This

transmitted

the

assertion

SOM

and

goes

down

the

cleared

the

and

the

Idle

clearing

when

the

modem

the

Message

(EOM)

bit.

the

are
bit

character

not

loaded
CRC

followed

another

state.
of

when

character

last

EOM

initiated

causes

the

End

meaningless

Silo.

unit

sequence

The

into

the

character

The

ignored.

the

assertion

character,

the

line

transmitter

shut

Out

Active

and

RS.

SEND

drops

Clear

Send

(CS).

If the assertion of EOM is followed by the assertion of
SOM,

Transmitter

transmitter

Operation

The

into

the

Stuff

Mode

microprocessor

loads

the

Out

character

active.

Bit

the

remains

Control

into

Out

Data

and

SOM

null

character

Out

Data

Silo.

asserted

the

Out

the

The

Start

Out

indicate

Data

Silo.

Message

then

loads

(SOM)

bit

null

Silo.

bit

are

propagated

Composite

Output

that

4-/7

data

Ready

ready

through

the

(OCOR)

bit

the

output

the

SOM

bit

set,

are

asserted

bit

the

not

line

set

but

unit

the

hangs

simultaneously,

End

up.

the

Message

both

(EOM)

SOM

transmitter

and

sends

EOM

Zeros.

With

SOM

Request

and
to

OCOR

Send

asserted,

(RS)

the

transmitter

asserted

for

the

Clear

the

logic
modem

causes
control

logic.

The

line

Ready

unit

(MR)

signals

both

these

This

the

long

inhibited

each

signals

the

and

all

CRC

accumulation.

switch

data

and

five

the

Zero

the

are

and

all

stuffing

abort

4-/8

and

modem.

asserts

transmit

one

the

Modem
With

SEND.

CRC

cleared).

flag

character

data.

function
in

the

consists

preserve

characters.

loads

selected

transmit

characters

function

microprocessor

character

CRC

(CS)

transmitter.

included

consecutive

flag

the

When

the

unit

the

silo,

Send

that

performed

for

the

OFF,

line

set,

CRC

SOM,

aborts.

following

identity

signal

characters

stuffing

flags

the

into

without

Zero

ON,

transmitted.

the

CRC

turned

bit

loaded

character

SOM

(transmit

SOM

(01111110)

enabling

For

waits

except

the

inserting
the

During transmission, if DONE 1is still asserted at the

end of the current character, DATA LATE is asserted

which indicates that the Out Data Silo has not been
joaded with the next character. This results in the

Request to Send line being turned off after transmitting
an Abort character (seven or more 1s) and the line unit
reverts to the Idle state (transmits MARKS) .

10.

The normal ending sequence is initiated when the microprocessor sets the End of Message (EOM) bit twice.

The

EOM bit and a meaningless character are loaded into the
Oout Data Silo twice. This causes the 16 bit CRC character
to be transmitted followed by the terminating flag
character.

11.

When the terminating flag has been transmitted, the Out

Active bit is cleared (transmitter deactivated) provided
another message is not pending. If another message 1is
pending, the first data character is transmitted
following the terminating flag of the previous messagde.

If the SOM bit is asserted following the double assertion
of EOM,

a second flag is transmitted.

4-/9

Transmitter

The

CRC

use

code

With

the

all

This
the
the

check

DDCMP

has

CRC

the

Stuff

initialized.

This
at

the

used.

Bit

CRC

The

Stuff

logic.

DDCMP

type

ang

transmitter

Two

cyclic

family

are

CRC

accumulates

not

the

included

transmitter

been

CRC

protocols

CRC

end
in

¢f

the

check

the

looks

character.

message.

calculation

part

reads

all

cleared

right

after

transmitted.

mode,

the

allows
end

character

detection

trailing

the

transmitted

The

may

This

check

are

the

This

sequence

necessary

that

0Os

when

the

CRC

because

requires

computation

edge

cleared

detection
the

of
of

transmitter

message

the

€rroneous
message.

after

the

reads

the

addition

due

complemented

the

right

CRC

erroneous

before

being

addition

the

check

all

deletion
flag

4.2.2.4

Receiver

following

functions.
Buffers

data.

Section

and

The

converts

receiver

mode,

character

received

4-20

section

serial

has

performs

data

when

characters.

transmitted.

deletion

DDCMP

the

been

transmitted.

character.

leading

allows

the

character

Bit

(cleared).

another

CRC

and

transmitted

mode,

The

codes

enable

character.

character

the

enabled,

stuffed

off

CRC-16

character

the

(CRC)

function

mode,

initialized
check

code

Generation

CCITT.

bit

CRC

the

use

CRC

SDLC

must

checking

data

Character

switch

redundancy
protocols

CRC

the

parallel

Interprets transparent data stream in SDLC mode
stuffed

0s).

and

flag

Recognizes

abort

sequences.

Recognizes secondary station address
SYNC

CRC

(SDLC mode)

and

(DDCMP mode).

characters

Detects

(removes

errors.

This discussion includes basic functional descriptions of receiver
operation in the DDCMP and SDLC modes.

A related flow chart is

shown in sheet 2 of the circuit schematic print set.

Receiver Operation In DDCMP Mode

The microprocessor loads the network sync character into
the Sync Register.

The output of this register goes to

one branch of the ADRS+SYNC comparator.

The other branch

of the comparator comes from the output of the Receiver
The comparator looks at the output of

Data Register.

the Receiver Data Register on a bit by bit basis
searching

for

sync

character.

Reception of the first sync character causes FRAME to be
asserted.
received,
characters

If a second consecutive sync character is not
FRAME

is cleared and the search for sync

starts over again.

When at least two

consecutive sync characters have been received,

4-2/

the

receiver

ACT

MESG

The

set.

ACT

This

the

received

The

CRC

data

examines

the

received

8-bit

the

first

Data

character.

control

that

the

following

data

receiver

data

Silo,

microprocessor

MESG

RDY

that

and

IN
is

the

ACTIVE
off.

The

BCC

The

bit

asserted,
receiver

CRC

reads
MATCH

CRC

check

flag

the
is

asserted

decides

the

BCC

flag

when

the

microprocessor
MATCH

the

and

processing.

errors.

reads

When

switch

data

point

the

for

CRC

all

which

contains

output

enabled

character

mode.

The

the

synchronized

microprocessor

informs

the

ready

that

Receiver

provided

the

reception

which

assembled

asserted

informs

function

message

non-sync

bit

reaches

character

set

data

asserted

considered

first

being

character

The

ACTIVE

logic.

logic

when

valid,

the

and

message

when

the

ends,

when

receiver

should

cleared.

Operation

the

Bit

Stuff

primary

secondary

Stuff

modes

Mode

mode,

the

secondary

switch

mode,

all

the

primary

the

microprocessor.

unit

station.

are

line

4-22

The

operate
primary

and

selectable.

received

can

the

messages

secondary

are

mode,

presented

the

only

messages

that

presented

are

the microprocessor

those that are preceded by the line units'

secondary

This address is an 8 bit character that follows

address.

character.

flag

initial

the

are

The secondary address is loaded into the Sync Register
From the Sync Register,

by the microprocessor.
the ADRS+SYNC

receiver

The

comparator which examines the received data

line units
ACTIVE

character

flag character.

In the secondary mode,

the

asserted.

the microprocessor.

IN ACTIVE

that the receiver

informs

the microprocessor

in the data reception mode.

first data character

In the

all data subsequent to the secondary

presented

IN RDY

flag

all data subsequent to the

is presented to the microprocessor.

assertion of

Silo,

initial

secondary address must be received before

secondary mode,
address

secondary address.

IN ACTIVE is asserted upon reception

In the primary mode,

the

first data character.

of the

The

line unit

for

searches

the primary mode,

the

detect

in order

it goes to

reaches

the output of

asserted which informs

that received data

ready

4-23

the

When
In Data

the microprocessor

for processing.

During

data

all

stuffed

The

assertion

provided

CRC

message

bit

BLOCK

the

1is

codes

and

the

receiver

and

code

The

receiver

CCITT

enables

the

CERC

off.

data

and

the

errors.

for

removes

this

function,

The

receiver

bit

CRC

check

reads

016417

case,

the

BCC

flag

the

MATCH

the

with

Thus,

the

cleared

high

byte

microprocessor

assertion

terminating

BLOCK

errorless

BLOCK

the

CRC

should

END

and

message.

look

BCC

MATCH

The

receiver

END.

Checking

transmitter,

CRC

the

1logic.

SDLC

The

the

same

CRC

CRC-16

for

SDLC

family

protocols.

examines

mode,

this

all

switch

cyclic

code

the

when

loaded

reception

used:

CRC

automatically

switch

all

time

simultaneous

Character

are

CRC

asserted

automatically

(CRC)

which

the

character.

indicate

enable

ACTIVE

examines

character.

the

case

the

CRC

receiver

asserted.

received

for

contains

END

check

the

O0s.

that

character

Receiver

reception,

the

DDCMP

must

redundancy

family

and

the

includes

all

information

4-24

checking

protocols

data

off

bit

CRC
between

the initial and terminating flags and excludes intermessage flags
and

stuffed

Os.

In the DDCMP mode, after reception of the CRC check character, the
receiver CRC register reads 0 if the message contains no errors.

In the SDLC mode, the register reads 016417 if the message contains
errors.

DETAILED

4.3

DESCRIPTION

Introduction

4.3.1

The detailed description is divided into 10 major sections as shown
below.

Para.

Description

4.3.2

Reglisters
Out Control

4.3.3

Logic

4.3.4

In Control Logic
Transmitter Control
Receiver
CRC

Logic

Control Logic

*Data Set

Interface

Maintenance

Logic

Initialization
**Tntegral

only

**M8202

only

4.3.5
4.3.6
4.3.7

Logic

*M8201

No.

Logic

Modem

Logic

4.3.8
4.3.9
4.3.10
4.3.11

The

discussion

Supplementary

4.3.2
The

keyed

the

illustrations

circuit

are

schematics

included

the

order

unit

shown

contains

nine

registers

and

they

set.

text.

Data

Silo

Out

Data

Out

Control

Sync

Reserved

Registers

(2)

primarily

operation

Chapter

Data

Silo

data

The

received

the

silo

Control

received

data

IBUS

covers

DEVICE

where

the
it

contains

bits.
are

the

logical

registers.

from

and

4.3.2.7

4.3.2.8

the

data

4.3.2.5
4.3.2.6

discussion

with

4.3.2.3

contained

No.

4.3.2.4

Maintenance

the

4.3.2.2

Control

4.3.2.1

Modem

4.3.2.1

discussed

Para.
Register

Silo

Control

functional

are

below.

the

Registers

line

This

description

and

each

bit

REGISTERS.

The

Receiver
is

implementation

read

Data

form

The

other

discussed

Data

the

8-bit

four

Silo

buffer

presents

loaded
this

microprocessor.

characters.

bits

Paragraph

are

Physically,

part

4.3.2.4.

the

The In Data Silo is comprised of three 3341 64 word-by-4 bit
propagatable registers called silos or FIFOs (first in/first out).

At this point, the discussion digresses to explain the operation
of

the

3341

FIFO.

The logic symbol for the silo is shown in Figure 4-2.
are DO-D3 and the outputs are Q0-Q3.

The inputs

There is no common clock so

the inputs and outputs are completely independent.

SHIFT IN is a

control signal that is sent to the silo and INPUT READY is generated
by the silo when space is available.

When INPUT READY and SHIFT IN

are high, the input is loaded into the top word position.

INPUT

READY goes low and when SHIFT IN goes low, the 4-bit word propagates

to the second word position (if empty) and on to the bottom of the
silo by

internal

control

signals.

When data has reached the bottom of the silo, OUTPUT READY goes

high to indicate the presence of valid data.

When OUTPUT READY

and SHIFT OUT are high, the bottom word 1is transferred out of the

silo.

This causes OUTPUT READY to go low but the word is maintained

in the output stage until SHIFT QUT goes low also.

At this point,

the word in the adjacent position is transferred into the bottom

position which causes OUTPUT READY to go high again but the data
does not change.

If the silo has been emptied, OUTPUT READY stays

low.

In this application, three 3341s are connected to provide a register
64 words deep by 12 bits wide (Figure 4-3).

Two devices (8 bits)

represent the In Data Silo and one device (4 bits) represents bits
0-3 of the In Control register.

The discussion now returns to the

4-27

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MASTER RESET

b
-

Eguvalent Logic Block Driagram

Figure

4-2

Logical

Representation

4-28

3341

FIFO

®©3ed OTTS

1oP4m

—

7-29

description

circuit

the

schematic

1In

Data

Silo

and

associated

logic

shown

D12.

—

The

Data

are

three
The

Silo

read

3341

FIFOs

additional

the

form

bits

are

loaded

described

The

inputs

from

the

The

INPUT

signal
that

Receiver
RDY

D12

the

silo

Maintenance

Data

and

the

74S11

ready

Silo

out

received

bits

together.

data

words

that

composed

0-3.

deep.

Although

Control

(The

Control

RDR

4.3.2.4.)

that

Physically,

Control

Silo

bits

Paragraph

Data

bit

shifted

outputs

ICIR

the

and

are

separate,

the

microprocessor.

functionally
0-3

contains

They

are

D11

represent

three

FIFOs

are

3-input

AND

gate.

input.

The

SHIFT

inputs

the

ANDed

D11

RDR

data.

indicates

three

the

FIFOs

are

connected to D11 RSIP H (Receive Shift In Pulse) which is asserted
by

the

receiver

assembled.

the

3341

The

FIFO.

control
width

The

logic

when

this

pulse

common

SHIFT

the

RDACP

(Receive

Data

Accepted

Silo

been

read.

clocked

RSO

Data

The

RSO

flip-flop.
it

has

flip-flop

The

always

when

signal

Pulse)

this

which

pulse

the

4-30

character

dependent

clocked.

This

OUT

D-input

set

received

comes

has

the

from

the

The

signal

asserted

approximately

positive-going

edge

been

speed

flip-flop
clock

produce

flag

bit

the

received

This
is

output

connected
is

when
60

the
ns

this

wide.

negative

pulse.

The

RDY

outputs

INRDY

D12

signal

to produce

OUT

the microprocessor

that

received

output.

the

INRDY

not

clears

The

the

CLEAR

input

ready

the

silo

output,

the

RSO

ICLRP

flip-flop

RESET

When
is

this

Out

Silo

D12

three

goes

low,

three

available

INRDY

part

transmitted

the

shift

FIFOs

are

the

silo

the

Signal

connected

clear

the

reset

discussion,

8-bit

directly

cleared.

device

the

data

operation.

this

D12

When

sends

silo

low which
out

ANDed

informs

the

and

are

flag

flip-flop.

microprocessor

FIFOs

This

gate.

the

considered

data

inhibits

the

clear

Data

information

signal

controlled

specifically

4.3.2.2

inputs

and

the

74S11

Control

ICLRP

Shift

goes

MASTER

Silo

bit

D14

D14
receiver

function.

the

that

Out

Data

accepts

Transmitter

Physically,

composed

that

words

deep.

operation

the

Out

Data

Silo

which

described

Bits

8-11

the

Output

the

Out

Control

Paragraph

Data

Silo

three
The
is$

3341

FIFOs

architecture

similar

the

form
and

12-bit

basic

Data

Silo

4.3.2.2.

are

which

4.3.2.3.

4-31

associated

are

with

described

bits

0-3

Paragraph

The

Out

inputs
via

Data

are

TBO

H-D4

buffer.

completely

FIFO

hence,

and

Transmitter

Some

Silo

Shift

TB7

outputs

functions

are

the

When

space

the

that

input

cleared

they

come

from

the

The

BTBO
3341

the

from

inputs

FIFO

has

the

examining

BTB7
and

the

described

DS8.

The

microprocessor
H

and

outputs

common

devices

that

the

silo

top

two

positions

available,
FIFO

silo

internal

Assume

shown

controlled

internal

bottom

are

the

are

clock.

internal

logic

logic;

(DS8).

detail.

Conditions

assumed

logic

sequence

therefore,

are

evident

load/unload

and

because

are

not

Initial

independent

they

typical

The

associated

is
so

the

INPUT

and
RDY

There

OUTPUT

RDY

characters;
1)

are

output
data

output

empty.
goes

the

goes

high

flip-flop

Also

SHIFT

assume

OUT

cleared

that

the

low.

input

the

SHIFT

TSOP

flip-flop

NOTE

The

silo

with

one

set

three

composed

high

function.

TSIP

low.

the

function.

FIFO

the

contains

described

inputs.
FIFOs.

4-F2

functional

Actually,

unit

1is

The

silo

has
a

character

loading.
loaded

this

first

Loading
With

indicated

the

and

that

and

INPUT

driving

connected

then

RDY

the

SHIFT

the

SHIFT

load

the

Out

Data

Silo,

is
a

SEL

input

edge

character

After

the

internal

RDY

Now,

loaded

under

TSIP

the

was

remained

for

available

for

un-

unloaded.

both

INPUT

loaded

had

When

pulse

sets

the

top

loaded,
In

This
IN

internal

goes

and
the

the

low.

4-d3

silo,

its

goes

this

goes

low,

word

and

low

drives

SHIFT
RDY

input

high

flip-flop

second

again.

positive-going

RDY

signals.

high

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ALU

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for

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devices

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the

D11

negative

CLEAR

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unit

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L
of

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the

H).

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be

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OBUS

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The

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clear

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comparator

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edge.

flip-flops.

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connected

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Sync

quad

common

pulse

considered

the

are

signal

output

74175

microprocessor

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two

This

its

compared

the

sent

The

the

are

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Sync

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ALU

the

The

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stored

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clocks

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Signal

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microprocessor

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circuit

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protocol, the comparator looks for a sync character.

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Figure 4-9 is a block

diagram that shows the interrelation among the OBUS Sync register and
the

Out Data

Silo

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only

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information

line

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logic

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select

control

microprocessor

all

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microprocessor

respectively.

shown

Figure

4-11.

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example,

this

the

select

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multiplexer
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true

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Data

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4.3.5.3

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three

output

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this

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logic

additional

4.3.5.2

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Data

some

microprocessor,

the

Logic

TCSC

Out

Sync

Discussion
ROMs

the

L; Signal

the

from

edge

Control

The

RDACP

shows

which

input

the

Transmitter

output

are

CROM

trailing
in

reading

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to generate

positive-going

4.3.5

4-11)

selected

microprocessor,

third

therefore,

RSO

goes

Figure
with

Silo

inverted

associated

Data

This

the

(and

high.

into

4.3.5.1

(ROMs)
Each

ROMs

are

one

the

organized
shown

and

ROM

major
1024

256

Sync

Buffer

controlling

bit

words

TTL
of

ROM
4

Three

elements

(5603

bits

each.

read-only

for

the

transmitter.

equivalent)
The

ROMs

Decode

Data

Path

Data

Decode

Both

enabling

bit

ROM

the

always

control

replace

ROM

(DPCR)

D7
D7

(pins

coded

and

14)

while

power

address

that

through

least
1s

held

low

applied.

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inputs

represent

one

words

selects

255).

significant

are

The

bit

unalterable.

any

most

When

same

states

elements,

the

ROMs

act

compact

amount

distributive

Each

addressed,

the

keep

256

significant

produces

large

No.

(DCR)

addresses

and

constantly

pre-programmed

word

identified

(FDR)

inputs

binary

(decimal

ROM

Control

enabled

below.

Function

that

are

Name

ROM

memories

the

four

bit

word
a

the

specific

outputs.

logic

arrays

that

logic.

A listing for each ROM is contained in the print set (drawing ED ik
The

listing

address
Many

contains

along

addresses

meaningless

with
form

are

input/output
brief

note

combinations

not

allowed.

binary

what

459

the

inputs

These

illegal.

equivalents
address

for

each

represents.

that

are

functionally

addresses

are

defined

The

circuit

contained

Figure

The

path

connected

on
a

control

directly

D14

inverter
side

prints

for

the

and

ROMs

D7.

simplified

has

its

enabling

ground.

The

other

TEST

switch

through

ROM

POINT.

D14.
in

This

The

switch

resistor.
switch

enabled.

During

simulate

the

used

following

signals

associated

functionally.
only

when

with

Some

viewed

the

signals,

group

This

shown

(pins

D14

the

ROMs

the
TEST

7404

one

also

closing

connected

switch
PT

14)

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and

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ROM.

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and

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specifically
during

and

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connected

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output

point

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discussion,

ROMs

other

ROMs

two

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inputs

the

SP3.

keeps

logic

diagram

pack

the

signal

inverter

With

associated

grounded.

can

and

4-12.

data

signal

schematic

destiration

sync
ROM

specific

buffer
inputs,
point

the

are

described

have

relevance

transmit

operation.

Function

Decode

This

controls

ROM

microprocessor

ROM

the

inputs

the

modem

clock.

the

logic

determines

This

FDROM

responds

shown

4-1.

Table

the

setting
which

some

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the

DONE
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along

event

microprocessor,

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D14

Function

4-1

Decode

ROM

Input

DDCMP

Signals

Source

Microprocessor

via

bit

Maintenance

D14

D16

CRC

SEND

Hardware

switch

and

E29

AND

function

DATA

SENTXAC

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SEND

FLG

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Buffer.

LOAD

no.

using

M8201

SEND

and

M8202).

CLEAR
from

the

modem.

Decode

ROM

via

ROM

from

of
ROM

SCRC

Sync

Control

4-62

and

via

bit

This

bit.
control

Sync

Buffer.

indirectly

Transmitter

no.

(E26

Microprocessor

Out

switch

READY

function

silo
D7

SET

Function

pack

SSOM

selectable

logic.

from the

four outputs

the

Three of

input gating for the TX DONE flip-flop.

This

ROM are

sent to

and

D6 TCRC H,

goes to the preset

(D6 ENTXDNE H)

fourth output

The

D6 TFLG H,

These outputs are:

the ROM Sync buffer.
D6 ENTXAC H.

function decode

signal allows this

flip-flop to be set directly at certain times during a transmit
sequence.

ROM

Sync

Buffer

Tfie ROM Sync buffer is a 74174 hex D type flip-flop that has a
$ix

for

storage

flag or sync

each input.

for

(Q=H=1)

single-rail output

transmitter

logic

control

characters have been sent,

clocked only at the

end of a character.

The buffer provides
signals.

the

After

the ROM Sync buffer
This allows the

logic

to set up for the next character during the present character
affecting

not

while

clear

clock and
are?

TFLG

D6 SFLG H,

inputs.

TCRC

outputs are:

which

SABORT

Two gates
for

the

Three

0).

buffer.

the

come

inputs

and ENTXAC

(Out Control

Control register bit

(1)

outputs

has

from the

The

is hardware controlled,

The

They

outputs

are

fourth and f£ifth inputs
1)

and D8

sixth

(Out

TSOM H

TEOM and TSOM are silo bits.

D6 SEOM H and D6 SSOM H.

common

FDROM.

corresponding

The

D6 CRC H and D6 SENTXAC H.

TEOM H

are:

the

input

The corresponding
is D6 DATA LATE

and the corresponding output

and

several

ROM Sync

first bit of the

signals

buffer.

are used to provide the

During the

sync character

idle

(DDCMP)

403

state

clock signal

and up until

or flag character

the

(Bit

Stuff

protocol)

SACT

LOAD

this

the

transmitted,

high.

buffered

This

Signal

and

ANDing

1is

signal

goes

LOAD

ACTIVE
to

ANDed

cleared.

7432
with

OR
D6

inverted

transmitter

clock

from

LOAD

buffer

positive-going

ACTIVE

OUT

cleared,

The

leading

edge

the

ROM

Sync

buffer

set,

SACT

goes

low

for

CLK

gate

and

TXCLK

the

clocked

result,

emerges

which

modem.

actually
L.

The

result

clocked

long
once

0OUT

each

bit

time.

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OUT

low.

TCSC

counter

the

ACTIVE
LOAD

TCSC

ANDed

goes

high

again

reaches

the

last

counter

with

CLK

buffer.

The

Sync

one

associated

Except

during

buffer

outputs

The

the

transmitter

CLK

which

LOAD

time

only

when

the

this

time,

TCSC

LOAL

Pulse

which

this

phase

transmission,

the

FDROM

ROM

Sync

buffer

the

clocks

case

the

ROM

the

This

Sync

allows

anticipation

current

character.

event

the

thus

modem.

can

considered
because

current

inputs

with

and

the

end

MAX

the

derivative

clock

unit

clock

drives

character.

pulse

line

are

ard

bit

interferring

outputs

modem

last

change

without

synchronizing

only

CLK

short

generate

the

bit

positive

start

clocked

event

clocked.

with

the

microprocessor

The

asserts

ROM

the
the

change

464

when

synchronized

buffer
modem

only

clocked

clock.

to
by

the
D6

Data

Path

Control

ROM

The data path control

control
The

characters
inputs

DPCROM

and
are

(DPCROM)

controls
shown

Table

Transmitter

Signal

D14

DDCMP

Data

Path

formats

the

Bit

Stuff

protocol

transmitter data path multiplexing.
4-2.

Table

4-2

Control

ROM

Input

Signals

Source

Microprocessor via

bit

Maintenance

SABORT

Transmitter

control

logic.

D6 SFLG H

Function Decode ROM via ROM Sync

buffer.

SCRC

Ground

T1BC=6 H

T1BC=5

LOAD

)

T1BC

Counter

“—

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Transmitter

4¢%5

control

logic.

Three

the

outputs

are:

output,

four
D7

ENTCSC

signal

not

transmitted
prevent

Data

data

the

timing

The

four

Signal
Shift

ROM

DDROM

ENTCRC

high

low)

the

data

and

signal

allow

when

from

counted

being

ENTXSR

for

the

TCSC

ROM.
H.

being

fourth

counter.

count.

stuffed

counter

These

The

TCSC

counter

the

decode

the

therefore,

and

ENTXSRC

(DDROM)

clock.

character;

CRC
is

from

are

are:

This

into

the

inhibited

(Bit

Stuff

the

data

received

and

DPCROM.

mode

only).

Out

Data

shown

ENTXSRC

Silo

from

also

controls

the

Shift

Table

4-3,

CRC

CLK

for

the

Transmitter

qualifying

This

asserted.

conditions:

multiplexes

CRC

TXDT

following

inputs

outputs

TXBUF—>SR

enabling

(goes

transfers

DDROM

ENTXSRC

stream;

stuffed

the

must

The

ROM

shift

TXBUF-—>SR

the

outputs

asserted

decode

data

Decode

The

TSPACE

ENTCSC

Signal

DPCROM

during

information;

input
can

signal

not

transmission

when

asserted.

466

clocked

only

asserted

Bit

during

Stuff

stuffed;

when

and

the

mode

control

when

Table

Transmitter

4-3

Data Decode

ROM Input

Source

Signal

Signals

Buffer.

D6 SSOM H

ROM Sync

D7 LOAD H

Transmitter control logic.

Data Path Control

ROM.

Data Path Control

ROM.

TXCRC

Data Path Control

TSPACE H

Ground

ENTCRC

TCRC

ENTXSR H

OUT

SER OUT

Shift

4-67

ROM.

Signal

CRC

CLK

This

can

clocked

This

signal

being

not

qualifying

asserted

TXBUF—>SR

Control

information

Signal

TXDT

transmitted.

TDS

only
when

input

when

control

for

CRC
Oor

from

CLK

sync

CRC

asserted.

characters

are

The

must

asserted

loaded

into

allow

the

the
to

Data

the

output

Decode

ROM

flip-flop

the

TDS

which

This

arrangement

ensures

that

the

transmitted

with

the

edge

the

modem

transmit

The

TDS

the

modem

clock

flip-flop

has

4.3.5.2

supplied

internal

Shortly

clocked

only

ns.

synchronized

after

TDS

captured

Clock

0-7

the

(This

integral

modem

data

turn

goes

be
to

the

(M8202).

data

clock

synchronized

keep

minimum.

flip-flop

considered
edge.

the

flip-flop

(M8201)

distortion

Shift

represents

logic

leading

bits

transmitted.)

goes

flip-flop.

conversion

the

transmitted.

Signal
Out

the

Logic

modem.

clock

maintenance

clock

logic

Maintenance

Logic.

the
a

bit

the

step

user

logic
clock

discussed

4-68

CLOCK
the

modem

data

Special

single

Hence,

clocks

the

D15

bit

TDS

which

offset

flip-flop

transmit
on

the

clock

line,

from

leading

the

transmitted.

mode,

the

allows
during

transmitter

selection

maintenance.

Paragraph

4.3.9

clock

an
This

The

transmitter

the

level

Figure
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conversion

4-13.

The

interface

interface.
4-bit

clock

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outputs

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4-66

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Discussion

Paragraph

RCS

4.3.6.1

Flip-Flop

Logic

Counter

4.3.6.2
and

Enabling

Shift

Counter

Shift

and

Data

4.3.6.3
4.3.6.4

Data

Buffer

4.3.6.5

Silo

4.3.6.1

4.3.6.6

ROMs

Two

read-only

for

the

and

ROMs

that

are

RCS

Flip-Flop

memories

receiver.

equivalent)
The

Logic

Each
is

(ROMs)

are

one

1024

256

organized

identified

shown

the

major
bit

controlling

TTL

words

ROM

(5603
bits

ROM

Function

each.

below.

Name
Decode

elements

"Print No.
(DR)

ROM

D10

(FR)

D10

Both enabling inputs (pins 13 and 14) are held low to keep the
ROMs

enabled

represent

256

bit

word

constantly
8

bit

while

binary

power

that

0-255).

The

most

significant

bit

addresses

and

least

specific

pre-programmed

word

always

and

The

address

(decimal
the

applied.

coded

words
15

produces

unalterable.

the

same

outputs.

4-87

inputs

selects

states

one

significant

When

any

Each

addressed,

the

four

The

circuit

contained

Figure

Both

schematic
prints

are

Paragraph

the

enabled

receive

Decode

This

flag

signal

with

Some

only

signals

when

viewed

ROM

decodes

characters
Shift

the

simplified

D14

TEST

Source

ROMs

logic

diagram

POINT

and

RCS

specifically
as

and

protocol

stuffed

group

shown

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described

destination

the

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are

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during

Two

the

Decode

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the

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D14

RSRC

DDCMP

described

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specific

ROM,

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Decode

D10

Function

for

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logic

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selected,

0s.

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internal

ORed

associated

point

operation.

and

the

microprocessor

RSRC

and

ROM

Receiver

are

D11.

discussion,

associated

functionally.

and

ROMs

4.3.5.1.

following

relevance

D10

the

4-19,

ROMs

signals

for

ROM

shown

FRM

the

Table

and

The

third

the

clock

for

fourth

provide

4-88

D10

the

ROM

the

4-4 .

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ADDRS+SYNCAH,

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ocutput,

Function

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enabling

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ROM.

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sync

D10

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ROM

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RCS

flip-flop.

7
6

D10

R1BC

Function

ROM

This

interprets

pack

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sync

logic

selectable

Function

Output

The

R1IBC

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From

D10

timing

bit

;

ROM

switch

via

ROM

shown

the

state

the

receiver

and

characters

the

Receiver

Buffer

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the

microprocessor

4-5.

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controls

and

the

Table

Receiver

Function

Signal

D14

DDCMP

4-5

ROM

Input

Signals

Source

Microprocessor
Maintenance

D14

SEC

MODE

Hardware
switch

D11

INACT

(1)

From

D11 MESG ACT (1) H j

flip-flop.

D10

ADDRS+SYNC

Unlabeled

RECD

From

RSRC

MAX

switch

Function

Decode

using

pack

no.

via

RCS

ROM

a
1.

ROM

function

and

D11

bit

selectable

D10 EN FRM H

via

From

4-9/

D14

DDCMP

RSRC

D10
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Counter.

FLG

RECD

RCS

Flip-Flop

The

Receiver

quad

D-type.

are:

D10

(Print

Control
It

FRAME

(D11

fourth

input).

RCOD

which

200

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ve
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RCS

flip-flop

gate.

Signal

Control

RCS

also

can

signals

D10

the

clear

the

abort

sequence

4.3.6.2

RCS

D10

MESG

fed

back

for

the

modem

The

AND

7408

RCS

RECD

clock

when

the

error

ICLRP
the

and

condition

D10

FLG

AND

and

gate

This

condition

1s)

the

D10

clock.

bit

time.

flip-flop.

via

CLEAR

7402
bit

initiates

single
is

that

RECD
two

exists

are

asserted

signals

inverted
exists

when

appears

directly
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Bit

Stuff

received.

user

Special

logic

D14

They

the

microprocessor

these

RCS

ROM.

each

the

when

modem.
or

asserted

function

clock

once

74175

ACT

flip-flop

receiver

unit.

Logic

internal

clocks

cleared

line

set

the

edge

directly
ICLRP

Maintenance

that

trailing

supplied

maintenance

and

generated

This

signal

flip-flop.

Clock

Function

pulse

the

INACT

(1)

flip-flop

from

the

ADDRS+SYNC

output

ACT

cleared

simultaneously.

signals

clearing

D10

(RCS)

derivative

D14

general

three

clock

positive-going

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step

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clock

discussed

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the

selection

during
in

clock

maintenance.

Paragraph

4.3.9

the

The
in

receiver

clock

signal

from

the

level

conversion

logic

Figure

4-20.

The

goes

V24

interface

interface.

signal

The

75107

outputs

the

modem

which

these

shown

1489

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goes

to
in

receiver

receivers

print
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receiver

D16

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EIA/CCITT

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2-input

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SO0

determines

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input

closed

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input

the

low

switch

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RECEIVE

MUX

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SRC

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inverse

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single

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the

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Figure

4-21

signal

D15

NAND

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SRC

another

7400

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D15

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counter.

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receiver

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signal

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R1BC

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clear

input

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directly

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the

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always

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pulse

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the

that

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4.3.6.4

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of

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Sync

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Bit

Stuff

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bit

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second

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shift

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received.

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Data

Silo

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unit.

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Silo

detailed

contained

one

discussion

Paragraph

the

eight

the

operation

4.3.2.2.

CRC Logic

4.3.7.1

General

transmitter

the

signal

registers

This

clock

future

Data

4.3.7

which

for

reserved

4.3.6.6

the

RCOD

outputs

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D10

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detection

abort

signal

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buffer

DEL ACTIVE H which
H

time.

data

(1)

identified

are

inputs

represented

error

bit

the

framed.

receiver

data

each

when

INACTIVE

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point

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D11

ROM

D11

signal

mid

controlled

Function

and

discussion
order

shown

This

receiver
is

discussion

cyclic

divided

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covers

redundancy
four

below.

4-/0'7

the

operation

checking

sections

that

(CRC)
are

the

logic.

covered

Some

Error

Transmitter

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Typical

background

Chapter

Error

used

only

must

computes

plus

the

its

stations'

that

the

CRC

transmitter

information

Detection

the

stations

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and

receiver

cyclic

CRC

computations.

redundancy

checking

found

INTRODUCTION.

4.3.7.2

end

detection

receiver:

have

CRC

the

protocol,

however,
logic

character

for

the

The

message

protocol,

The

CRC

character.

CRC

their

message.

CRC

Logic

has

must

been

receiver

must

the

of
a

the

detection

sending
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and

station

end

contain

error

enabled.

message

received

CRC

read

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receiving

CRC

and

codes

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definition

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for

defined

use
and

message

message,

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receiving

value

indicate

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the

specific

free.

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read

logical
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=
=

+3
0

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logical

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different

Bit

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4-108

the

error

examines

016417.

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stétion

NOTE

receiving

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transmits

logic

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Bit

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detection

comparator

CRC

8242

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high

when

bare

logic

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collector

message.

check

gates.

match

output

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its

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high

and

both

circuit

output

Figure

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0

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character

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logic

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pulse

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a

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both

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the

input

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output

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gate

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pass

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gate

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active

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function

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signal

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(1)

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the

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sets

character

set

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all

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the

data

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transmitted

message

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character

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are

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the

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the

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character

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being

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data

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shifted

being

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CRC

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the

output

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after

character,

alteration.

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not

transmitted

the

accumulate

simultaneously

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disabled

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character.

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process.

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transition

contribution
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determine

SCRC

that

the

SDLC

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makes

character

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the

not

the

Logic

message

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feedback

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data

station

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path

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operation

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low

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from

non-inverting

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CRC

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due

the

deletion

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the

mode).

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leading

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bit

stage

positions
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in

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the

the

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by

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signal

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bit

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feedback

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and Bit Stuff)

(DDCMP

is discussed using Figure 4-27.

In the DDCMP mode,

signal D14 DDCMP H is asserted.

This puts a high

on one input of NAND gate A and negated-input AND gate B.

The

output of gate B is held low which makes X-OR gates 5 and 12 perform
The output of gate A can be high or low

as non-inverting gates.

depending on the state of D11
and

RSR 00 H.

15 to perform the X-OR function.

This

path for code CRC-16 in the DDCMP mode.

is D11

This allows X-OR gates 2
sets up the feedback

The input to the register

RSR 00 H which is the bit 0 output of the Receiver Shift

In summary,

the state of D11

DDCMP H conditions the input logic to

set up the feedback path to conform to code CRC-16.

All data and

the received CRC character are included in the CRC computation.

At the end of the message,
all

O0s.

This

indicates

the Receiver CRC Register should read

reception of an errorless message.

Input/Feedback Control Logic

(Bit Stuff Mode)

In the Bit Stuff mode, D14 DDCMP H is low which qualifies gate B and
disqualifies gate A.

Qualification of gate B sets up the feedback

path for operation with code CRC-CCITT by enabling X-OR gates 5 and

4-//9

12.
2

Disqualification

and

which

summary,

set

the

are

included

the

FCS

and

FCS

indicate

4.3.7.5

the

and

CRC

makes

of
them

state

feedback

character
in

the

keep
as

DDCMP

character,

the

FCS

CRC

input

code

X-OR

input

logic

CRC-CCITT.

SDLC

All

sending

station

it.

After

receiving

must

data

protocol)

The

gates

gates.

the

character

transmitting

Receiver

conditions

conform

the

low

non-inverting

computation.

before

Typical

D11

(called

CRC

errorless

perform

path

character

gate

complements

the

read

016417

shows

typical

data

message.

CRC

Accumulation

transmit

and

receive

Remember

the

following

CRC

Figure

accumulations

facts

concerning

4-28

the

CRC

Bit

Stuff

operation

mode.

the

Bit

Stuff

mode.

the

Receiver

represents

Both

After

logical

registers

the

and

CRC

Transmitter
0

and

transmit

low

signal

high

represents

signal
logical

—~

start

check

registers,

cleared

(all

character

mode,

1s) .

(FCS)

has

transmitted

been

accumulated

complementary

form.

the

receive

character,

right

the

mode,

after

Receiver

justified)

else

reception

CRC

the

4-/20

message

the

must

data

read

and

016417

error.

FCS
(LSB

showing Os being shifted into register.

CRC Accumulation

4=/2/

B @
NOTES
NOTES

showing accumulated FCS character.

Reception of 19 bit data character.

Reception of compliement of FCS character.

Contents equal 016417, (LSB right justified).

m 111-1011
1000
0010101010100
0101000101001010
0000111111010100
1110111010000011

Receive CRC Accumulation (SDLC)
Transmit CRC Accumulation (SDLC)

000
010101010
1101.1:10
1
101010000
100010010
01.I11010010100010
1011100000000111-1

2 ®

o o0

..IO.I110000011110101001011101110100000

O 0~ O - Ol = O~ rO0~~000000OOOOO0
~-~~~0~000OC
OrOlrlr-rO0-~
r
e, O OFr e00O
rr111111
010000000000
0101&110‘1‘1
..00«!0«!141
11!1;0..&1&1

1!1!01‘1-001011.1!01.01..1101110100000000000

@ Contents of register at end of message.
Transmission of 16 bit FCS character

naunsumd

- O~~~ 0 0000 rr~-~rO0rO0rOjlo-rOrrrr-~rO0r—-~-0~00O0OO0

111111000111010011111010000000000000
O OOO
0~
O000000000O
O
C
0
0
~
0
=
l
0"
OO0~
00
~lOolr00000
~00~r—e+—~v
-_-—rr
000O0O0O0OO0O0
l~rl000D0D0O00
00O00Orr "0 rO0O0~rer-rr~O
-~~~

Typical Transmit and Receive

Figure 4-28

Transmission of 19 bit dsta character
@

< z
< £

DMN- r~ m

n-3352

4.3.8

Data

4.3.8.1
The
TTL

Set

Interface

Logic

(M8201

Only)

General

data

set

logic

outside

levels

the

TTL

interface
used

line

Levels

High
Low

performs

the

line

unit.

The

logic

(Inside

the

line

=
=

logic

logical

signal

unit

and

levels

conversion

the

are

EIA

between

the

levels

used

logic

defined

below.

unit.)

EIA

Levels

High
Low

This

logic

which

uses

(Outside

=
=

single

ended

the

EIA/CCITT

1489

handled

75107

that

for

CCITT

handled

Each

different

interfaces.

One

signals.

The

CCITT

other

EIA/CCITT

V35

which

V24

uses

signals.

signals

receiver

resistor

conversion.

has

and

from

the

modem

external

are

handled

response

control

capacitor,

that

sets

signals

the

modem

The

the
are

drivers.

V35

75110

unit.)

interface,

signals

receivers.

converted
by

logical

two

V24

two-channel

are

1line

logical

differential

level

1488

ended

consisting

the

receivers.

threshold

-6

supports

double

input,

the

Each

single

two-channel

from

the

receiver

output.

drivers.

4-/E2

modem

has

are

handled

differential

The

signals

Each

driver

has

the
a

inputs

modem

single

are
input

that

converted

The

level

differential

conversion

logic

4.3.8.2

Conversion

the

that

modem

are

shown

Signals

converted

outputs.

the

TTL

levels

the

Modem

are

The

signals

shown

75107

Receiver

SET

READY

Yes

CLEAR

SEND

Yes

CLOCK

SERIAL

REC

DATA

1489

EIA

control

signals,

The

outputs

receiver

and

RING

and

D16

the

Modem

determine

1IN

CLOCK

The

the

1489

signals

D16

Control
the

inverts

RING

the

high

state

that

for

the

again

respectively.

the

and

indicates

inverted

status

signal

receivers

are

4-6.

Modem

DATA

XMIT

from

Table

1489

RING

SEND,

D16.

4-6

from

Signal

from

Table
Signals

they

are

modem.

4-/123

is
an

DATA

For

condition.

SET

READY,

produce

These
read

converting.

D16

signals
the

CLEAR

MODEM

are

program

part
to

RDY

addition,

CLEAR

SEND

enabling
to

turn

the

only

when

both

signal

the

DATA

each

2-input

With

possible

For

75107

the

signals

Two

pair

for

the

used

each
one

DATA

from

the

1489

ground;

the

inversion

action

the

switch

input

the

75107

With
A

RDY

the

multiplexer

CLOCK
for

SO0

V24)

4-124

MODEM

and

that

the

and

one

quad

from

the

inputs.

the

and

inputs

input
input

open

(OFF),

selected.

for

the

V24

Select

position
which

low

modem

8266

multiplexer
B

RDY

EIA/CCITT

two

compensates

receiver.

the

are

the

provided

READY

from

two

there

order

installed

the

switch

(EIA/CCITT

D16

asserted.

determines

(ON),

D16

between

therefore,
S0

SET

and

are

multiplexer

input

closed

selected.
of

the

W3)

interface.

SEND

applications

receiver

assert

DATA

REC

signals,

outputs

select

V35

and

ON,

1489

select

connected
to

and

asserted

removed,

MODEM

receivers:

these

1489

those

READY

gate

with

For

SET

(high)

(W2

IN,

CCITT

and

D16

DATA

AND

must

permanently

signal

SERIAL

and

jumpers

installed

are

associated

inverse

these

With

V35)

for

negated-input

outputs

chosen.

receivers

transmitter

holds

The

connected

(CCITT

receiver

READY

outputs;

receiver.

the

non-asserted.

75107

switch

and

multiplexer

interfaces.

input

the

and

the

CLOCK,

sent

interface

and

This

XMIT

transmitter.

SET

removed.

75107

for

asserted

Signals
are

ANDed

4-29).

require

are

output

outputs

SEND

(Figure
can

the

the
is

high

The

non-inverting

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4.3.8.3
modem

Conversion

that

are

Signals

converted

EIA

the

levels

Table

Signals

DTR

(Data

the

D15

RTS

TDO

The

drivers

drivers
supply

Two

supply

Signal
used
and

the

D15

the

RTS

SECS

during
off

and

installed

controlled

out,

(W4

Yes

Data)

the

signals

output

W5)

and
RS

the

switch

EIA

logic

signals

levels.

and

the

The

75110

1488

drivers

signals.

prcvided

out,

held

output
the

the

assertion

flip-flop

output

are

servicing
a

Modem

Clock)

signal

the

Ready)

single-ended

differential

Jjumpers

With

convert

4-7,

75110

(External

Table

Driver

SECS

Send)

(Transmitter
D15

shown

signals

1488

(Request

The

Driver

Terminal

are

4-7

Signal

D15

Modem

(print

the

D15).

RTS

With

the

RTS

signal

driver.

installed

and

asserted.

line

package

input

SP3

the

internal

unit.

D15

(print

4-17¢6

SECS

D15).

clock
H

that

turned

4.3.9

Maintenance

Logic

4.3.9.1

- The

General

disconnecting

this

2.
e

Test

clock.

clocking

Mode

this

mode,

must

plus

the

which

turned

the

modem

M8202

line

12-12528

the

line

Mode

the

checked

diagnostic

supplied
unit

may

unit,

the

remain

the

logic

the

receive

and

M8201
H325

program

line

unit

connected

the

H325

test

unit,

RC
to

mode,

the

cable

kHz

internal

the

connector

modem

test

connector

must

line

are

clock
simulate

clock.

cables

must

used

Clocking

supplied

4-127

line

this

the

coaxial

adapter

together.

and

the

cable.

supplied

around

transmit

coaxial

cables

For
and

BC05-25

conversion

Clocking

the

provided

disconnected

checked.

the

Clocking

Maintenance

connected

unit

For

cable

modem.

External

coaxial

microprocessor.

System

modem

coaxial

step

the

cannot be

cable

the

unit without

(M8201)

a means

mode.

Single
via

and

provides

line

the

the modem

converters

Level

(M8202).

from

mode

This

ninety percent

analyzing

for

Mode

Maintenance

Internal

described below.

are

The modes

servicing.

modes during

line unit can be operated in three maintenance

must

connect
by

the

disconnected

the

and

pig-tail

integral

modem.

The

maintenance

select

the

The

logic

proper

shown

consists

clock

and

source

for

the

data,

clock,

D15

and

Figure

4-30.

4-/28

two
and

multiplexers
control

signals.

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4-/129

4.3.9.2
and

feedback

clock
only

The

that
when

power

output

input

also

the

wave

the

shapes

RCC

D15

clock

ECS

installed

connector

Signal

4.3.9.3
the

are

D15

LINE

The

the

receiver

SEND,

LOOP

LINE

LOOP

Request

and

also

the

7404

free

line

inverters

running

unit

20K

and

stops

goes

input

is
by

10K

goes

output

and

CCITT

interface.

input

Multiplexers

Two

CLK

its

the

output

square
and

H325

test

the

1488

driver

the

cable

SRC

multiplexers

modem

and

test

multiplexer.

are

used

Multiplexer

SEL

Send

mux

controls

logic

(RTS)

and

the

source

state

Data

4~/30

received

three

Terminal

data

control

Ready

the

different

the

SHAPER

flip-flop

simulates

switch

When

signals.

V35

RCC

symmetrical

driver.

around

the

The

clock

through

the

connected
two.

actual

7510

turned

the

clock

logic.

control
to

for

The

servicing,

clock

SEL

two

output

signal

receiver

maintenance

flip-flop

which

Maintenance

for

the

clock

interface)

output.

driver

required

ECS

This

connector

1488

and

appliéd

this

flip-flop

transmitter

goes

the

V24

consists

resistors.

power

clock

input

(EIA/CCITT

clock

and

output

SHAPER

removed.

divides

the

called

The

when

the

The

capacitors

starts

flip-flop.
D

Clock

(DTR).

signals:

These four signals are outputs of the ON LINE LOOP SEL mux which

The muX strobe input is

is a 74157 quad 2-input multiplexer.

The select input

connected to ground which keeps the mux enabled.
7432

is connected to the output of a 7402 2-input NOR gate; therefore,
the input signals to this gate controls the selection of the mux

inputs.

These signals are D3 LU LOOP H and D14 R/W H.

Signal

The micro-

D3 LU LOOP H is controlled by the microprocessor.

processor asserts D3 LU LOOP H to put the line unit in the

Signal D14 R/W H is bit 5 of the In Control

maintenance mode.

D14 R/W H comes from the 1 output of a 7474

maintenance mode.
flip-flop that

is controlled by the microprocessor.

In the user mode, neither D14 R/W H nor D3 LU LOOP H are asserted
so the S0 input of the ON LINE LOOP SEL mux is low which selects
input A.

The following events occur.

(1) H

D16 SEND

(input A1)

is high because Data Set Ready

and Clear to Send from the modem are ON

asserts D15 SEND H at mux output f1.

high to

activate

D15 RS

(1)

the

! :,,\ :
!
e

(high).

This

This signal must be

transmitter.

(input A2)

is low because the transmitter

control logic has set the RS flip-flop.
RTS H low at mux output f2.

This drives D15

This signal is inverted by

4 1488 driver to put a high on the EIA Request to Send
line.
modem

This signal must be ON
for

transmission.

4-/3/

(high)

to condition the

T e <‘-n L”v:}

.
<

D16

RDATA

data

from

output

the

f3.

(1)

has

set

the

DTR

mux

output

signal

must

the

maintenance

D14

R/W

which

control

SEND

Input

high

Input

mux

(D7
at

TDLS
mux

This

drives

D15

DTR

This

signal

the

EIA

(high)

output

Data

the

SO0

prepare

following

B1)

output

the

high
RS

f2.

the

logic.

low

driver

line.

either
ON

because

which

LINE

This

the

LOOP

SEL

mux

transmitter

This

the

occur.

flip-flop.

1488

modem

events

activate

Ready

the

asserts

input

control

channel.

The

set

receiver

Terminal

processor

the

inverted

communications

asserts

D15

transmitter.

drives

D15

This

the

OFF

state

TDLS

which

RTS

for

the

EIA

1line.

This

mux

flip-flop.

connected

transmitted.

microprocessor

output

1is

the

has

Send

DATA

received

because

AO0)

connected

mux

the

low

(input

logic

Request

D15

drives

(1)

becomes

This

the

input

selected.

goes

mode,

This

signal

selects

D15

f0.

is
It

(input

high

connected

This

DTR

put

A3)

modemn.

D15

high

(input

At
.
A5

used

means

that

the

data

received

f£3).

4-/132

data

(D15

transmitted

DATA

Input BO

is connected to +3 V which drives D15 DTR H high
This

at mux output fO.

1line.

Ready

Terminal

is the OFF state for the EIA Data

The above discussion covers the 74157 ON LINE LOOP SEL mux for the
low speed line unit

(M8202).

speed line unit

A similar mux is used in the high

(M8201).

It is a 74S158 mux that is functionally

equivalent to the 74157 except that the outputs are inverted.

Because there is no level conversion logic in the M8202,

D15 SEND H is a mux output but 1its

NO SEND input to the mux.

(A1

associated inputs

and B1)

This

is selected.

is low.

The mux inverts this
input B1

the RS

flip-flop and

assert

D15

CLK

SRC

are different.

In the user mode,

is D16 CSL from the integral modem which

input A1

maintenance mode

there is

signal to assert D15 SEND H.

In the

(1)

L from

This

selected.

is D15 RS

The mux inverts this

it is low.

signal to

SEND

Multiplexer

The CLK SRC mux controls the source of the transmitter and receiver
clocks during normal operation and servicing of the
CLK SRC mux
strobe
the mux

inputs

a 74153
are

enabled.

or D14 R/W H.

dual

line-to

The

Both

line multiplexer.

connected to ground which keep both sections of
Select

input

SO0

(LSB)

controlled by

LU LOOP

Select input S1 (MSB) is controlled by D3 RUN (1) H

from the microprocessor.

clock signal

line unit.

Output f0

is D15 TX CLOCK H which is

for the transmitter control logic.

4-/33

Output f1

goes

the

one

input

gate

represents

gate

control

half

mux

D15

logic.

duplex

7400

2-input

(D15

CLK

gate

operation

shown

(1)

which

This

NAND

gate.

(D15

the

The

other

(1)

H).

HDX

clock

signal

the

receiver

inhibits

selected.

truth

input
The

for

this

output

the

clock

table

for

the

receiver
only

the

when

CLK

SCR

below.

RUN

LOOP/RW

(A)

INPUT

SELECTED

Modem

clocks

TRANSMIT

OPERATING
MODE

D16

and

CLOCK

D16

User

CLOCK

RECEIVE

(B)

Single

STEP

(C)

step

clock

Internal

Modem

Maintenance

clocks

TRANSMIT

RECEIVE

D16

and

CLOCK

D16

simulated

*External

CLOCK

Maintenance

clock.

(D)

Internal

D15

*Test
modem

connector

H325

must

ECS

clock

System

used.

Test

clocks.

4-1T+

clock

used

simulate

4.3.10

The

Initialization

initialization

transmitter
shown

For

each

that

are

logic

section

section,

the

used

separately

clear

the

receiver

simultaneously.

section

This

logic

and
1is

D14,

Logic

74123

clearing

negative-going

edge

one-shot

signals.

its

generates

Each

input.

complementary

one-shot

The

output

triggered

pulses

are

pulses

400

a
ns

duration.

The

microprocessor

simultaneously
inverted

by
7404

The

gates.

The

microprocessor
separately

Control

transmitter.

For

example,

The

microprocessor

assume

input

the

drives

R12

SEL

this

gate.

another

NOR

The

gate

from

can

clear

the

driving

that
drives

Ccntrol
I

low.

output

tco

and

transmitter

sections

CLEAR

This

sent

these

ALU

signal

AND

the

trigger

the

signal
each

trigger

section

low

and

the

Out

Control

ALU

gate

and

signal
gate

input

gates

desired

This

one

receiver

negated-input

addresses
D4

outputs

the

receiver

signal
and

for

the

inverter

low

section

one

clear

driving

NOR

can

the

one-shot

the

The

high

that

the
and

one-shots.

the

transmitter
the

receiver

for

section.

signal

goes

microprocessor

decoding
other

7402

the

This

goes

two

addressing

low.

(7402).

goes

4-]35

clear

logic

input

inverted

generates

of
by

ICLRP

4.3.11

Integral

4.3.11.1
each

Modem

General

contain

(M8202

Information

integral

corner

the

module

The

modem

for

the

DMC11-MA

6000

distance
L4

coaxial

The

cable

modem

of
or

18,000

feet.

the

bit

time.

SPACE

per

bit

time.

per

bit

time.

The

transmitter

The
be

receiver
150

The

modem

the

cutout

Each

DMC11-MD

circuitry

Line

Units

located

section.

operates

DMC11-MD

and

version
version

bps

operates

56K

requires

Belden

bps

8232

equivalent.

the

DMC11-MA

identified

The

version

The

non-return-to-zero

amplitude

above

feet.

incorporates

modem.

the

distance

Only)

diphase

(NRZ)

number

clock

peak-to-peak

frequency)

Transmitted

signal
is

identified

(logical

generated

from

minimum.

4-/36

identified

signal

recovered

transitions

transmitted

clock

(double

coding.

(logical

MARK

—

the

modulation
received

that
two
by

occur

with

data

during

transitions
one

a
~—’

transition

oscillator.

The

peak-to-peak.

received

signal

which

should

Functional Description - The functional description
discusses the modem operation at the block diagram level. Figure
4.3.11.2
4-31

is a simplified block diagram of the modem.

Section

Transmitter

(Figure

4-31)

A free running RC oscillator supplies the transmitter clocking

The oscillator is adjustable within a tolerance of +5%

signal.

and contains a temperature compensation network to prevent drift.
The oscillator frequency is twice that of the modem operating
frequency.

The oscillator output is divided by two which produces a clean
square wave

symmetrical

at the desired modem operating frequency.

This signal plus the oscillator output and data to be transmitted
are combined in the Clock Phase/Data Anding Network to generate the

This clocking signal

for the OUT flip-flop.

clocking signal

is a

string of positive pulses that occur once or twice per bit time
depending on whether

The OUT flip-flop

the

Therefore,

respectively.

complemented by

connected so that

clock pulses.

successive

data

its

output

executes

one

two state transitions during one bit time depending on whether the
data

The TTL output from the OUT flip-flop goes to a bipolar line driver

that generates an ac signal with zero crossover points that coincide
with

the

included
signal

input.

TTL

the

line

the

driver

crossover

56K bps

increase

points.

4-137
~v

version,

the

pulse

shapers

amplitude

are

the

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The

output

and

the

line

receiving

transformer

protects

1500

that

may

Data

the

TDS

driver

accidently

TDS

the

DATA

operating

frequency.

The

the

Phase/Data

Anding

Transmission
the

Delay

these

the

maintenance

times

after

maintenance
for

the

times,

After
1

RTS

set,

transmission

the

transmit

RTS
of

set

data

(print

the

logic.

output

Signal

flip-flop

signal

D16

D15

the

SEND

(print

RTS

the

modem

goes

L
H

D6).

flip-flop

signal

D16

transmit

D15)

Send
is

set,

modem

set.

goes

low

which

After

three

remains

RTS

and
the

1is

Seven

and

Until

flip-flop

D15

set

CS.

line

(RS)

sent

bit

the

enabling

signal

additional

bit

starts.

set,

the

flip-flop

goes

allow

the

Request

flip-flop

assert

flip-flop

this
to

logic

from

is clocked

asserts

the

RTS

Circuit

When

the

logic

until

satisfied,

Now,

voltages

cable.

control

DATA

The

Network.

been

select

transmitter

output

must

state.

the

transformer

cable.

comes

the

Send

hold

which

output

MARK

which

Clear

the

damage

flip-flop

initiated

have

protection

coaxial

transmitter

conditions

asserted.

against

cannot

and

the

picked

the

Clock

via

the

modem

flip-flop

station

the

transmitted

goes

the

modem

indicated

ENABLE
the

flip-flop

Bipolar

leave

the

state

changes

4-/33

Line

MARK

Driver.

hold

set.

the

state

OUT

The
ENABLE
and

flip-flop.

The

Glitch

Line
the

Preventer

Driver.
MARK

During

condition

transmission

Receiver
The

for

peak-to-peak.

and

this

several

its

output

circuit

goes

holds

milliseconds

the

Bipolar

modem

prevent

the

characters.

(Figure

data

power-up,

nonsense

Section

received

senses

4-32)
ac

enters

signal

the

that

modem

must

exceed

through

the

150

input

protection

transformer.

From

the

transformer,

the

signal

linear

phase

front

end.

which

eliminates

MHz

The

filter

Zero

Two

signals

are

Each

200

Zero

TTL

200

1-shot.

triggered

for

filter

noise

signals

from
to

with

for
the

the

form

and

low

provide

and

3.5

pulses.

single

output

1-shots

FET

KHz

input

edge
do

e’

signal.

the

two

string

2140

outputs

output

are

high.

the

one

the

nor

input

200

triggers

are

produces

strings

positive

detector

retrigger

pulse

Zero

These

that

connected

each

the

complementary

levels

from

not

form

inputs.

for

therefore,
These

provides

corresponding

Detector

The

connected

circuit

the

simultaneously;

are

positive-going

1-shot.

negative

inverted

This

compatible

Crossover

associated

frequency

comparators

inverse

approximately

bandpass

complementary

Detector.

the

low

Detector.

differential

are

provides

Crossover

that

goes

its’

they

string

are

ORed

and

pulses.

These

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It

trigger

produces

This

on-off

modem.

value

output

the

mux

receiver

signal
each

The

pulse

the

bit
Data

which

(56K,

values
in

750

logic

responds

produce

state

modem).

generate

the

receiver

string
occurs
to

of
at

the

1-shot

the

D10)

Clock

250
the

D15

are

data

goes

DATA

also

goes

clock

signal

D16

clock

pulses.
bit

logic

the

bps

component

plus
R

string

DATA)

which

time

Line

sent

Loop

Select

the

data.

the

CLOCK

The

time.

(print

Data

the

bit

received

each

ns.

Receiver

one

1-shot

(D16

the

and

250

obtained

the

signal
for

for

set.

1-shot

data

positive

start

receiver

goes

750

signal

750

time

This

the

bit

bps)

the

retriggerable.

separated

received

(sheet

the

500K

the

logic

are

not

circuitry.

TTL

that

modem

D16

Clock

which

and

the

sheet

1-shot

250K

control

goes

Clock

RECEIVE.

leading
Signal

D10)

ControI“/j

This

edge

D16

CLOCK

the

clock.

Timer.

the

1-shot

750

This

duration.

times

totals

out

output

Reset

pulses

comes

pulse

receiver

D15),

RECEIVE

750

the

bps

output

logic

shown

the

(sheet

The

train

pulses

represents

for

Clock

speeds

This

200

component

table

logic.

750

cycle

Other

changing

The

the

remains

(1.5

ns),

Clock

device

long

enabled.

the

1-shot

constantly

retriggerable

data,

and

there

times

Logic.

F-/42

1-shot

hence

the

clock

out

and

monitored
with

clock,

for

clears

one

the

1.5

the

present

and

one

Receiver

half

CHAPTER

MAINTENANCE

5.1

SCOPE

This

chapter

lists

required

description

maintenance

procedures.

5.2

the

MAINTENANCE

DMC11

line

corrective

maintenance

performed

aging

The

that
all

faults

the

5.3

the

detecting

intervals

module

caused

log

any

will

These

inspection

and

circuitry

detect

improper

complete

corrective

for

are

only

future

failure

preventive

and

programs,

and

procedures

are

any

deterioration

the

performed

isolate

has

log

reference

and

been

used

that

may

module.
and

determined

record

analysis;

maintenance

pattern

due

after

future

handling

maintenance

facilitate

component

action

and

aid

develop.

MAINTENANCE

ensure

downtime.

provides
and

diagnostic

procedures

The

maintenance

attempt

faulty.

maintenance

activities

PREVENTIVE

Preventive

preventive

damage

maintenance

and

preventive

consists

procedures,

maintenance

module

hopefully,

any

Unit

maintenance

The

regularly

corrective

repair

unit

log.

and

Line

equipment

PHILOSOPHY

Basically,

maintenance

test

consists

proper

tasks

equipment

consist

operational

checks.

performed

operation

running

and

periodic

minimum

diagnostics,

unscheduled

visual

The

preventive

and

operating

Under
of
4

normal

conditions

and

conditions

work

demand

The

loads

distinct

The

area

such

uses

standard

the

fault

5.4

TEST

and

standard

hand

tools,

The

corrective

maintenance

line

unit

determine

the

site.

maintenance

operation

relatively

and/or

basic

tool

exercise

consists
every

extreme

abnormally

used

the

receiver
and

the

heavy

technician

three

indicating

logic.
probe)

DMC11

printouts

technician

(scope

for

the

particular
The

logic

technician

further

isolate

component.

line

programs

cleaners,

unit

require

listed

test

cables,

the

Table
and

standard

5-1,

test

addition

probes.

MAINTENANCE

technician

that

installation

However,

dust,

environmental

REQUIRED

maintenance

module.

the

maintenance.

the
or

the

hours

provide

circuit

diagnostic

CORRECTIVE

and

point

specific

procedures

equipment

5.5

modes

preventive

humidity,

equipment

EQUIPMENT

Maintenance

first.

transmitter

test

600

diagnostics

printouts
the

every

comprise

The

maintenance

exist

frequent

programs

faults.

results.

temperature,

diagnostic

isolate

occurs

depends

recommended

cleaning

whichever

schedule

that

conditions,

inspection
months,

maintenance

Hence,
the

line

procedures

isolating

the

are

and

repairing

technician

unit

is,

designed

must

fact,

be
at

aid

faults

the

within

otherwise
fault.

the

equipped

Table

Test

Equipment

5-1

Equipment

Required

Manufacturer

Designation

Multimeter

Triplett

Oscilloscope

Tektronix

Type

X10

Tektronix

P6008

Probes

Module

(2)

Extenders

Simpson

Model

DEC

630-NA

260

453

W984

(Double)

W987

(Quad)
NOTE

For

Diagnostic

5.5.1
The

line

unit

can

Internal

System

External

modes

are

control

two

the

5.5.1.1
the

line

coaxial

and

board

and

use

gquad

DZDMF

three

modes.

They

are:

maintenance

test
maintenance

selected

The

source

integral

double

DZDME

operated

and

modem

Internal

two

signals

multiplexers

clocking

hex

Modes

microprocessor.

the

DEC

Maintenance

The

Tapes

in
to

signals

are
the

without

cable

(M8202).

(M8202

LOOP

maintenance

condition

only)

Maintenance

unit

that

the

for

This

disconnecting

come

from

and

logic

interface

the

RUN

(print
logic

(1)

D15)

(M8201

They
select
only)

servicing.

mode

from

checks

the

about

modem

90%

(M8201)

the

Signal

D15

SEND

transmitter

output

The

Request

The

clocking

single

5.5.1.2

mode

looped

and

source

System

maintenance

Send

stepped

asserted

the

keep

around

Data

STEP

from

become

Ready

the

active.

receiver

signals

are

input.

held

microprocessor.

The

OFF.

program.

This

mode

except

that

the

clock

External

checking

associated

For

the

H325

the

set

similar

source

the

internal

KHz

internal

line

unit

Mode

including

line

unit,

connected

the

12-12528

coaxial

adapter

coaxial

cables

together.

Clocking
clock

for

which

modem

Clocking

This

level

the
is

M8201

turned

transmit

for

the

and

M8202

the

well

must

BC05C-25

and

logic

unit,

modem

M8202

receiver

line

the

pig-tail

mode

provides

conversion

complete

logic

and

cables.

M8201

must

Maintenance

For

the

transmitter

clock.

5.5.1.3

and

Terminal

diagnostic

Test

the

coaxial

This

unit

around

the

receive

cable

(Figure

must

used

tests

integral

line

disconnected

cables

must

the

5-1).

disconnected

connect

the

all

the

transmitter

modem

and

pig-tail

supplied
H325

and

test

the

cables.

KHz

internal

simulate

connector

clocks.

supplied

the

integral

modem

clock.

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MODEM CONN

modem end of BCOS coble.

PlNS

Figure

5-1

11- 3384

Schematic

H325

Test

Connector

Also,
the

for

the

proper

turned

M8201,

level

around

Data

-5.5.2
Two

the

H325

data

Send

Terminal

control

and

test

cable

returned

paths

‘connector

returned

Ready

signals

returned

The

ensure

signals

are

follows.

received

tested

exist.

Clear

are

Ring

data.

Send.

and

Data

Set

Ready.

Diagnostics

diagnostic

unit.

They

which

tests

Detailed

tapes

are

DZDME

under

Bit

discussions

diagnostic
are

modem

conversion

Transmitted

Request

the

shipped

tape
with

are

used

verify

proper

which

tests

under

DDCMP

Stuff

protocol

control.

content,

use

the

documented

the

line

separately.

unit.

and

operation

control

and

documents

line

DZDMF

interpretation

The

the

and

each

tapes

dlifgliltiall
digital equipment corporation

Printed

U.S.A.