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Document:	DHQ11 User Guide
Order Number:	EK-DHQ11-UG
Revision:	002
Pages:	114
Original Filename:

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EK-DHQ11-UG.002

DHQ1 1

User Guide

Prepared by Educational Services

of
Digital Equipment Corporation

Second Edition, July 1987
Copyright © 1987 by Digital Equipment Corporation

Printed in U.S.A.

The information in this document is subject to change without
no
assumes
notice.
Digital
Equipment
Corporation
responsibility for any errors herein.

The

following

are

trademarks

Digital

Equipment

Corporation:

dliolilt]al
)

DEC
DECmate

MASSBUS
PDP

DECSYSTEM-20
DECUS
DECwriter
DIBOL

Professional
Rainbow
RSTS
RSX

DECsystem-10

FALCON

P/OS

RT-11
UNIBUS
VAX
VAXBI
VMS
VT
Work Processor

CONTENTS

PREFACE

DWW
-

[

NGV
N I )

LR WL
———

Lbbbsrbbbhbbbbbbbbbbbbbbbbbbb
H U
—
LI W LN
RN

CHAPTER 1

CHAPTER 2
2.1

2.2
2.3
2.3.1
232
2.3.3
234
24
24.1

INTRODUCTION

e
et
e e e
SCOPE ..ottt
e et ettt teae e eanaaaeaennns
OVERVIEW
ee
e
General Description .......cooiruiiiiiiiiiiiiiiiiiiii
Modem Control Facility ........ccvviiiiiiiiiiiiiiiiiiiiinann
Self-Test Facllity .....coviiiiiiiiiiiiii i
Diagnostic Programs ............c.ooiiiiiiiiiiiiiiiiiiian.
i,
Preventing Data Loss .......ooviiiiiiiiniii
e
i
Physical Description .........oiiuiuriiieiiiieniiiiiei
On-Board Switchpacks ........cccviiiiiiiiiiiiiiiiiiiiannn
Communications Standard ..o
e
Versions Of The DHQI11 ...
Configurations ......c.ceieeininieiiinneenieeaneaeeaneeceaneinnoenns

Lo Yo SN
(@70 1701715
SPECIFICATIONS ........ et
Environmental Conditions .........cceeeiiiimriiiiieeenaaeeencnanens
Electrical ReqUIrements ..........ccesiviiueennreneeeceaaneeonannnn.
e
Q-bus Loads ......coviiiieiiiiiiii
PP
N
4 1o <I
20 5{079117:%
aanns
eeessninnaaaaa
naaeeeeeeeetee
Data Rates . ..utitiiiiiera
t
itt
iiiiiiiii
Throughput ......ccoiiiiii
nanenans
tt
ittt ianiinananeaa
SERIAL INTERFACES ...t
i
iiiiiiiiii
........cciii
Standards
Interface
) IR1 0T S =3 A 7= - P
Line Transmutters . ...veiveeeeeenneeeonereonsunneaneasoaaeeneecnoens
Speed And Distance Considerations ..............ooemiiienianannn.
iiiiiieieniaiaceneens
FUNCTIONAL DESCRIPTION ... .ottt
(€ =3¢ 1= v 1 A
Main FUNCHONS . .vvvvttiiiirenneneeeecneneannnnnsnsanecaanencscenns
eaaanes
tt
e
Control ChiP ..ot
R
V¥ 23 NN61| T
(0104

1-1
1-1
1-1
1-2
1-2
1-2
1-2
1-2
1-3
1-3
1-4
1-5

1-7
1-8
1-8
1-9
1-9
1-9
1-9
1-9
1-10
1-10
1-11
1-11
1-11
1-13
1-13
1-13
1-13
1-14

INSTALLATION

3 /G
Y L0
it iiiiiiiei e
UNPACKING AND INSPECTION ...
PREPARING THE DHQI11 MODULE ...t
Address And Vector Assignment ..........ccoiiiieieiiiiiiiiiiinnnns
Setting The Address Switches .......... ..o,
Setting The Vector Switches ..........coviiieiiiniiiiiiaina.,
DHV11 Or DHUI11 Programming Mode Selection ..................
BUS CONTINUITY ottt ieeteeettsesasineeananninansenaases
Bus Grant Continuity JUmMPers ..........cceeviiiiennenneeieeannennns

2-1
2-1
2-3
2-3
2-3
2-5
2-6
2-6
2-7

1 NRNRNNNRDNDNNN
NSNS
hinhhin

N =

PRIORITY SELECTION ... ittt
eiiieee
e,
DMA Request Priority .........oiuniiiiiiiii
it iiiiineennnnn.
Interrupt Request Priority ......... B ettt
e
RecomMmendations .........ciiiiriieriiiiintitnnrenneeenaacennnnnn
INSTALLING THE DHQII1 ...t
e eieeane
Installing The M3107 Module ........ ... .. iiiiiiiiiiiiiiinan.
Distribution Panels ........ ..o
i
e i e
Installing The EIA-232-D Distribution Panels .......................
Installing The DEC423 Distribution Panels .........................
INSTALLATION TESTING ...t
it et ireiiaeeeeaenann.
Installation Tests On MicroPDP-11 Systems .........................
Testing In MicroVAX II Systems .....c.oiiiiiiiiiiiiinennennnnn..
H3101 LOOPBACK CONNECTOR ......ciiiiiiiiiiiiiiiiiiieaeennn,
CABLES AND CONNECTORS — EIA-232-D ...... ...,
Distribution Panel ............
i
i i i
Null Modem Cables ...t
et
Full Modem Cables ........ ... ittt
CABLES AND CONNECTORS — DEC423 ........ ..ot

2-8
2-8
2-8
2-8
2-8
2-8
2-11
2-11
2-11
2-12
2-12
2-13
2-13
2-15
2-15
2-18
2-19
2-20

o ovon

W N

NooooauLbhLLLWID-

W W WL LWL WWWWLWWWWL

bbbbbbbhwhbbbhwwwbbbbi

SIS

PROGRAMMING

L1
3
A
REGISTERS ...
et iieeeannse e
Register ACCESS ....oiitiriiiiiiiiiiieiiieinerannannn e
Register Bit Definitions ...............coiiiiii... e,
Control And Status Register (CSR) ...,
Receive Buffer (RBUF) ...t eiiieieee
Transmit Character Register (TXCHAR) .......................
Receive Timer Register (RXTIMER), DHU11 Mode Only ......
Line-Parameter Register (LPR) .......coiiiiiiiiiiiaiiiait.
Line-Status Register (STAT) ...ttt
FIFO Size Register (FIFOSIZE), DHU11 Mode Only ..........
FIFO Data Register (FIFODATA), DHU11 Mode Only ........
Line-Control Register (LNCTRL) ...............coiiaiiiiit.
Transmit Buffer Address Register Number 1 (TBUFFADI1) .....
Transmit Buffer Address Register Number 2 (TBUFFAD?2) .....
Transmit DMA Buffer Counter (TBUFFCT) ...................
PROGRAMMING FEATURES ...
i
Initialization .. ... .. i i
i i i
e
e
L0003 ¢V 12100 o1 1o ) ¢ KRN Y
6200135
¢ 064
DMA Transfers . ..cuiieiiiiieiinnnianeeeaereassoostoannanas
Programmed I/O (DHV1I1 Mode) .........coiiiiiiiiiiia..
Programmed I/O (DHUI1 Mode) .........coiiiiiiiiiiiiii.
3o VInterrupt Control . ......ii.iiii
i ittt ettt
Auto XON And XOFF ...ttt
iee et e i e eeieeaanas
JAUT
O .ot
ettt
it et tetanaaaaaaaanenanenan
FORCE.XOFF ......... P
OAUT
O .ot
i ittt
i teetaaeaaaeeanaanaanaeens
DISAB.XRPT ... it feeeeeeiieaan
Error Indication ....... ...ttt
ittt
ie ittt

3-1
3-1
3-1
3-3
3-3
3-6
3-8
3-8
3-9
3-12
3-14
3-14
3-15
3-19
3-19
3-20
3-22
3-22
3-23
3-23
3-23
3-24
3-24
3-24
3-25
3-25
3-26
3-26
3-26
3-27
3-27

i bt \O OO

TM
o

QOO OO

bk ek ek

o PLLbLLwLLW

3-27
3-28
3-28
3-28
3-28
3-29
3-30
3-31
3-31

TranSIMIttiNE . ..ovouereetnnenneneneantaaaeannsseeanaaeueancanaiones
Single-Character Programmed Transfer (DHU11 Mode) ........
Single-Character Programmed Transfer (DHV11 Mode) .........
el . .oiiiiiiiiiieenaeesieeeeensasenneanasennnnns
DMA Trans
Aborting A TranSmiSSiON ........ceeeeeeeeinrnroaneanacenenens
ass
e onns
RECEIVIIIE .« e eveeteeenevninniiaeanaaanennennneinannasac
iiiiieiiia et
Auto XON And XOFF ..

3-33
3-33
3-34
3-35
3-36
3-37
3-39

ae
ettt atanees
e tanerenet
CONAZUIAION . .euuvuttateteen

W W

enenans
eeie
eraaanae
itie
it nnnanane
Modem CONtrol ...cvitvirrr
enns
naneanane
necinnian
..oeeeeeu
Maintenance Programming .........
iia
s
iiiiii
iiiiii
iiiiia
Diagnostic Codes ........ouii
Self-Test Diagnostic Codes .......oeviiieiniiiiiiiaiiiaen..
Interpretation Of Self-Test Codes ...........oiiiiiiiincenennn.
ii
e
Skipping Self-Test ........coieniiiiiiiiiiiiiiiii
oeennnn.
.......o
........
(BMP)
Program
Background Monitor
PROGRAMMING EXAMPLES ............c.cotnn errreeaearaeaaaes
Resetting The DHQI1 ... oo

343
3.4.3.1
3.4.3.2
3.4.3.3
3.4.34
344
3.4.5
3.4.6

4
CHAPTER

aian
Checking Diagnostic Codes ........coeiniiiininiimniiiie,

3-32

3-41

TROUBLESHOOTING

R
23 A
Y000
e
t
t
t
PREVENTIVE MAINTENANCE ... i
t
.
.
TROUBLESHOOTING PROCEDURES .
INTERNAL DIAGNOSTICS .......coiiiiiiiinnnn. e
R R RR
T L U AR

4-1
4-1
4-1
4-2
4-2

4-3
4-3
4-3
4-3

4.6.1
4.7

eees
iteiii
MicroPDP-11 DIAGNOSTICS ... iiiiiiiiiiiiiiie
aeanens
enaeeae
rnninri
nerneen
uieeeen
......o
User-Mode DiagnostiCs
Running User-Mode Tests ........ooiviiiiiiiiiniiiieninientnns
eeenes
t
ra e
MicroVAX II DIAGNOSTICS ..tt
ncanns
nnaseco
sassana
saeneoe
eesoona
reeeeaa
vvvinei
..o
USer-MoOde TeStS
nn
iiiinn
iiiiii
iiiiii
...cii
(FRUS)
UNITS
LE
FIELD-REPLACEAB

APPENDIX A

MODEM CONTROL

A.l
A2
A.2.1

:J S
1 00)
MODEM CONTROL .. iiiiiiiiieiiiiaiananeeaenseeansananoanaennes
Example Of Auto-Answer Modem Control For The PSTN ..........

APPENDIX B

FLOATING ADDRESSES

B.1
B.2

FLOATING DEVICE ADDRESSES ... . i
FLOATING VECTORS .. iiiiiiiiiiiiiiiiannaaeteantiaranacseenncanenns

APPENDIX C

AUTOMATIC FLOW CONTROL

4.1
4.2
4.3

4.4
44.1
4.4.2
4.5
4.5.1

o —

oTeTelels
W W W N =

4.5.1.1
4.6

Background Monitor Program (BMP) .............ciiiininiinnenn.
i

R R
21,2
1927 21 2172 0
tt
ot
CONTROL OF TRANSMITTED DATA ..
CONTROL OF RECEIVED DATA ..ottt
Flow Control By The Level Of The Receive FIFO ..................

Flow Control By Program Initiation ............ccoieieeiniinnnnenns

4-3

4-4
4-5

A-1
A-1
A-2

B-1
B-3

C-1
C-1
C-2
C-2

C+4

C.3.3

Mixing The Two Types Of Received-Data Flow Control .............

APPENDIX D

GLOSSARY OF TERMS

D.1
D.2

SCOPE ...
GLOSSARY o

APPENDIX E

DHQ11 Q-BUS CONNECTIONS

C-5

D-1
D-1

FIGURES
Figure No.

Title

1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3

Layout of the DHQII Module ............oooieure
Example of a DHQI11 Configuration .............ooouireininrninneni
DHQI11 Connections (EIA-232-D) .......ovuuuriin
DHQI1 Connections (DEC423) .....oovniinmn
DHQI1 Functional Block Diagram .............coouuuimiionsoinen
Location of Switchpacks ............ ... oo
Setting the Device AdAress .............oooviininiuemnei
Setting the Vector Address ...............oooiiiiinii

2-4
2-5

2-6
2-7
2-8
2-9
2-10
2-11
3-1
4-1
C-1
C-2
C-3

Page

Bus Grant Continuity ................ouuiineinenee

Installing the DHQII (EIA-232-D)

....vuiinninea

e
e

Installing the DHQI1 (DEC423) ....ouvnineeieie
I/O Insert Panels and Adapter Plate (EIA-232-D) ............ouvvunoin...
I/O Insert Panel (DEC423) .....oovuuin
e e
iteee
H3101 Loopback Connector ..............covuuemoeiunnni
H3173-A Circuit Diagram ............ooouiienennnnei
Null Modem Cable Connections ............c.ovueueernuesan
i,
Register Coding .........ooo
i iiiiiiii
Troubleshooting DEC423 Installations ................ovveenenennnn... e
Transmitted Data Flow Control ...............coouiiiiinunn
.
Receive FIFO-Level Flow Control .........c.vueeerereinini.
Program-Initiated Flow Control ................ooouuiniin.

1-4
1-6
1-7
1-8
1-15
2-4

2-5
2-6

2-7
2-10
2-10

2-11
2-12
2-14
2-16
2-19
3-3
422
C-2
C-3
C-4

TABLES
Table No.

Title

1-1

EIA/CCITT Signal Relationships ............coooouneerninninn
i,
Maximum Distance Guidelines for DHQI11 ...............coiiueni.
..
DHQI1 Options ......couiuuiiiiiii ittt
H3173-A Connections .............o.vuuinenienaee
i
Serial-Line Connections for the 36-Pin Connector ........................

1-2

2-1
2-2
2-3
3-1
3-2
3-3
34
A-1
B-1
B-2
E-1

DHQI1 Registers in DHVII Mode .........ooovurniniinei
.
DHQI1 Registers in DHUII Mode ........oovoiniiinni,
Data Rates . ...t
DHQI11 Self-Test Error Codes ..........oouvinieiiieiniinaini,

Modem Control Leads ...........co.ounnuieiin
Floating Device Address Assignments ................ooeeuiinonunonnnn.
Floating Vector Address Assignments ...................o...... e,
DHQI11 Q-Bus Connections .............eueurueenemnen
e

Page
1-10
1-12

2-2
2-17
2-20
3-2
3-2
3-11
3-28
A-1
B-1
B-3
E-1

PREFACE
The DHQ11 User Guide provides reference information on physical layout, system configuration,
installation and testing, programming characteristics, and maintenance. There is a glossary of technical
terms generally used in DIGITAL technical manuals. The manual is divided into four chapters as
follows:

CHAPTER 1 INTRODUCTION. This chapter gives a physical description of the DHQI11, explains
how it can be configured, and explains how it interfaces with the system bus and serial data lines.
CHAPTER 2 INSTALLATION. Chapter 2 describes how to install a DHQI11 option, with detailed
information on device and vector address selection, backplane positioning, cables and connectors, and
testing after installation.
CHAPTER 3 PROGRAMMING. This chapter describes the DHQI11 registers. Some programming
examples are also included.

CHAPTER 4 TROUBLESHOOTING. Chapter 4 explains maintenance strategy, and how to use
diagnostic programs to locate a faulty module.
APPENDICES. These include additional information on topics discussed in this manual:
APPENDIX A

—

MODEM CONTROL

APPENDIX B
APPENDIX C
APPENDIX D
APPENDIX E

—
—
—
—

FLOATING ADDRESSES
AUTOMATIC FLOW CONTROL
GLOSSARY OF TERMS
DHQI1 BUS CONNECTIONS

This revision of the manual contains new information. The DHQ11 can operate in two different modes,
making it compatible with software drivers written for either the DHV11 or the DHU11. Revision -001
of this manual contained information on DHV11 mode of operation only.

vii

CHAPTER 1
INTRODUCTION
1.1

SCOPE

This chapter gives an overview of the DHQ11 asynchronous multiplexer, describes the features that it
offers, and defines its physical parameters and electrical requirements.
1.2

OVERVIEW

1.2.1

General Description

The DHQI1 option is a serial-line interface which provides eight full-duplex serial data channels on
Q-bus systems. The DHQ11 option consists of a single Q-bus module, and one of two groups of cabinet
kits, depending on the communication standard supported. The cabinet kits contain the cabinet
bulkhead panels and connecting cables.

The main application of the DHQI1 is for interactive terminal handling; it can also be used for data

concentration and real-time processing. It has two programming modes, DHV11 and DHUL11. The
register sets in these modes are compatible with those of the DHV11 and DHU11 respectively. The
preferred mode of operation is DHU11 mode. The main features of the DHQI11 are:
®

Eight full-duplex asynchronous data channels

For transmission: DMA transfers; or for each line, program transfers to a 1l-character
transmit buffer in DHV11 mode, or to a 64-character transmit FIFO in DHU11 mode

®
e

For receive: a 256-entry FIFO buffer for received characters, dataset status changes, and

diagnostic information

It supports EIA-232-D/V.28 or DEC423, with the appropriate cabinet kit.
NOTE

DEC423 is a term used in this manual to indicate a
data-leads-only implementation of the RS-423-A
electrical standard. DEC423 uses MMJ connectors
instead of the 37-way connectors specified by RS-449.

It is compatible with all DIGITAL DHV11 and DHU11 device drivers

It can auto-answer on a switched line

The transmit and receive baud rates for each line can be individually programmed

It has a total module throughput of 60,000 characters per second, using 8-bit characters, with
all channels operating at 38.4 kbaud for both character reception and transmission

1-1

The DHQI! supports 16-, 18-, or 22-bit addressing, including block-mode data transfer

suitable memories

The DHQI1 can be programmed to filter XON/XOFF

Self-test and background monitor testing

Dual-height module, M3107

with

characters from the received data flow

Switchpacks for selecting the Q-bus base address, vector address and DHV11 or
DHUI11

programming mode.

All other functions are selected by program.
1.2.1.1

Modem Control Facility — All eight channels have sufficient modem control
to

auto-answer dial-up operation over the public switched telephone network using

allow

suitable modems, such

as DIGITAL’s DF124, or Bell models 103, 113, 212. Equivalent modems from other manufacture
rs can
also be used. The DHQI11 is designed to minimize software requirements for modem
link control.
Appendix A gives further information on modem control. Modem control can be
used for driving
modems over both public and private lines. Please note that, in some countries, modems
must be
approved by the PTT for that country for connection to the public network.
1.2.1.2 Self-Test Facility — The
DHQI1
incorporates
self-test
sequencers
which
operate
independently of the host. The result of the self-test is provided to the host system through the
receive
FIFO buffer. A green LED indicates GO/NO-GO status for the device. More details are given in
Section
4.3.
1.2.1.3 Diagnostic Programs — A full range of diagnostic programs is available. These run under
the
MicroPDP-11 diagnostic supervisor or MicroVAX II maintenance system. Loopback test connectors

are not needed when running the user-mode diagnostics. Service-mode diagnostics and
loopback

connectors are available from DIGITAL.

1.2.14 Preventing Data Loss — The DHQI1 can be programmed for automatic XON and
XOFF
operation, to prevent the loss of data at high throughput. The reporting of received XON/XOFF
characters to the software driver can be enabled or disabled.
1.2.2 Physical Description
The DHQI11 is an M3107 dual-height Q-bus module. It is 21.6 cm (8.51 inches) long and 13.2 cm (5.19
inches) wide. Figure 1-1 shows the layout. Connectors A and B are for the Q-bus, while connectors
J1
and J2 interface to the communications lines via BCO5L-xx cables and distribution panels. Two
distribution panels are supplied with an EIA-232-D option, and a single panel is supplied with a
DEC423 option. Connector J3 provides power to the active distribution panel supplied with DEC423
options. This connector is not used with EIA-232-D options. Mixed use, that is, one EIA-232-D and one
DECA423 panel connected to a single module, is not supported by DIGITAL.

1-2

1.2.2.1

On-Board Switchpacks — The DHQI1 has two on-board switchpacks to select the following
,

functions.
®

Switchpack E-19 (10-position)

Switch 1 selects DHV11 programming mode when closed, or DHU11 programming mode

when open.

Switches 2 to 10 select the device address.
®

Switchpack E-11 (8-position)

Switch 1 enables the on-board oscillator. This is a manufacturing test switch, and is closed for

normal operation.

Switch 2 selects manufacturing self-test mode. This is a manufacturing test switch, and is open
for normal operation.

Switches 3 to 8 select the device vector address.

Chapter 2 gives further information about these switchpacks.

1.2.2.2 Communications Standard — The serial drivers on the M3107 module are compatible with
EIA-232-D. However, the CK-DHQ!11-W cabinet kits provide level conversion for DEC423.

1-3

AN\

cTo

J2 CONNECTOR

\] POWER

CONNECTOR

CHANNELS 4 - 7
m

(

J1 CONNECTOR

{

FUSE

CHANNELS O - 3

OCTART

CONTROL
CHIP
ADDRESS

VECTOR

10 POSITION

8 POSITION

SWITCHPACK

—]

RE3200

Figure 1-1

Layout of the DHQ11 Module

1.2.3 Versions Of The DHQ11
The DHQI11-M option consists of the M3107 Q-bus module and the User Guide. It can be used with one
of six cabinet kits. The choice of kit depends on the type of system cabinet, and on whether a EIA-232-D
or a DEC423 communication interface is needed.
The cabinet kits available for use with the DHQ11-M are:

1-4

EIA-232-D
®

CK-DHQI11-AA for BA123/BA11-M boxes

CK-DHQI11-AB for BA23 boxes

CK-DHQ11-AF for H9642 cabinets

DEC423

CK-DHQI11-WA for BA123/BA11-M boxes

CK-DHQI11-WB for BA23 boxes

CK-DHQI11-WF for H9642 cabinets

1.2.4
Configurations
The DHQI11 can be used in many different system configurations. Figure 1-2 shows a typical EIA-232-D
application.

1-5

DEVICE

HOST

PROCESSOR

{

Q-BUS

LOCAL

EQUIPMENT
DHQ11

LOCAL

fHIIIIA

TERMINAL:

EIGHT
DATA

{

‘

CHANNELS

MODEM

TELEPHONE
OR DATA COMMS
LINES

ANY

fe——

ASYNCHRONOUS
DEVICE

y
REMOTE

EQUIPMENT

TERMINAL

EIGHT
DATA CHANNELS

[

! 1 I I t I i :

remore

TERMINAL

REMOTE
DHQ11 OR
DHV11

Q-BUS

REMOTE

PROCESSOR
RE1703

Figure 1-2

Example of a DHQI11 Configuration

1.2.5 Connections
The DHQ11 module is connected directly to the Q-bus by connectors A and B. Figures 1-3 and 1-4 show
the interconnections for EIA-232-D and DEC423.
40-PIN BERG
CONNECTORS

H3173-A
DISTRIBUTION PANELS

BACKPLANE (Q22/LSI11 BUS)

CHANNELS
0TO3

25 PIN D-TYPE
CONNECTORS

BCOSL-XX

CABLE

| CHANNELS
4707

NOTE:

BCO5L-01 = 30 cm (12 INCHES)
BCO5L-1K = 53 cm (21 INCHES)
BCO5L-03 = 92 cm (36 INCHES)
RE3

Figure 1-3

DHQI11 Connections (EIA-232-D)

1-7

BCOSL-XX
40-PIN BERG

CONNECTORS

H3100 ACTIVE
/

BULKHEAD PANEL

H3104 CABLE

BACKPLANE

CONCENTRATOR

(Q22/LSI BUS)

CONNECTOR

COLOURED STRIP

S5S

POWER CABLE
70-22775-XX

BC16C-25

NOTE:

BCO5L-01=30cm (12 INCHES)
BCO5L-1K=53cm (21 INCHES)
BCO5L-03=92cm (36 INCHES)
RE3201

Figure 1-4
1.3

DHQI11 Connections (DEC423)

SPECIFICATIONS

1.3.1

Environmental Conditions

The following environmental constraints for storage and operation apply to the DHQI1.
®

The storage temperature must be within the range —40 degrees C to 66 degrees C (—40 degrees
F to 151 degrees F).

The operating temperature must be within the range 5 degrees C to 60 degrees C (41 degrees F
to 140 degrees F).

When operating, the relative humidity must be within the range 10 percent to 95 percent,
non-condensing, at 2 maximum wet-bulb temperature of 32 degrees C and a minimum dew
point of 2 degrees C.

DIGITAL normally defines the operating temperature range for a system as 5 degrees C to 50 degrees C
(41 degrees F to 122 degrees F); the 10 degrees C difference between the upper limits quoted allows for
the temperature gradient within the system box.

1-8

The maximum operating temperatures must be derated by 1.8 degrees C/1000 m above sea level (1
degree F/1000 ft) for operation at high-altitude sites.
1.3.2 Electrical Requirements
The DHQI11 needs the following electrical supplies.

For EIA-232-D options: 5 volts dc plus or minus 5 percent at 1.7 A maximum current, 1.4 A
typical

For DEC423 options: 5 volts dc plus or minus 5 percent at 2.2 A maximum current, 1.9 A
typical

For EIA-232-D and DEC423 options: 12 volts dc plus or minus 5 percent at 300 mA
maximum, 230 mA typical

An on-board switched-mode power supply generates a —10 V supply for the serial-line drivers.
1.3.2.1

Q-bus Loads — The loads applied to the Q-bus are:

3.2 ac loads

0.5 dc loads

1.3.3

Performance

1.3.3.1

Data Rates — Each channel can be separately programmed to operate at one of 16 speeds (in

bits/s):

50
75
110
134.5

1800
2000
2400
4300

150
300
600
1200

7200
9600
19200
38400

NOTE

See

also

Section

1.4.4

(Speed

and

Distance

Considerations).

Chapter 3 contains further information on data rates for EIA-232-D.

1.3.3.2 Throughput — Each channel is capable of full-duplex operation at the maximum data rate. The

following maximum throughput is obtainable:

®
®

At 7 bits per character, with 1 start bit, 1 stop bit, and 1 parity bit, the throughput 1s 61440
characters per second.

At 5 bits per character, with 1 start bit, 1 stop bit, and no parity, the throughput is 87771

characters per second.

This throughput may be limited by your driver software.
1.4

SERIAL INTERFACES

1.4.1
Interface Standards
The DHQI11 provides modem control signals which conform to EIA/CCITT standard EIA-232-D/V.24.
The electrical characteristics of the data signal lines conform either to EIA-232-D/V.24 or to
RS-423-A/V.28, depending on which cabinet kit is fitted. The interface. is compatible with X.26/V.10
standards. The slew-rate requirements for RS-423-A/V.28 are different from the slew-rate requirements
for X.26/V.10.

Connections to external equipment are made via 25-pin male subminiature D-type connectors, as
specified for EIA-232-D, or 6-pin MMJ connectors for DEC423.
NOTE

The H3173-A distribution panel does not support
separate transmit and receive grounds.

Table 1-1 shows how the signals in EIA-232-D, V.24, and RS-449 are related, and lists the pin
connections for male subminiature D-type connectors.
Table 1-1

EIA/CCITT Signal Relationships

Signal Name

D-type

EIA-232-D

Circuit

CCITT

Circuit

RS-449

V.24

Signal Ground

(SIG
GND)

RS-423-A Receive Common

102

102B

103

104

Transmitted Data

(TXD)

Received Data

(RXD)

Request To Send

(RTS)

105

Clear To Send

(CTS)

106

Data Set Ready

(DSR)

107

Data Terminal Ready

(DTR)

108/2

Data Carrier Detect

(DCD)

109

Ring Indicator

(RI)

125

’

Not Connected

1-10

1.4.2 Line Receivers
The DHQI11 uses octal serial-line receivers which convert line input signals to TTL levels for the
OCTART. Signals are inverted by the receivers.
1.4.3
Line Transmitters
The DHQI11 uses EIA transmitters which convert TTL level signals from the OCTART and modem
latches to line levels on the data and modem lines.

1.4.4 Speed And Distance Considerations
As of December 1985, the Electronics Industries Association (EIA) have replaced the “RS-" identifier
for RS-232-C with “EIA”. Therefore RS-232-C has been replaced by EIA-232-D. These two standards

are compatible with each other. This manual uses EIA-232-D.

The RS-232-C/CCITT V.28 standard was originally designed to specify the connection between a local
interface and a modem. It was not intended to be used for connecting to terminals over long distances.
The maximum specified cable length is 50 feet (15 metres). Shielded cable must be used in order to meet
the requirements of FCC and VDE Radio Frequency Interference (RFI) regulations.
Although cable lengths greater than 50 feet can be used with reasonable success, cable capacitance, noise
and ground potential difference restrict the line speed as the distances increase. Consequently, the
performance of long-distance communications to a terminal using EIA-232-D often does not meet
today’s requirements for terminal wiring.
DECA423 is a data-leads-only implementation of the RS-423-A/CCITT V.10 standard. RS-423-A has a
different grounding and signal return path arrangement from EIA-232-D.

DEC423 uses line driver and receiver chips which have better filtering and tighter level tolerances than
those $pecified by RS-423-A. In addition, DEC423 devices include transient suppressors for electrical
overstress (EOS) and electrostatic discharge (ESD) protection. DEC423 devices may also be connected
with unshielded cable.

The features provided by DEC423 devices are reliable data communication over increased distances,
typically 1000 feet (300 metres) at 9600 baud. See Table 1-2 for maximum-distance guidelines.

Table 1-2

Maximum Distance Guidelines for DHQ11

Up to
4.8 Kb
DEC423 to DEC423

DEC423 to EIA-232-D

9.6 Kb

19.2 Kb

38.4 Kb

300 m

1000 ft
300 m

500 ft
150 m

250 ft
75 m

200 ft
60 m

1000 ft

The DEC423 standard is for data-leads-only connections to terminal equipment, and is not suitable for
connection to modems or other Wide Area Network equipment. The standard also specifies the use of a
6-pin Modified Modular Jack (MMJ) connector, instead of the much larger 37-pin D-type connector
used with RS-423-A.

DEC423 is signal-compatible with the EIA-232-D standard when used for data-leads-only
interconnection, in that interconnection between devices using the different standards is possible.
However, the restrictions on the speed and distance of EIA-232-D will still apply.
DEC423 should always be used in preference to EIA-232-D for direct terminal connection over
extended distances.
NOTE
An H3105 active terminal adapter is necessary when
using an EIA-232-D terminal with a DEC 423
interface if the longer cable lengths obtainable with

DEC423 are required.

The recommended cable for DEC423 is BC16E-XX, which is available with 6-pin MMJ plugs at each
end, in lengths up to 100 feet. This cable is also available without MMJ connectors in 1000-foot reels,
DIGITAL part number H8220. Unshielded four-twisted-pair cable can also be used. This is available in
1000-foot reels, DIGITAL part number H8245-A.

NOTE
DEC423 to EIA-232-D. is intended for local
communication. In general, communication devices
can become non-operational or be damaged if the

total cable length exceeds 300 metres (1000 feet) for

DEC423 devices. The cable should not be run outside
the building, and the low-voltage data wiring must be
separated from ac power. wiring. The installation or
sites may require additional devices to correct
problems in communication.

NOTE
Under ideal conditions, DEC423 devices can drive
cables considerably longer than the 1000-foot
maximum stated above. However, differences in

1-12

ground potential, pick-up from mains ac power
cabling, and risk of induced interference limit the
maximum distance for reliable communications in
most practical situations.

1.5

FUNCTIONAL DESCRIPTION

1.5.1
General
The DHQ11 functional blocks are shown in Figure 1-5. Most of the functions are provided by two chips:
the control chip and the OCTART chip.

Q-bus buffering uses six DC021 bidirectional buffers. Serial-line interface buffering uses five octal line
receivers (5180) and three octal line transmitters (5170), used for data and modem signals.
A 2k x 8 static RAM chip (2018D-45) provides the memory requirements. Switchpacks provide vector
address and module address selection.
1.5.2 Main Functions
The main functions of the DHQI11 are:

Transmission — Single characters (DHV11 mode) or multiple characters (DHU11 mode) can
be transmitted using programmed transfers. Characters can also be transferred by DMA.

Reception — Received characters are deserialized by the OCTART and transferred to a
four-character area in the RAM (one such area per line) by the control chip’s OCTART
sequencer, following an interrupt from the OCTART. The control chip’s OCTART sequencer
later removes characters from the bottom of the 4-character FIFO, and places them in the 256
x 16 receive FIFO, which can be read by the host.

Modem Control — The modem control latches are external to the control chip. Data i1s
written to the latches from RAM by the OCTART interface sequencer. The sequencer also
samples modem status lines every 10 milliseconds and reports on changes via the STAT
register (and also via the receive FIFO, if programmed to do so).
1.5.3

Control Chip

The control chip contains the following functional blocks.

Q-bus Interface — Matches addresses, generates vector addresses, and handles interrupts. It
also interfaces the Q-bus signals to other functional blocks

Data I/O Sequencer — Controls host access to device registers

OCTART Sequencers — Transfers data between the OCTART and RAM, and handles flow
control

Self-Test/Power-Up Sequencer — This section powers-up the module to a fixed set of initial

conditions, such as 9600 baud rate on all lines; it also handles self-test

DMA Sequencer — Initiates and manages all DMA data transfers to the module
RAM Arbitrator — Provides RAM and OCTART bus access to the various sequencers.

1-13

1.5.4 OCTART Chip
This chip contains eight UARTSs, which perform parallel-to-serial and serial-to-parallel data
conversions. It interfaces with the control chip through eight registers. Four are read-only and four are
write-only. An index register is used to access individual lines. The OCTART chip shares the RAM bus
with the control chip, and the RAM itself. The OCTART chip also includes:
®

Receive and transmit control blocks

Interrupt -logic for interfacing with the control chip

A 16-output baud-rate generator

All necessary line-parameter registers

Diagnostic loopback logic

Modem status multiplexers.

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CHAPTER 2

INSTALLATION
2.1

SCOPE

This chapter describes the preparation and installation of the DHQ11

option. It contains the following

sections.

2.2

Unpacking

Preparation

Installation

Testing

UNPACKING AND INSPECTION

If ordered as part of a system, the DHQI1 will already be installed, and you should refer to the

instructions for unpacking the system.

If ordered as an add-on option to an existing system, a DHQ11-M (Q-bus module) will be supplied
together with a cabinet kit, distribution panels, and interconnecting cables. The choice of cabinet kit
depends on the type of system and on whether EIA-232-D or DEC423 connection standards apply
(Table 2-1 gives details of these options).

NOTE

DEC423 is a term used in this manual to indicate a
data-leads-only implementation of the RS-423-A
electrical interface standard.

If the equipment is to be installed by DIGITAL Field Service, the customer should not open the
packages.

If the DHQ11 was ordered as an add-on option, find the carton marked OPEN FIRST and carefully
unpack it. There is a shipping list inside the carton.

Undo each package and examine the contents for physical damage. Check that the contents of each
package are complete. Report any damaged or missing items to the shipping agent and to the DIGITAL
representative. Do not dispose of the packing material until the unit has been installed and is
operational.

Table 2-1
DHQ11-M

DHQ11 Options

M3107 module + DHQ11 User Guide (EK-DHQ11-UG)

(Base Option)
EIA-232-D Cabinet Kits

CK-DHQIl11-AA

BA123 boxes

CK-DHQI11-AB
CK-DHQI1-AF

BA23 boxes
H9624 cabinets

Contents
H3173A
BCO5L-1K

4-line 25-way distribution panel
40-way ribbon cable, 21 inch

BCO0S5L-01
BCOS5L-03

40-way ribbon cable, 12 inch
40-way ribbon cable, 36 inch

Y
2

DEC423 Cabinet Kits

CK-DHQI11-WA
CK-DHQ11-WB
CK-DHQI11-WF

BA123 boxes
BA23 boxes
H9624 cabinets

Contents
H3100
BCO5L-1K

Active bulkhead panel
Ribbon cable — 2 inch

1
2

BCO05L-01

Ribbon cable — 12 inch

BC0SL-03
70-22775-1K
70-22775-01
70-22775-03

Ribbon cable — 36 inch
Bulkhead power cable
Bulkhead power cable
Bulkhead power cable

H3104
BCl16C-25

Cable concentrator
Multiway cable

1
1

H3101

Multiway cable loopback

1
1

2.3 PREPARING THE DHQ11 MODULE
Please check that your system has sufficient power and bus load capacity before installing additional
modules; see your system manual. Before installing the DHQ11, you must define three parameters by
selecting them on the DHQI11 on-board switchpacks. The parameters are:
®

Module address

Interrupt vector

DHVI1 or DHUI1 programming mode.
NOTE

Ensure that you are wearing an antistatic wriststrap,
part number 29-11762-00.
2.3.1
Address And Vector Assignment
The DHQI11 has a floating device address and vector. It is shipped from the factory with a device address
of 17760440, and a vector of 300;. These assignments are determined by the floating address and vector
rules. The factory settings are only correct if no other floating address option is installed in the system.
Otherwise, the proper rules for address assignment must be applied; these are given in Appendix C.
2.3.2 Setting The Address Switches
The device address for the DHQI11 is set on the 10-position switchpack E19; the location of this
switchpack is shown in Figure 2-1. Switch 1 on the switchpack is used to setup the module in DHU11 or
DHV11 programming mode.

—

E19

E11

10 POSITION

8 POSITION

SWITCHPACK

(ADDRESS)

(VECTOR)

Figure 2-1

Location of Switchpacks

Figure 2-2 shows how to set the device address on the switchpack. The example shown is for the
factory-set address of 17760440,.

DHU/DHV MODE SELECTION

(DHU MODE SELECTED)
PART OF SWITCHPACK E19

DEVICE ADDRESS SELECTION

LEGEND

D = SWITCH OFF (BINARY 0) OPEN

[

PART OF SWITCHPACK E19

l = SWITCH ON (BINARY 1) CLOSED

EXAMPLE

SETTING

=17760440

INTERPRETED _

AS ALL ONES

]

DECODED

]

[

BY DEVICE

[

SEE NOTE

BIT NO.

DEVICE

ADDRESS

21|

20|

19|18 | 17|16

——

NOTE:

J o

—

|15}

1413|1211
J \

—~——

—

!
|

PENCIL-IN THE ADDRESS
PATTERN YOU NEED

—~

J \

—~——

)

EACH GROUP IDENTICAL

)
0|=6
1

USE THE BLANK ROW TO

|
'
e

|10{09]c8|07}06]05|04]03]|02(01]|00

{
4
MNP

ocloflol=o0
0

?
11

- ;

11=3

110}j0]|=4
1o}

1]=5

1{1]01)=6

111

]=17

REAS04

Figure 2-2

Setting the Device Address

2.3.3
Setting The Vector Switches
The six high-order bits of the interrupt are set on the eight-position switchpack E11. Figure 2-1 shows

the location of this switchpack. Figure 2-3 shows an example of these switches set to the factory setting
of 300 (octal). Switches 1 and 2 are used during manufacture, SW-1 must be set ON (closed), and SW-2
must be set OFF (open) for correct operation of the DHQI11.

MANUFACTURING TEST SWITCHES SW1 MUST BE ON - CLOSED
SW2 MUST BE OFF - OPEN
PART OF SWITCHPACK E11

VECTOR ADDRESS SELECTION
PART OF SWITCHPACK E11

LEGEND

EXAMPLE

SETTING
= 300

SWITCH OFF
(BINARY O) OPEN

SWITCH ON
(BINARY 1) CLOSED

J
I

INTERPRETED
AS ALL ZEROES

!
1DEVICE
BY

DECODED

SEE NOTE

BIT NO.

1511413
.

VECTOR

ADDRESS:

}12

{11
A,

{10}09]08|07(06}05}|04]|03}02|01{00
-

y -

BOTH GROUPS IDENTICAL

NOTE:

—T

USE THE BLANK ROW TO

PENCIL-IN THE ADDRESS
PATTERN YOU NEED

0
10]0]|=0
o1
[|=1
of{1]0|=2

o111

|=3

110|0]|=4a
110]1{=58

1{1]0|=6
1

=7
RE3224

Figure 2-3

Setting the Vector Address

2.3.4 DHV11 Or DHU11 Programming Mode Selection
The DHQI11 offers two separate program interfaces, DHV11 mode or DHU11 mode. Select the mode
appropriate to the device driver within the system, by setting switch 1 of the on-board switchpack E19
(see Figures 2-1 and 2-2).

Modules prior to revision Cl1 have a jumper installed (W1), which locks the module in DHV11 mode.
See figure 2-1 for the position of the jumper. Remove W1 to enable selection of DHV11 or DHU11 mode
by the switch.
NOTE
DHUI11 programming mode generally gives better
performance, because of reduced CPU overhead in
transferring characters to and from the device. The
Software Product Description states whether the
operating system supports DHU11 programming

mode.

2.4 BUS CONTINUITY
Bus grant continuity jumper cards (M9047) are used in vacant backplane slots to provide bus continuity

(see Figure 2-4).

NOTE
To find out the type of backplane on your system,
consult your system manual.
Q/Q BACKPLANE

A
1

Q/CD BACKPLANE

PROCESSOR

PROCESSOR
]

I
|

{

|
|

TERMINATOR

10
11

12
13
RE3202

Figure 2-4

Bus Grant Continuity

2.4.1
Bus Grant Continuity Jumpers
Backplanes suitable for DHQI11 fall into two groups.

Q/CD

—

Q-bus on A and B connectors, user-defined
~signals on C and D

Q/Q

—

Q-bus on A and B, and C and D connectors.

In Q/CD backplanes, bus grant signals pass through each installed module via the A and C connectors
of each bus slot.
Q/Q backplanes are designed so that two dual-height options can be installed in a quad-height bus slot.
The Q-bus lines are routed as follows.
1.

AB, first slot

CD, first slot

2-7

CD, second slot

AB, second slot

and so on.

Each dual-height module extends the continuity of the bus grant signals BIAK and BDMG to the next
module. Therefore, with a Q/Q backplane, if a quad module (DHV11) is replaced with a dual module
(DHQI11), a Q-bus grant continuity card M9047 is needed for the vacant slot.
2.5
PRIORITY SELECTION
The bus (backplane) position may be a compromise between DMA and interrupt priority requirements.
As a general rule, consider DMA request priorities first, and then consider interrupt (bus) requests.

2.5.1

DMA Request Priority
DMA request priority is usually assigned according to throughput. Faster devices (higher throughput)

usually have priority over slower DMA devices; for example, disk has priority over tape, which itself has
priority over communications devices. This is because fast devices usually reach overrun or underrun
conditions sooner than slower ones.
2.5.2 Interrupt Request Priority
The DHQ!1 has a fixed interrupt priority level of 4, and cannot be changed to other priority levels. It
does not monitor any of the higher-level interrupt request lines. Because of this, both the
interrupt-request and DMA (non-processor request) priorities of the DHQI1 are selected by the

position of the DHQI11 on the bus; it must therefore be positioned after any device that does monitor
any of the request lines. Devices closest to the processor module have the highest priority.

2.5.3 Recommendations
In general the DHQI1 bus position is not critical. However, it is recommended that you place the
module after any mass-storage interfaces and high-speed synchronous communications options; these
are more sensitive to bus position.
2.6

INSTALLING THE DHQ11
Once you have defined the backplane position for the DHQI11, you can begin to install the DHQI11
module.

2.6.1

Installing The M3107 Module
WARNING

Shut off the system power and disconnect the main
system power cord before performing any procedure

in this chapter.

ATTENTION
Avant d’effectuer I'une des procédures de ce chapitre,
mettez le systéme hors temsion et débranchez le
cordon d’alimentation.

VORSICHT!

Schalten Sie das System ab, und ziechen Sie das
Netzkabel, bevor Sie die in diesem Kapitel
beschriebenen Anweisungen ausfiihren.

ATENCION

Apague el sistema y desconecfe el cable principal de

alimentacion antes de realizar ningin procedimiento
de este capitulo.

RE2848

Connect the BCOSL cables to J1 and J2. Figure 2-5 for EIA-232-D installations and Figure
2-6 for DEC423 installations show how the parts of the option connect together.

Install the module in its correct backplane position as previously defined.
NOTE

hat

Be careful not to snag module components on the card
guides or adjacent modules.

Check that bus continuity exists. If necessary, install bus grant continuity cards.
Do not connect the cables to the bulkhead panels.

2-9

A. PRINTED(E\[_|<
ON PCB

40-PIN BERG

CONNECTORS

1 CHANNELS
ICACE

RED LINE

TOA

BACKPLANE (Q-BUS}

TO A

H3173-A

DISTRIBUTION
PANEL

25 PIN D-TYPE

RED LINE

RED LINE
T0 A

TOA

CONNECTORS

BCO5L-XX
CABLE

CHANNELS
4707

NOTE:

BCO5L-01 = 30.48 CM (12 INCHES)
BCO5L-1K = 53.34 CM (21 INCHES)
BCO5L-03 = 91.44 CM (36 INCHES)

RES

Figure 2-5

Installing the DHQ11 (EIA-232-D)

-]
:

H3100

(32

70-22775-XX

PIN A

~ BACKPLANE

BCOSL-XX

CABLE

?\4’ o~ \
i

BACKPLANE

(Q22/LS! BUS)

e {

40-PIN BERG

Ayl

[

(Q22/LSI BUS)

% 1.i\\/—\\

CONNECTORS

H3100 ACTIVE

BULKHEAD PANEL

NN
COLOURED STRIP
POWER CABLE
70-22775-XX

NOTE:

BCO5L-01=30cm (12 INCHES)
BCOSL-1K=53cm (21 INCHES)
BCOS5L-03=92cm (36 INCHES)
RE3203

Figure 2-6

Installing the DHQI11 (DEC423)
2-10

2.6.2 Distribution Panels
The rear I/O distribution panel has six cutouts: two type-A cutouts and four
type-B
a removable bracket between the third and fourth cutout allows you

cutouts. In addition,

to install three more type-A insert

panels by mounting an adapter plate. Figure 2-7 shows typical type-A and
type-B insert panels, and the
adapter plate.
2.6.3

Installing The EIA-232-D Distribution Panels

The DHQI1 has two type-B distribution panels. Figure 2-7 shows how these
are installed in a BA23 box.
Installation in BA123 and H9642 cabinets is similar.
To fit the distribution panels:
1.

Remove the two type-B blanking panels.

Bolt the two H3173-A distribution panels into the cutouts.

Connect the free end of the BCOSL-XX cable from connector J1 of the module
to the first
distribution panel.

Connect the free end of the BCOSL-XX cable from connector J2 of the module to the

distribution panel.

second

REMOVABLE INSERT

€

50-PIN CONNECTOR
EXPANSION SLOTS-TYPE A
RE3204

Figure 2-7

1/O Insert Panels and Adapter Plate (EIA-232-D)

2.6.4 Installing The DEC423 Distribution Panels
The DHQI1 has one type-B distribution panel. Figure 2-8 shows how this is installed in a BA23 box.

Installation in BA123 and H9642 cabinets is similar.

2-11

To fit the distribution panels:
1.

Remove a type-B blanking panel.

Bolt the H3100 active distribution panel into the cutout.

Connect the free end of the BCOSL-XX cable from connector J1 of the module to the upper
(J2) connector on the distribution panel.

Connect the free end of the BCOSL-XX cable from connector J2 of the module to the lower
(J1) connector on the distribution panel.

Connect the free end of the power cable (70-22775-XX) to the left-hand power connector (J5)
on the distribution panel.

REMOVABLE INSERT

€

@
®

50-PIN CONNECTOR
EXPANSION SLOTS
RE3205

Figure 2-8
2.7

I/O Insert Panel (DEC423)

INSTALLATION TESTING

This section details the diagnostics used to test the option during and after installation. The diagnostics
are also used to test other Q-bus modules in the same family, for example, DHV11. The diagnostics will
automatically ‘size’ the option to determine which one is being tested.
Both MicroPDP-11 and MicroVAX II diagnostics are described. After successful completion of the
appropriate system test, the DHQI1 may be connected to external equipment. Further information on
the diagnostics is given in Chapter 4.

2.7.1

Installation Tests On MicroPDP-11 Systems

To verify that the MicroPDP-11 system and the DHQI11 module are functioning correctly:

2-12

Switch on the system.

After 2 seconds, check that the green self-test LED on the DHQ!1 module is on. If it does not

come on, call DIGITAL Field Service.

Boot the Micro-11 Customer Diagnostic media. Refer to your MicroPDP-11 System Manual
for further information.
.

Type ‘T’ at the main menu to allow the diagnostics to identify the new module, and add it to
the configuration file.

NOTE
Look at the list of devices displayed, and make sure
that the new module is included. If it is not included,
repeat the installation sequence, and make sure that

the module switches have been set correctly.
5.

Type ‘T’ at the main menu to run the system tests. These should complete without error; if an
error occurs, call DIGITAL Field Service.

A MicroPDP-11 Maintenance Kit is available, and may be ordered from your local DIGITAL office.
This kit allows traiued personnel to run individual diagnostic programs under the XXDP + diagnostic
monitor, and to configure and run DECX11 system test programs. The XXDP+ functional diagnostic
is VHQA**.BIN, and the DECX11 module is XDHV** OB]J.
2.7.2 Testing In MicroVAX II Systems
To verify that the MicroVAX II system and the DHQI11 module are functioning correctly:

1.
2.

Check that the green self-test LED on the DHQI1 module is on.
Boot the MicroVAX Maintenance System media. Refer to your MicroVAX II System Manual

for further information.
3.

Type ‘2’ at the main menu to show the system configuration and devices.

NOTE
Look at the list of devices displayed, and make sure
that the new module is included. If it is not included,
repeat the installation sequence, and make sure that
the module switches have been set correctly.
4.

Type ‘I’ at the main menu to run the system tests. These should complete without error; if an
error occurs, call DIGITAL Field Service.

2.8
H3101 LOOPBACK CONNECTOR
The H3101 loopback connector (see Figure 2-9) is used during diagnostic tests for DEC423 installations.
It is two loopback connectors in one package, and consists of a female 36-way loopback connector and a
male 36-way loopback connector. It can be inserted into the cabling at the distribution panel, or at the

cable concentrator. To test the cables, type characters at the keyboard and make sure that they are
echoed to the screen (refer to Chapter 4).

2-13

RE2439

1
LINE

LINE 2

LINE 3

LINE 4

LINE S

MALE CONNECTOR

LINEG

LINE 7

; Rx + © IZ[ O Rx + z
3 Rx+cc‘:_| 4[—_;.>0Rx+ ;
Tx + O=

+
O Tx

Tx +

+
Tx

Tx + ©-

+
o Tx

Tx+ ©

+
O Tx

Tx + 0—

-0 Tx +

Tx+ ©

+
O Tx

Tx+ O—

+
o Tx

Tx + O

I15I

O Tx +

Rx + ©

+
O Rx

; Rx + & IGfioRxfi- i
g Rx + o IS[ —0 Rx + %
3 Rx + O l‘lO[ o Rx + z
3 Rx + © I‘I2I © Rx + }
3 Rx + © 114l o Rx + }
3

NOT USED o-

NOT USED oLINEO

LINE 1

LINE 2

LINE 3

LINE 4

LINES

LINE 6

LINE 7

Tx=- ©

J18I
19

g Rx - o- 120[

}

o Tx
-

o Rx - $

—0 Tx -

Tx - o

0 Tx
-

Tx=- O

~0 Tx -

o Rx- i

o Rx - }

Tx=- o

-0 Tx

Tx - o0—

o Tx=-

Tx- ©

O Tx~

Tx- ©

]33[

O Tx -~

Rx - o

-0 NOT USED

3 Rx= © |30!7 o Rx - }
; Rx~ © l32l O Rx- z
g

NOT USED o

'36[

LINE 2

LINE 3

LINE 4

LINES

LINE 6

LINE 7

Tx- ©

; Rx—- © ]28[

LINE 1

—0 NOT USED

; Rx- © I22l o Rx~- 2
g th--(‘ril24l O Rx - §
; Rx - o- l26I

LINE O

LINEO

LINE 1

FEMALE CONNECTOR

LINEO

LINE 2

LINE 3

LINE 4

LINES

LINE 6

LINE 7

o NOT USED
RE2438

Figure 2-9

H3101 Loopback Connector
2-14

2.9

CABLES AND CONNECTORS — EIA-232-D

2.9.1

Distribution Panel
Each H3173-A distribution panel adapts one of the DHQI11 Berg connectors to four subminiature
D-type EIA-232-D connectors. Noise filtering is provided on each pin of the EIA-232-D connectors.
This reduces electromagnetic radiation from the cables and also provides the logic with some protection
against static discharge.

Figure 2-13 shows the circuit of the H3173-A. There is no CCITT equivalent of EIA circuit AA
(Protective Ground). To implement this circuit, a ground strap must be installed between the H3173-A
and the system cabinet. The 0-ohm link W1 (not installed at the factory) can then be installed to connect
this circuit, and removed to disconnect it, as needed.

2-15

B | TRANSMIT DATA
,
8
0/4

2
3

DATA CARRIER DETECT 2/6

C
S|

RECEIVE DATA 0/4

3
o

DATA SET READY 2/6

DATA TERMINAL READY 0/4

2'0

E | RING INDICATOR 0/4
&

22
22

REQUEST TO SEND 2/6

F | CLEARTO SEND 0/4
£

5
3

CLEAR TO SEND 2/6

H | REQUEST TO SEND 0/4
4

4
3

RING INDICATOR 2/6

DATA TERMINAL READY 2/6

°®

K
S|

DATA SET READY 0/4

6
S

RECEIVE DATA 2/6

L | DATA CARRIER DETECT 0/4
L

8
S

TRANSMIT DATA 2/6

SIGNAL GROUND

J2
M
M | SIGNAL GROUND

7
3

N
N | TRANSMIT DATA 1/5

2
2

DATA CARRIER DETECT 3/7

P
&_|

3
3

DATA SET READY 3/7

RECEIVE DATA 1/5

DATA TERMINAL READY 1/5

2'0

S
|

RING INDICATOR 1/5

22
2

REQUEST TO SEND 3/7

T
e—|

CLEARTO SEND 1/5

5
3

CLEAR TO SEND 3/7

4
&

RING INDICATOR 3/7

) | REQUEST TO SEND 1/5
§
V
®

DATA TERMINAL READY 3/7

w
W | DATA SET READY 1/5

6
$

RECEIVE DATA 3/7

TRANSMIT DATA 3/7

DATA CARRIER DETECT 1/5

e 00 O

;

SIGNAL GROUND

oy O O O LB o on

A
_]

00 60 &— &

]

SIGNAL GROUND

oy o0 0w 0N ON o on

TMTM

—
g

— PROTECTIVE GROUND
/Dt147

Figure 2-10

H3173-A Circuit Diagram

Table 2-2 is for two distribution panels. The numbers within parentheses apply to channels 4 to 7.
Table 2-2

H3173-A Connections

Signal

Name

Circuit No.

J5 Pin No.

SIG GND 0(4)
TXDO0(®4)
RXDO0(4)
DTRO(4)
RI0(4)
CTS0(4)
RTS0(4)

Transmitted Data
Received Data
Data Terminal Ready
Ringing Indicator
Clear to Send
Request to Send

102
103
104
108/2
125
106
105
107
109

1-A (2-A)
1-B (2-B)
1-C (2-C)
1-D (2-D)
1-E (2-E)
1-F (2-F)
1-H (2-H)
1-K (2-K)
1-L (2-L)

SIG GND 1(5)
TXD1(5)
RXD1(5)
DTRI(5)
RI1(5)
CTS1(5)
RTSI1(5)
DSRI1(5)
DCDI1(5)

102
103
104
108/2
125
106
105
107
109

1-M (2-M)
1-N (2-N)
1-P (2-P)
I-R (2-R)
1-S (2-S)
1-T (2-T)
1-U (2-U)
1-W (2-W)
1-X (2-X)

DCD2(6)
DSR2(6)
RTS2(6)
CTS2(6)
RI2(6)
DTR2(6)
RXD2(6)
TXD2(6)
SIG GND 2(6)

109
107
105
106
125
108/2
104
103
102

1-Y (2-Y)
1-Z (2-Z)
1-BB (2-BB)
1-CC (2-CC)
1-DD (2-DD)
1-EE (2-EE)
1-FF (2-FF)
1-HH (2-HH)
1-JJ (2-1))

DCD3(7)
DSR3(7)
RTS3(7)
CTS3(7)
RI3(7)
DTR3(7)
RXD3(7)
TXD3(7)
SIG GND 3(7)

109
107
105
106
125
108/2
104
103
102

1-KK (2-KK)
1-LL (2-LL)
1-NN (2-NN)
1-PP (2-PP)
1-RR (2-RR)
1-SS (2-SS)
1-TT 2-TT)
1-UU (2-UU)
1-VV (2-VV)

DSRO0(4)
DCDO0(4)

Data Set Ready
Data Carrier Detected

The following examples show how to use Table 2-2.

Signal TXDO is the transmitted data line for channel 0; the CCITT circuit number is 103 and it 1s

connected to J5 pin B on the first H3173-A for channels 0 to 3.

Signal TXD4 is the transmitted data line for channel 4; the CCITT circuit number is 103 and it is
connected to J5 pin B on the second H3173-A for channels 4 to 7.

2.9.2 Null Modem Cables
Null modem cables are used for local EIA-232-D connection, when a modem is not used. Because of
Federal Communications Commission (FCC) regulations, the cable specifications for the United States
and Canada are different from those for non-FCC countries. Other countries may also have similar
electromagnetic interference (EMI) control regulations. EMC/RFI shielded cabinets are now available
for systems which conform to FCC requirements.
Recommended null modem cables are as follows.
1.

BC22D (for EMC/RFI shielded cabinets)

Rounded 6-conductor fully shielded cable to FCC specification

Subminiature 25-pin D-type female connector moulded on each end

Lengths available:

BC22D-10
BC22D-25
BC22D-35
BC22D-50
BC22D-75
BC22D-A0
BC22D-B5
2.

(10 ft)
(25 ft)
(35 ft)
(50 ft)
(75 ft)
(100 ft)
(250 ft)

BCO3M

Round 6-conductor (three twisted pairs), each pair shielded

Cables over 30.5 m (100 ft) have a 25-pin subminiature D-type female connector at one
end. The other end is unterminated, for passing through the conduit

Cables 30.5 m (100 ft) and less have a similar connector at each end

Lengths available:

BCO3M-25

BCO3M-A0Q
BCO03M-BS
BCO03M-E0

BCO3M-LO
3.

3.1m
7.6 m
10.7m
152m
29m
30.5m
762m

7.6 m

305m
762m
1524m

3048 m

(25 ft)

(100 ft)
(250 ft)
(500 ft)

(1000 ft)

BC22A
®

Round 6-conductor cable

Subminiature 25-pin D-type female connector moulded at each end

2-18

Lengths available:

BC22A-10
BC22A-25

3.1 m
7.6 m

(10 ft)
(25 ft)

Cables of groups 1, 2, and 3 are all connected as in Figure 2-11. The cables are not polarized. They can
be connected either way round.

PIN
NUMBERS

PROTECTIVE GROUND _

. o_PROTECTIVE GROUND

RECEIVED DATA .

, o TRANSMITTED DATA
5 oRECEIVED DATA

TRANSMITTED DATA , ,

+ oSIGNAL GROUND

SIGNAL GROUND ,

DATA TERMINAL READY

& o_DATA SET READY

DATA SET READY

20 oDATA TERMINAL READY

RD11S0

Figure 2-11
2.9.3

Null Modem Cable Connections

Full Modem Cables

Recommended full modem cables are as follows:
1.

BC22F (for EMC/RFI-shielded cabinets)

Rounded 25-conductor fully shielded cable

Subminiature 25-pin D-type female connector on one end, male connector on the other

Lengths available:

BC22F-10
BC22F-25
BC22F-35
BC22F-50
BC22F-75
2.

3.1m
7.6 m
10.7 m
152 m
229 m

(10 ft)
(25 ft)
(35 ft)
(50 ft)
(75 ft)

BCOSD

Round 25-conductor cable

Subminiature 25-pin D-type, female connector on one end, male connector on the other

2-19

Lengths available:
BCO5D-10

3.1m

(10 ft)

BC05D-25

7.6 m

(25 ft)

BCO05D-50
BCO05D-60

BCO5D-A0

152 m
186m

30.5m

(50 ft)
(60 ft)

(100 ft)
NOTE

some countries, protective hardware may be
needed when connecting to certain lines. Refer to the
national regulations before making a connection.

2.10 CABLES AND CONNECTORS — DEC423
The H3100 active distribution panel adapts the the two DHQ11 Berg connectors to one 36-way AMP
connector. Noise filtering is provided on each pin of the connector. This reduces electromagnetic
radiation from the cables and also provides the logic with some protection against static discharge.

Table 2-3 shows connections to the 36-pin AMP filtered connectors used on DHQI11 with DEC423
installations.
Table 2-3

Serial-Line Connections for the 36-Pin Connector

1
2

Blu/Wht
Org/Wht

Line 0
Line 0

Transmit +
Receive +

19
20

Wht/Blu
Wht/Org

Line O
Line 0

Transmit —
Receive —

3
4

Gm/Wht
Brn/Wht

Line 1
Line 1

Transmit +
Receive +

21
22

Wht/Grn
Wht/Brn

Line 1
Line 1

Transmit —
Receive —

Slt/Wht

Line 2

Transmit +

Wht/Slt

Line 2

Transmit —

Biu/Red

Line 2

Receive +

Red/Blu

Line 2

Receive —

7
8

Org/Red
Gm/Red

Line 3
Line 3

Transmit +
Receive +

25
26

Red/Org
Red/Gm

Line 3
Line 3

Transmit —
Receive —

Brn/Red

Line 4

Transmit +

Red/Brn

Line 4

Transmit —

Slt/Red

Line 4

Receive +

Red/Slt

Line 4

Receive —

11
12

Blu/Blk
Org/Blk

Line 5
Line 5

Transmit +
Receive +

29
30

Blk/Blu
Blk/Org

Line 5
Line 5

Transmit Receive —

Gm/Blk

Line 6

Transmit +

Blk/Gm

Blk/Brn

Line 6

Transmit —

15
16

Slit/Blk
Blu/Yel

Line 7
Line 7

Transmit +
Receive +

33
34

Blk/Slt
Yel/Blu

Line 7
Line 7

Transmit —
Receive —

17
18

Org/Yel
Grn/Yel

Spare
Spare

35
36

Yel/Org
Yel/Gm

Spare
Spare

Brn/Blk

Line 6

Receive +

2-20

Receive —

CHAPTER 3

PROGRAMMING
3.1 SCOPE
This chapter describes the device registers, and how they are used to control and monitor the DHQI11.
The chapter covers:
®

The bit functions and format of each register

. ®

Programming features available to the host.

Some programming examples are also included.

NOTE

DHU11 programming mode is the preferred mode of
operation for the DHQ11. The development of user
drivers that use the DHQ11 in DHV11 programming
mode is not recommended.
3.2

REGISTERS

The host system controls and monitors the DHQ11 module through several Q-bus-addressable registers.
Command words or bytes written to the registers are interpreted and executed by the module. Status
reports and data are also transferred through the registers.
3.2.1

The DHQI11 registers occupy 8 words (16 bytes) of Q-bus memory-mapped 1/O space.

The base physical address of the eight DHQ11 registers is selected by using switches on the module. The
address selected is in the peripheral I/O space. The term ‘base’ means the lowest I/O address on the
module; that is to say, when the four low-order address bits = 0.

Table 3-1 and 3-2 list the DHQ11 registers and their addresses in DHV11 and DHU11 mode: The suffix
(I) means that there are eight of these registers, one for each channel. When an (I) register is accessed, the
contents of CSR
< 3:0> select which of the eight registers at that address is actually accessed.
NOTE

CSR<3:0> allows up to 16 channels to be
addressed. However, only the lower eight channels are
used. Therefore CSR bit 3 must always be 0.

Table 3-1

DHQI11 Registers in DHV11 Mode

Address

Type

Base
Base+2
Base+2(I)
Base+4(I)
Base+6(I)
Base+10(I)
Base+ 12(I)
Base+ 14(I)
Base+ 16(I)

Read/Write
Read Only
Write Only
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write

(Octal)

Control and Status Register
Receive Buffer
Transmit Character
Line-Parameter Register
Line Status
Line Control
Transmit Buffer Address 1
Transmit Buffer Address 2
Transmit Buffer Count
Table 3-2

(CSR)
(RBUF)
(TXCHAR)
(LPR)
(STAT)
(LNCTRL)
(TBUFFADI1)
(TBUFFAD?2)
(TBUFFCT)

DHQI11 Registers in DHU11 Mode

Address

Type

Base
Base+2
Base+2
Base+4(I)
Base+6(I)
Base+6(I)
Base+7(I)
Base+10(1)
Base-+12(1)
Base+ 14(1)
Base+ 16(I)

Read/Write
Read
Write (byte)
Read/Write
Write
Read (byte)
Read (byte)
Read/Write
Read/Write
Read/Write
Read/Write

(Octal)

Control and Status Register
Receive Buffer
Receive Timer*
Line-Parameter Register
FIFO Data
FIFO Size
Line Status
Line Control
Transmit Buffer Address 1
Transmit Buffer Address 2
Transmit Buffer Count

(CSR)
(RBUFF)
(RXTIMER)
(LPR)
(FIFODATA)

(FIFOSIZE)
(STAT)
(LNCTRL)
(TBUFFADI1)
(TBUFFAD2)
(TBUFFCT)

* Only accessible when CSR3:0> = 0000

NOTE
It is possible to write to the line-status register.
However, the host should not write to this register.

There are eight line-parameter registers, only one of which is accessed at any one time. The register
which is accessed is associated with the line selected using CSR <3:0>.

For example, to read the line-parameter register of channel 3, the following I/O commands would be
executed:
MOVB #CHAN,#BASE
MOVB #BASE+4,R0

;WRITE CHANNEL NUMBER (SEE BELOW) TO CSR
;READ THE LINE PARAMETER REGISTER

In the above example, CHAN = 0er00011(binary)
Where:

3-2

the RXIE bit of the CSR
the MASTER.RESET bit (which would be 0)
channel number 3

0011

NOTE

Not all register bits are used. In a write action,
all unused bits must be written as 0s. In a read
action, unused bits are undefined.

Read-modify-write instructions may be used on
all registers except CSR and RBUF.

3.2.2 Register Bit Definitions
Registers which are modified by reset sequences are coded as shown in Figure 3-1.

CLEARED BY MASTER RESET

SET BY MASTER RESET

‘

CLEARED BY BINIT
BUT NOT BY MASTER RESET

RD2249

Figure 3-1
3.2.2.1

Control And Status Register (CSR) —

CSR (BASE)

RR/VJR

DIAGNOSTICS

ACTION

| FAILURE

Kfi"émg_e TRANSMIT
)

DMA ERROR

TRANSMIT
LINE NUMBER

RR/WJR/WFVWJR/WR/WR/WR/W
RCVE

[

SKIP

L’}'JABLE
e

RCVE DATA

AVAILABLE

INDIRECT ADDRESS REG POINTER

(CHANNEL NO.)

MASTER
RESET

*DHU11 MODE ONLY

UNUSED IN DHV11 MODE
RE10

Bit

Name

Description

TX.ACTION

This bit 1s set by the DHQ11 when:

(Transmitter Action) (R)

The last character of a DMA buffer has left the
OCTART.

A DMA transfer has been aborted.

A DMA transfer has been terminated by the
DHQI1 because non-existent memory has been
addressed, or because of a host memory parity
error.

DHVIl]

mode:

single-character

programmed output has been accepted; that is
to say, the character has been taken from
TX.CHAR.
5.

In DHU11 mode, following a programmed data
transfer, the module has emptied a transmit
FIFO.

The bit is cleared if the host reads the CSR after the
TX.ACTION FIFO has become empty. To avoid
losing TX.ACTION reports, the host must not let
more than 16 reports accumulate. It is advisable to
read the CSR until TX.ACTION becomes clear.

NOTE
TX.ACTION reports may be lost if the upper byte of
the CSR is discarded following a read of the CSR.
14

TXIE
(Transmit Interrupt Enable)

When set, this bit atllows the DHQI11 to interrupt the
host when CSR
< 15> (TX.ACTION) becomes set.

(R/W)
It
is
<cleared
by
MASTER.RESET.
13

DIAG.FAIL
(Diagnostic Fail) (R)

BINIT,

but

not

When set, this bit indicates that the DHQ11 internal
diagnostics have detected an error. The error may
have been detected by the self-test sequencer or by
the background monitor program (BMP).

3-4

Bit

Name

Description

This bit is associated with the diagnostic-passed
LED. When it is set, the LED will be off. When it is

cleared, the LED will be on.

The bit is set by MASTER.RESET. It is cleared after
the self-test has run successfully.

Not valid if MASTER.RESET is set.
12

TX.DMA.ERROR

(Transmit DMA Error) (R)

If this bit is set and TX.ACTION is also set, either
the channel indicated by CSR <11:8> has failed to
transfer DMA data within 10 microseconds of the
bus request being acknowledged, OR there is a host

memory parity error.

The TBUFFADI! and TBUFFAD?2 registers will
contain the address of the memory location at which
the error occurred. TBUFFCT will be cleared.
<11:8>

TX.LINE

(Transmit Line Number) (R)
RX.DATA.AVAIL

(Received Data Available) (R)

If TX.ACTION is set, these bits hold the line

number to which TX.ACTION refers.

When set, this bit indicates that a received character
is available. It is clear when the receive FIFO is
empty. It is used with RXIE to request a receive
interrupt.

It is set after MASTER.RESET because the receive
FIFO contains diagnostic information.

RXIE

(Receiver Interrupt Enable)

(R/W)

When set, this bit allows the DHQI11 to interrupt the
host when RX.DATA.AVAIL is set. An interrupt is
generated under the following conditions.
1.
2.

RXIE is set and a character is placed into an

empty receive FIFO.

The receive FIFO contains one or more
characters, and RXIE is changed from 0 to 1.

It is cleared by BINIT but not by MASTER.RESET.
MASTER.RESET
(Master Reset) (R/W)

This bit is set by the host to reset the module. It stays

set while the DHQ11 runs the self-test and performs
an initialization sequence. The bit is then cleared to
tell the host that the process is complete.

3-5

Bit

Name

Description
This bit can be set directly by the host, or indirectly
by BINIT (bus initialization signal).

SKIP (Skip Self-Test)

In DHU11 mode, this bit is used (RW) to shorten the

reset/initialization time to about 30 milliseconds.

The host program must only set this bit at the same
time as it sets MASTER.RESET. It must then clear
the bit, but must wait at least 20 microseconds before
doing so. It is recommended that the host always set
SKIP when setting MASTER.RESET. The DHQ11
will execute the full self-test, regardless of whether
SKIP is set or not. The 1.7 seconds delay during
MASTER.RESET is purely for DHU11 hardware
compatibility. In DHV11 mode, this bit is ignored
for compatibility reasons.
<3:0>

IND.ADDR.REG
(Indirect Address Register)

(R/W)

For indexed registers, these bits select one of sixteen
channels. However, on the DHQI11 only the lower
eight channels are defined. So, when writing these
bits, CSR
< 3> must be zero.

3.2.2.2

Receive Buffer (RBUF) — A read from ‘base + 2’ is interpreted by the DHQ11 hardware as a
read from the receive FIFO. Therefore RBUF is a 256-character register with a 1-word address. The
least-significant bit (LSB) of the character is in bit 0.
RBUF (READ BASE + 2)

1
RECEIVED

DATA

VALID

FRAMING

ERROR

RECEIVE

CHARACTER

LINE NUMBER

O,R

DATA SET

OVERRUN
ERROR

PARITY
ERROR

STATUSIJ FLAGS

(FROM HIGH BYTE
OF STAT)

OIR

DIAGNOSTIC INFO
RE2723

3-6

Bit

Name

Description

DATA.VALID

This bit is set if there is data in the receive FIFO.

(Data Valid) (R)

When this bit is clear, the contents of RBUF < 14:0>
is not valid.

After self-test, diagnostic information is loaded into
the receive FIFO. Therefore, this bit is always set
after a successful master reset sequence.

OVERRUN.ERR
(Overrun Error) (R)

This bit is set if one or more previous characters of
the channel indicated by bits <11:8> were lost
because of a full receive FIFO.

NOTE

The ‘all 1s’ code for bits <14:12> is reserved. This
code indicates that RBUF<7:0> holds modem
status or diagnostic information.

FRAME.ERR
(Framing Error) (R)

This bit is set if the first stop bit of the received
character was not detected (also see RX.CHAR).

PARITY.ERR
(Parity Error) (R)

This bit is set if this character has a parity error, and if
parity is enabled for the channel indicated by bits

RX.LINE
(Receive Line Number) (R)

These bits hold the binary number of the channel on
which the character of RBUF <7:0> was received,

RX.CHAR

-If RBUF<14:12> = 000, these eight bits contain

<11:8>

<7:0>

(Received Character) (R)

< 11:8> (also see RX.CHAR).

or on which a data-set change was reported.

the oldest character in the receive FIFO. The

character is good.

If RBUF<14:12> = 001, 010, or 011, these eight
bits contain the oldest character in the receive FIFO.
The character is bad.

If RBUF<14:12> = 111, these eight bits contain
diagnostic or modem status information. In this case,
RBUF <0> has the following meanings.
0
1

3-7

Modem status in RBUF <7:1>
Diagnostic information in RBUF <7:1>

Bit

Name

Description
If there is an overrun condition, the four-character
UART receive buffer for that channel will be cleared.
This data will be lost. A null character is placed in the

receive FIFO, and RBUF < 14> is set.

The DHQI11 does not have a break-detect bit. A line
break is indicated to the program as a null character
with FRAME.ERR set, and overrun is clear.

3.2.2.3 Transmit Character Register (TXCHAR)
- Single-character programmed transfers are made
through the transmit character register.
TXCHAR (WRITE BASE + 2 ,DHV11 MODE)

\2%

\4%

TRANSMIT

DATA VALID

CHARACTER

Bit

Name

TX.DATA.VALID

Description
When set, this bit instructs the DHQI11 to transmi
t

(Transmit Data Valid) (W)

the character held in bits < 7:0> . The bit is sensed by
the DHQI11, which then transfers the character, clears
the bit, and sets TX.ACTION.
TX.DATA.VALID and TX.CHAR can be written
together, or by separate MOVB instructions.

<7:0>

TX.CHAR

This contains the chardcter to be transmitted. The
LSB is bit 0.

(Transmit Character) (W)
3.2.2.4

Receive Timer Register (RXTIMER), DHU11 Mode
Only — The indirect address register
(CSR <3:0>) must = 0000 in order to access the receive
timer. The host can use the timer to delay the
receive interrupt.

Rx TIMER (WRITE BASE+2,DHU11 MODE)

Wiwilwliwiw]lw]|wlw

RE2750

3-8

Bit

Name

Description

<7:0>

RX. TIMER
(Receive timer)

The receive interrupt is normally raised when a
received character is loaded into the previously
empty receive FIFO. The binary number loaded into
RX.TIMER modifies this procedure as follows.
0 = Infinite timeout. This timeout will be overridden
by the conditions below.
1 = No timeout.
immediately.

The interrupt will be raised

2 to 255 = Timer delay in milliseconds.

The timer is overriden when the receive FIFO
becomes three-quarters full (critical) or when a
modem status change is written to the FIFO.
This bit is set to 1 by MASTER.RESET.
3.2.2.5

Line-Parameter Register (LPR) — This register is used to configure its associated channel.

LPR (BASE + 4)

12
4

11
7

RWI|RW|RWIRWI|rRW|[RW|RW|RW]|RW|RW|RW]|RW|RW]|RW|RW|RW

TRANSMIT

STOP

SPEED

RECEIVE

PARITY

CODE

ENABLE -

EVEN

SPEED

PARITY

CHARACTER

LENGTH

DIAGNOSTIC

CODE

DISABLE

XON/XOFF

REPORTING
RE3I233%

3-9

Bit

Name

Description

<15:12>

TX.SPEED

(Transmitted Data Rate) (R/W)

This bit is set to 1101 by MASTER.RESET (9600
bits/s). It defines the transmit data rate (Table 3-2).

<11:8>

RX.SPEED

This bit is set to

(Received Data Rate) (R/W)

bits/s). It defines the receive data rate (Table 3-2).

STOP.CODE

This bit defines the length of the transmitted stop bit.

(Stop Code) (R/W)

1101

by MASTER.RESET (9600

1 stop bit for 5-, 6-, 7-, or 8-bit characters

1 =

2 stop bits for 6-, 7-, or 8-bit characters, or 1.5

stop bits for 5-bit characters
The bit is cleared by MASTER.RESET.
6

EVEN.PARITY

If LPR<5> is set, this bit defines the type of parity.

(Even Parity) (R/W)
1 = Even parity
0 = Odd parity

The bit is cleared by MASTER.RESET.
5

PARITY.ENAB
(Parity Enable) (R/W)

This bit causes a parity bit to be generated on transmit,
and checked and stripped on receive.
1 = Parity enabled
0 = Parity disabled

The bit is cleared by MASTER.RESET.

3-10

Bit

Name

Description

<4:3>

CHAR.LGTH
Character Length) (R/W)

These two bits define the length of characters. The
length does not include start, stop, and parity bits.
00
01
10
11

=
=
=
=

5 bits
6 bits
7 bits
8 bits

They are set to 11 by MASTER.RESET.
<2:1>

Diagnostic control codes are are used by the host as

DIAG

follows.

(Diagnostic Code) (R/W)

00 =

Normal operation

01 =

Causes the background monitor program
(BMP) to report the DHQI11 status through
the receive FIFO.

Other codes are reserved.

<0>

DISAB.XRPT

(Disable XON/XOFF

XON and XOFF characters are reported on

1 =

If LNCTRL <4> is also set for a particular
channel, these characters are filtered from the
received data stream, to relieve the host of the

all channels.

Reporting) (R/W)

need to do so.

On initialization, this bit is cleared. In order to read or

write to this bit, CSR <3:0> must equal zero.
NOTE

An XON code = 21;=DC =CTRL/Q. An XOFF
code =23;=DC3=CTRL/S. No other codes are

specified for the interface.

Table 3-3

Code

0000
0001
0010

Data Rates

Maximum

Data Rate

Error (%)

(Bits/s)

0.01
0.01
0.08

50
75
110

3-11

Table 3-3
Code

Data Rates (Cont.)

Data Rate

Maximum

(Bits/s)

Error (%)

0011

134.5

0100
0101

150
300

0110
0111

600
1200

0.01

1000
1001
1010
1011

1800
2000
2400
4800

0.01
0.19
0.01
0.01

1100
1101

7200
9600

0.01

1110

19200

1111

38400

0.01
0.01

0.07
0.01
-

0.01
0.01

0.01

3.2.2.6 Line-Status Register (STAT) — The high byte of this register holds modem status information.
In DHV11 mode, the low byte is undefined.
STAT (READ BASE+6
15

DSR

DCD
RI

(RING

DHUID

SETTO O, DHV11 MODE
CTS

INDICATOR)

MDL
0 = MODEM SUPPORT PROVIDED FOR THIS LINE

1 = MODEM SUPPORT NOT PROVIDED FOR THIS LINE
RE2722

Bit

Name

Description

DSR
(Data Set Ready) (R)

This bit gives the present status of the Data Set

Ready (DSR) signal from the modem.
1 = ON
0 = OFF

3-12

Bit

Name

Description
NOTE

In order to report a change of modem status, the
DHQ11 writes the high byte of STAT into the low
byte of RBUF. RBUF <14:12> = 111 indicates to
the host that RBUF <7:0> holds modem status
information instead of a received character.

RI
(Ring Indicator) (R)

This bit gives the present status of the Ring Indicator
(RI) signal from the modem.
1 = ON
0 = OFF

DCD

(Data Carrier Detected) (R)

This bit gives the present status of the Data Carrier
Detected (DCD) signal from the modem.
1 = ON
0 = OFF

CTS
(Clear to Send) (R)

This bit gives the present status of the Clear To Send
(CTS) signal from the modem.
1 = ON
0 = OFF

MDL
(MDL Modem Support Low) (R)

Always reads as 0 for DHQI11, to indicate that the
module has modem support capability.

NOTE.

It is only necessary to read the modem support status
for one line, since all the other lines will have the same
setting.

DHUID (DHUI11 Identification
bit) (R)

This bit allows software to distinguish between
DHV11 mode and DHUI11 mode.
0
1

3-13

DHV1l1
DHU11

3.2.2.7

FIFO Size Register (FIFOSIZE), DHU11 Mode Only — This low-byte register holds a number

which indicates the space available in the transmit FIFO.
FIFOSIZE (READ BASE+6,DHU11 MODE)
15

DSR

OO0

R
4

DCD

ALWAYS O
L

CTS

(RING

—

FIFO SIZE 0 TO 64

DHUID

INDICATOR)

SETTO 1, DHU11 MODE
MDL

0 = MODEM SUPPORT PROVIDED FOR THIS LINE
1 = MODEM SUPPORT NOT PROVIDED FOR THIS LINE

Bit

Name

Description

<7.0>

FIFOSIZE
(FIFO Size)
(R BYTE)

This byte indicates the (in characters) available space
in the transmit FIFO. The range is 00000000 (binary)
to 01000000 (binary) (0 to 64 (decimal)). This register

should be read before sending a character, or a
sequence of characters, to the transmit FIFO data
register.

The

byte

set

MASTER.RESET.

3.2.2.8

01000000

(binary)

FIFO Data Register (FIFODATA), DHU11 Mode Only — To send a character or characters

through a transmit FIFO, the host writes the character(s) to the transmit FIFO, data register of the
appropriate channel. To make sure that there is room in the transmit FIFQO, the host should first read the
associated transmit FIFO size register. If single characters are sent, they must be written to the low byte
of FIFODATA.
FIFODATA (WRITE BASE+6,DHU11 MODE)
15

WIWIWIWIWIWIWIWIWIWIWIWI[IWIW|IW]W

“

TX DATA CHARACTER

TX DATA CHARACTER
RE2720

3-14

Bit

Name

Description

<15:0>

FIFODATA<15:0>

This word contains two characters for transfer
through the transmit FIFO. After a write-word
action to this register, FIFODATA <7:0> and then
FIFODATA < 15:8> are transferred to the transmit
FIFO.

(FIFO Data Register)

(W)

The least-significant bits of the characters are in
FIFODATA bits 0 and 8.
<7:.0>

FIFODATA<7:0>
(FIFO Data register)
(W BYTE)

This byte contains one character for transfer through
the transmit FIFO. After a write-byte action to this
register, FIFODATA <7:0> is transferred to the
transmit FIFO.
The least-significant
FIFODATA bit 0.

bit

the

character

3.2.2.9 Line-Control Register (LNCTRL) — The main function of this register is to control the line
interface.
LNCTRL (BASE + 10)
15

R/W

R’W

R'W |RW | R'W |

W | R'W| R'W |

W |R/W | VYW

L
RTS

DTR

MAINTENANCE |
MODE
LINK
TYPE

OAUTO

FORCE.
XOFF

RX
ENABLE

BREAK

X
ABORT

IAUTO

RE2442

Bit

Name

Description

RTS
(Request To Send) (R/W)

This bit controls the Request To Send (RTS) signal.

1
0

DTR
(Data Terminal Ready) (R/W)

ON
OFF

This bit controls the Data Terminal Ready (DTR) signal.

3-15

Bit

Name

Description

ON
OFF

LINK.TYPE
(Link Type) (R/W)

This bit must be set if the chiannel is to be connected to a
modem. When the bit is set, any change in modem status
will be reported through the receive FIFO as well as the
STAT register.
If this bit is cleared, this channel becomes a
‘data-leads-only’ channel. Modem status information is
loaded in the high byte of STAT, but is not placed in the
receive FIFO.

<7:6>

MAINT
(Maintenance Mode) (R/W)

These bits can be written by the driver or test programs, in
order to test the channel.
‘
The coding is as follows:
00 =

Normal operation

Automatic echo mode — Received data is

looped back to the terminal (regardless of the
state of TX.ENA) at the data rate selected for
the receiver The received characters are
processed normally and placed in the receive
FIFO. Any data that the host attempts to
transmit on this channel will be discarded by
the OCTART. The RX.ENA bit must be set
when operating in this mode.
10

Local loopback -— Data transmitted by the
host is looped back to the receive buffer. Data
received from the terminal is ignored, and the
transmit data line to the terminal is held in the
mark condition. The data rate selected for the
transmitter is used for both transmission and
reception. The TX.ENA bit still controls
transmission in this mode. The RX.ENA bit is
ignored.

11 =

Remote loopback — In this mode, data
received from the terminal is looped back to the
terminal at a clock rate equal to the received
clock rate. The data is not placed in the receive
FIFO. The state of TX.ENA 1is ignored. The
RX.ENA bit must be set on this channel.

3-16

Bit

Name

Description

FORCE.XOFF
(Force XOFF) (R/W)

This bit can be set by the program to indicate that this
channel is congested at the host system (for example, if the
typeahead buffer is full). When it sees this bit set, the
DHQ11 will send an XOFF code. Until the bit is cleared,
XOFFs will be sent after every alternate character received
on this channel. When the bit is cleared, an XON will be
sent unless IAUTO is set and the receive FIFO is critical.

OAUTO
(Outgoing Auto Flow) (R/W)

This bit is the auto-flow control bit for outgoing
characters. When set, if RX.ENA is also set, the DHQ11
will automatically respond to XON and XOFF codes
received from a channel. The DHQI11 uses the TX.ENA
bit in TBUFFAD2 to stop and start the flow. If
DISAB.XRPT is also set, XON/XOFF codes are not
entered in the receive FIFO.

BREAK
(Break Control) (R/W)

If set, this bit forces the transmitter of this channel to the
spacing state.
If this bit is set while a character is being transmitted,
transmission is completed before break is asserted on the
line.
Transmission 1s re-enabled when the bit 1s cleared.

NOTE
If the line is idle, there may be a delay of up to 170
microseconds between writing the bit and the channel
changing state. If a character is already being
transmitted by the OCTART, the BREAK signal will
be transmitted immediately afterwards.
RX.ENA
(Receiver Enable) (R/W)

If this bit is sét, this receiver channel is enabled.
If this bit is cleared when this channel is assembling a
character, that character is lost.
The bit 1s cleared by MASTER.RESET.

IAUTO
(Incoming Auto Flow) (R/W)

This is the auto-flow control bit for incoming characters.
If it is set, the DHQ11 will control incoming characters by
transmitting XON and XOFF codes.

3-17

Bit

Name

Description

If the receive FIFO becomes more than three-quarters full,
the DHQI11 will send an XOFF code to that channel, and
to any other channel which receives a character and has
the IAUTO bit set. When FIFO becomes less than half
full, an XON will be sent to all channels which had
previously been sent an XOFF.
0

TX.ABORT
(Transmit Abort) (R/W)

This bit is set by the driver program to halt data
transmission. If a DMA transfer was in progress, the
DMA address and count registers (TBUFFADI,
TBUFFAD?2, and TBUFFCT) will be updated to reflect
the number of characters which have been transmitted.
The transfer can be continued by clearing TX.ABORT,
and then setting TX.DMA.START in TBUFFAD2. No
characters will be lost.

If DMA is not in progress, the following actions will occur
DHV11 mode — no action

DHU11 mode — characters in the transmit FIFO will
be discarded. Because of bufiering, up to two characters
could be transmitted after the TX.ABORT bit is set. The
host cannot determine exactly how many characters have
been lost with this operation.

When an abort sequence has been completed, the DHQ11
will set the TX.ACTION bit in the CSR. If the transmitter
interrupt is enabled, the program will be interrupted at the
transmit vector.

The program must make sure that TX.ABORT is clear
before setting TX.DMA.START, otherwise the transfer
will be aborted before any characters are transmitted.
The bit is cleared by MASTER.RESET.

3-18

3.2.2.10

Transmit Buffer Address Register Number 1 (TBUFFADI1) -

TBUFFAD1 (BASE + 12)

R'W |R/W | R“W |

W |R'W | R“W [ R“W | RW |RW |R'W | R'W |[R'W |RW {R'W |

W | R/ W

TXMIT DMA ADDRESS

(BITS O TO 15)

Bit

Name

Description

<15:0>

TBUFFAD<15:0>

Bits <15:0> of the DMA address.

(Transmit Buffer Address [Low])

(R/W)
3.2.2.11

Transmit Buffer Address Register Number 2 (TBUFFAD2) —

TBUFFAD2 (BASE + 14)

R’W

R/W

TXMIT

DMA

ENABLE

START

R'W|R/W|RW

R/V\,/A R/'W}]

R/'W

TXMIT DMA ADDRESS
(BITS16 TO 21)

Bit

Name

Description |

TX.ENA
(Transmitter Enable) (R/W)

When this bit is set, the DHQI11 will transmit all
characters.

When this bit is cleared, the DHQI11 will only
transmit internally generated flow-control characters.
The bit is set by MASTER.RESET.
In the OAUTO mode, this bit is used by the DHQI11
to control outgoing characters.

3-19

Bit

Name

TX.DMA.START

This bit is set by the host to start a DMA transfer.

(Transmit DMA Start) (R/W)

The

Description

DHQI1

will clear the bit before returning

TX.ACTION.
The bit is cleared by MASTER.RESET.

NOTE
After setting this bit, the host must not write to
TBUFFCT, TBUFFADI1, or TBUFFAD2 <7:0>
until the TX.ACTION report has been returned.
<5:.0>

TBUFFAD<21:16>

Bits <21:16> of the DMA address. Before a DMA
transfer;,
TBUFFAD1
and the low byte of
TBUFFAD? are loaded with the start address of the

(Transmit Buffer Address [High])
(R/W)

DMA buffer. This address will be continuously
changing during a DMA transfer and has no
meaning. Once TX.ACTION has been returned, the
register contains the final DMA transfer address.
3.2.2.12

Transmit DMA Buffer Counter (TBUFFCT) —

TBUFFCT (BASE + 16)
15

RW |RW|RW|[RWIRW]|RW|RWIRW]|RWI|RW|RW]|RW|RW|RW|RW|
RW

SN S

]

DMA CHARACTER COUNT
(WHEN VALID HOLDS NO. OF CHARS STILL TO BE SENT)
RDY179

Bit

Name

Description

<15:0>

TX.CHAR.CT

This .word is loaded with the number of characters to

(Transmit Character Count) (R/W)

be transferred by DMA.

The number of characters is specified as a 16-bit
unsigned integer.

3-20

Bit

Name

Description
After a DMA transfer has been aborted, this location
will hold the number of characters still to be
transferred.
See also the previous NOTE.

3-21

3.3

PROGRAMMING FEATURES

3.3.1

Initialization
The DHQI11 is initialized by its on-board sequencers.

Initialization

takes

place

after

bus

reset

sequence,

when

the

host

sets

CSR<5>

(MASTER.RESET).

Before starting initialization, the on-board sequencers perform a self-test. The results of this test are
reported by eight diagnostic bytes in the receive FIFO.

The DHQI11 state, after a successful self-test, is as follows.

Eight diagnostic codes are placed in the receive FIFO

The diagnostic fail bit (CSR<13>) is clear

All channels are set for:
a.

Send and receive 9600 bits/s

Eight data bits

One stop bit

No parity

Parity odd

Auto-flow off

Receive disabled

Transmit enabled

No break on line

No loopback

Link type set to data-leads-only

DTR and RTS off

DMA character counter zero

DMA start address registers zero

TX.DMA.START cleared

TX.ABORT cleared

Auto-flow reports enabled

3-22

The DHQI11

clears the MASTER.RESET bit (CSR < 5> ) when initialization and self-test are complete.

3.3.2 Configuration
After DHQI11 self-initialization, the driver program can configure the DHQI11 as needed.
This is done
through the LPR and LNCTRL registers.
The line characteristics for a channel can be set up by writing to the LPR and LNCTRL
registers
associated with this channel. These are:
®

Transmit speed

Receive speed

Number of stop bits

Parity type or parity disabled

Character length

Flow-control characteristics

Normal or maintenance mode

Receiver enable/disable

Modem or data-leads-only

NOTE

If RX.ENA is reset while a received character is being
assembled, that character will be lost.

3.3.3 Transmitting
Each DHQI11 channel can be set up to transfer the characters by DMA or under program control.
3.3.3.1
DMA Transfers — Before setting up the transfer of a DMA buffer, the program should make
sure that TX.DMA.START is not set. TBUFFCT, TBUFFADI, and TBUFFAD2 should not be
written unless TX.DMA.START is clear.

Transmission will start when the program sets TX.DMA.START. The size of the DMA buffer, and its
start address, can be written to TBUFFCT, TBUFFADI, and TBUFFAD2 in any order, provided that
the TX.DMA start bit (TBUFFAD2<7>) is not set. However, TBUFFAD2 contains TX.ENA and
TX.DMA.START, so it is probably simpler to writt TBUFFAD2 last. By using byte operations on this
register, TX.ENA and TX.DMA.START can be separated.

The DHQI11 will perform the transfer, and set TX.ACTION when it is complete. If TXIE is set, the

program will be interrupted

the transmit vector.

Otherwise, TX.ACTION must be polled.

TX.ACTION is not returned until the UART has completely transmitted the last character of the DMA
buffer.

3-23

To abort a DMA transfer, the program must set TX.ABORT. The DHQI | will stop transmission, and
update TBUFFCT, TBUFFADI, and TBUFFAD2
< 7:0> to reflect the number of characters which
have been transmitted. TX.DMA.START will be cleared. If TXIE is set, TX.ACTION will interrupt the
program at the transmit vector. If the program clears TX.ABORT and sets TX.DMA.START, the
transfer can be continued without loss of characters.
If a DMA transfer fails because of a host memory error, the transrmission will be terminated.
TBUFFADI1 and TBUFFAD?2 will point to the failing location. TBUFFCT will be cleared.
3.3.3.2

Programmed I/O (DHV11 Mode) — Single characters are transferred through the channel
TX.CHAR register. The character and the DATA.VALID bit must be written as defined in Section
3.2.2.3. Note that the character and the DATA.VALID bit can be written by separate MOVB
instructions.

When the DHQI11 removes the character from TX.CHAR, it returns TX.ACTION. This will generate
an interrupt if TXIE is set.
NOTE
In single-character
mode, TX.ACTION is returned
when the DHQ11 accepts the character, not when it
has been transmitted. Each channel can buffer up to
three characters. Therefore, if line parameters are
changed immediately after the last TX.ACTION of a
message, the end of the message could be lost unless
three null characters are added to the end of each
single-character programmed transfer message.

3.3.3.3 Programmed I/O (DHU11 Mode) — Before writing a character or sequence of characters to
the FIFODATA register, the program should read the FIFOSIZE register to check that there is space in
the transmit FIFO.
If there is enough space, characters can be written as bytes (one character) or words (two characters) to
FIFODATA. After a low—byte write, FIFODATA <7:0> is transferred to the FIFO. After a word
write, FIFODATA < 7:0> is transferred to the FIFO, followed by FIFODATA < 15:0>. High-byte
writes to FIFODATA are not allowed.

The DHQI11 returns TX.ACTION when the transmit FIFO becomes empty. An interrupt will also be
generated if TXIE is set. As distinct from DMA mode, in programmed I/O mode TX.ACTION is
returned when the DHQI11 transfers the last character from the transmit FIFO to the OCTART, not
when it has been transmitted. Thus, if line parameters are changed immediately after the last
TX.ACTION of a message, the end of the message could be lost. The program can avoid this loss by
adding two null characters to the end of each programmed transfer FIFO message.
3.3.4

Receiving

Received characters, tagged with the channel number, error information and DATA.VALID, are placed
in the receive FIFO. RX.DATA.AVAIL is clear when the receive FIFO is empty. When a character is put
into the empty receive FIFO, the DHQI11 sets RX.DATA.AVAIL. A receive interrupt is generated if
RXIE is set. RX.DATA.AVAIL stays set while there is valid data in the receive FIFO. It is recommended
that the receive character routine continues to read characters from the receive FIFO until
DATA.VALID is clear.

3-24

NOTE
The interrupt is dynamic. It is raised as
RX.DATA.AVAIL is set after RXIE, or as RXIE is
set after RX.DATA.AVAIL. If the interrupt routine
does not empty the receive FIFO, RXIE must be
toggled to raise another interrupt. In DHU11 mode,

the interrupt is generated after a delay (set by

RX.TIMER).

If RXIE is not set, the program must poll RBUF often enough to prevent data loss.
3.3.5

Interrupt Control
The DHQI11 provides one of two vector addresses during a bus interrupt sequence. The receive vector
address is the address set up on the vector address switches. The transmit vector address is the receive
vector address + 4.

The receive interrupt vector is generated when:
®

RXIE is set and a character is placed into an empty receive FIFO

RXIE is changed from 0 to 1, and the receive FIFO contains one or more characters.

NOTE
In DHU11 meode an interrupt is generated either
immediately, or after the delay set by RX.TIMER.
The transmit interrupt vector is generated when:
®

TXIE is set and TX.ACTION becomes set

TXIE is changed from 0 to 1 while TX.ACTION is set
NOTE

Up to 16 TX.ACTION reports are buffered. It is
therefore recommended that your program reads the
CSR until the TX.ACTION bit becomes clear,
otherwise TX.ACTION will be lost.
At the two vectors, the host must provide the addresses of suitable routines to deal with the above
conditions.
In DHU11 mode, an interrupt is generated either immediately data is put into an empty receive FIFO,
or after a delay set by RX. TIMER.
3.3.6 Auto XON And XOFF
XON and XOFF characters are commonly used to control data flow on communications channels. To
use this facility, interfaces must have suitable decoding hardware or software.

A channel using flow control that receives an XOFF

stops sending characters until it receives an XON.

3-25

If the receive FIFO becomes more than three-quarters full, the DHQ11 will send an XOFF code to that
channel, and to any other channel which receives a character and has the IAUTO bit set. When FIFO
becomes less than half full, an XON will be sent to all channels which had previously been sent an
XOFF.
The DHQI11 automatically controls character flow when programmed accordingly (auto-flow). Four
bits control this function:
®

JAUTO

—

LNCTRL< 1>

FORCE.XOFF

—

LNCTRL<S5>

OAUTO

—

LNCTRL<4>

DISAB.XRPT

—

LPR<0>

IAUTO and FORCE.XOFF both control incoming characters. IAUTO is an enable bit which allows
the level of the receive FIFO to control the generation of XOFF and XON characters. The
FORCE.XOFF bit is a direct command from the program to control the incomimg data stream.

3.3.6.1 JTAUTO - The DHQI11 hardware recognizes when the receive FIFO is three-quarters full and
half full. The logic uses these states for auto-flow control.
Each channel has a separate IAUTO bit. If there are 191 or more characters in the receive FIFO, and a
character is received on a channel with IAUTO set, an XOFF character is sent. If the channel does not
respond to the XOFF, the DHQI11 will send another XOFF in response to every alternate character
received. An XON will be sent when the receive FIFO contains less than 128 characters, unless the
FORCE.XOFF bit for that channel is set. XONs are only sent to channels to which an XOFF has
previously been sent.

By inserting XON and XOFF characters into the data stream, the program can perfc'>rm flow control

directly. However, if the DHQI11 is in JAUTO mode, the results will be unpredictable.

In IAUTO mode, if RX.ENA 1i1s set, XON and XOFF characters will be transmitted even if TX.ENA is
cleared.

3.3.6.2 FORCE.XOFF - When FORCE.XOFF is set, the DHQ11 sends an XOFF and then acts as if
IAUTO is set and the receive FIFO is critical (was three-quarters full, and is not yet less than half full).
When FORCE.XOFF is reset, an XON will be sent unless the receive FIFO is critical and IAUTO is set.
3.3.6.3 OAUTO - Ifthe program sets OAUTO, the DHQI11 will automatically respond to XON and
XOFF characters from the channel. It does this by clearing or setting the TX.ENA bit.
The program may also control the TX.ENA bit, so in this case it is important to keep track of received
XON and XOFF characters.
Received XON and XOFF characters will always be reported through the receive FIFO, unless the
DISAB.XRPT bit is set. It is possible, during read-modify-write operations by the program, for the
DHQI11 to change the TX.ENA bit between the read and the write actions. For this reason, if DMA
transfers are started while OAUTO is set, it is advisable to write to the low byte of TBUFFAD?2 only.

3-26

3.3.6.4 DISAB.XRPT - If DISAB.XRPT is clear, XON and XOFF characters will be processed as
normal characters and are entered into the receive FIFO. DISAB.XRPT allows the individual line

OAUTO bits to control whether XON or XOFF characters received on that channel are discarded.
When DISAB.XRPT is set and OAUTO is set, this filtering is enabled.
NOTES

'When checking for flow-control characters, the
DHQI11 only checks characters which do not
contain transmission errors. The parity bit is
stripped, and the remaining bits are checked for
XON (21;) and XOFF (23;) codes.
Auto flow-control does not absolutely guarantee
that overrun errors will not occur. These errors

may still occur if the transmitting devices do not
respond to the XOFF immediately.

3.3.7 Error Indication
Four bits inform the program of transmission and reception errors.
e

TXDMA.ERR

—

CSR<I12>,

PARITY.ERR

—

RBUF<12>.

FRAME.ERR

—

RBUF<13>.

OVERRUN.ERR

—

RBUF<14>.

RBUF < 14:12> also identify a diagnostic or modem status code.
3.3.8 Modem Control
Each channel of the module provides modem control bits for RTS and DTR. Also on each channel are
modem status inputs CTS, DSR, RI, and DCD. See Section 3.2.2.6 for a description of each of these
signals.

CTS, DSR, and DCD are sampled every 10 ms. Therefore, for a change to be detected, these bits must
stay steady for at least 10 ms. Rl is also sampled every 10 ms, but a change is not reported unless the new
state is held for three consecutive samples. Modem signals must be coordinated under program control;
there is no hardware modem control logic. Modem status change reports are placed in the receive FiFO
only if LINK.TYPE is set, but any changes are updated in STAT irrespective of the state of
LINK.TYPE.
Appendix A gives more details of modem control.
By clearing LINK.TYPE, a channel is selected as a ‘data-lines only’ channel. Modem control and status
bits can still be managed by the program, but status bits must be polled at the line-status register.
Changes of modem status will not be reported to the program.

3-27

Status change reporting is done through the receive FIFO as follows.
®

When OVERRUN.ERR,

FRAME.ERR, and PARITY.ERR are all set, the eight low-order
bits contain either status change or diagnostic information. In this case:

If RBUF<0>

If RBUF<0> = 1, RBUF<7:1> holds diagnostic information (see Section 3.3.10).

= 0, RBUF<7:1> holds STAT <15:9> (see Section 3.2.2.6)

3.3.9 Maintenance Programming
The host can set bits 7 and 6 of LNCTRL to allow each channel to be configured in normal, automatic
echo, local loopback, and remote loopback modes. These modes allow an individual data channel to be

looped back to the host, or to be looped back to the terminal to assist in isolating communication
problems.
The host must provide suitable software to use these modes.
3.3.10

Diagnostic Codes

3.3.10.1
Self-Test Diagnostic Codes — After bus reset or master reset, the DHQ11 executes a self-test
and initialization sequence. During the sequence, eight diagnostic codes are put in the receive FIFO, and

RX.DATA.AVAIL is set.
After an error-free test, DIAG.FAIL will be reset and the ‘diagnostic passed’ LED will be on. If an error
1s detected, DIAG.FAIL will be set and the LED will be off.
3.3.10.2 Interpretation Of Self-Test Codes — The high byte of diagnostic codes in RBUF can be
interpreted as in Section 3.2.2.2, except that bits <11:8> are not the line number. They indicate the
sequence of the diagnostic byte, that is to say, 0 = first byte, 1 = second byte, and so on. Table 3-3 shows
the meaning of each of the error codes.
Table 3-4

DHQ11 Self-Test Error Codes

C:de
(O+:tal)
bits :7:0>

Explanation

201 |

Self-test null code (used as a filler)

203

Self-test skipped

211

OCTART error

225

RAM error

231

RTS-CTS-DCD error

235

DTR-RI-DSR error

All other errcr codes should be treated as an undefined error.
If bit 7 = 0 ad bit 0 = 1, then bits <5:2> contain circuit revision information.

3-28

Table 3-4
Code

DHQI11 Self-Test Error Codes (Cont.)

Explanation

(Octal)
bits <7:0>

Bit 6 always reads 1 for the DHQI1, and indicates that the circuit contains control and OCTART
chips.

Bit 1 indicates to which chip the information refers: 0 = Control, 1 = OCTART.

After self-test, the eight FIFO codes consist of six diagnostic codes and two circuit revision codes. If
there are less than six errors to report, null codes (201(octal)) fill the unused places.

After an error-free test, six null codes and two circuit revision codes will be returned.
~ Self-test may be ‘skipped’ to shorten the initialization cycle (see Section 3.3.10.3).

The module is still tested, even if self-test is skipped. The reset delay is much shorter, but test coverage is
not affected; therefore skipping self-test is advantageous.

After ‘skip self-test’ self-test, the eight FIFO codes consist of six diagnostic codes and two circuit
revision codes. If there are less than six errors to report, 203(octal) codes fill the unused places.
After an error-free test, six 203(octal) codes and two circuit revision codes will be returned.

3.3.10.3 Skipping Self-Test -~ In DHU11 mode only, the method is to set SKIP (CSR bit 4) and
MASTER.RESET (CSR bit 5) simultaneously, that is, write 60(octal) to the base CSR. SKIP must not
be cleared until at least 20 microseconds after it was set. SKIP must be cleared by the host so that the
master reset sequence can complete.

In DHV11 mode (this also works in DHU11 mode, but the previous method is preferred) the following

method is used:

The program resets the DHQI11.

The program waits 10 ms (+ 1 ms) after issuing reset, and then attempts to write 0525254 to

Following self-test, the DHQ11 hardware checks whether an attempt was made to write the
skip code to the registers during the 4 ms window after reset (see step 2 above). If an attempt
was made, the MASTER.RESET bit is cleared at 30 ms after issuing a reset instead of 1.2 s.

any of the control registers, except the CSR, within the next 4 ms.

The 1.2 s reset time was retained for compatibility with the DHVII.
NOTE

The program must not write to the CSR, or to the
control registers, during the period starting 15 ms
after reset, and ending when the MASTER.RESET
bit is cleared. Writing during this period could cause a
diagnostic fail condition.

3-29

3.3.10.4 Background Monitor Program (BMP) - The DHQI1 BMP logic performs background
self-tests by checking for OCTART interrupts. One of two codes is returned to the receive FIFO:
1.

305(octal) — DHQI11 running

307(octal) — DHQI11 defective (also LED off)

A single diagnostic word is returned to the receive FIFO. The low byte contains the diagnostic code. In
the high byte, OVERRUN.ERR, FRAME.ERR, and PARITY.ERR are all set to indicate that
bits <7:0> do not hold a normal character. The line number (RBUF<11:8>) = 0.
BMP normally only reports when it finds an error. However, the program can get a BMP report at any
time to check the DHQI11. This is done by setting DIAG (LPR <2:1>) of any channe] to 01.The line
number returned is that of the LPR used to request the report.

On completing the check, BMP clears this 01 code. The host should not write to the LPR of that channel
until LPR <2:1> becomes 00.

3-30

3.4
PROGRAMMING EXAMPLES
These programs are not presented as the only way of driving the option, and are neither guaranteed nor
supported.
3.4.1

Resetting The DHQI11
In the following example:
®

DIAGC is a routine to check the diagnostic codes. It returns with CARRY set if it detects an
error code.

The loop at 13 takes 1.2 seconds, so the programmer could poll through a timer or poll at
interrupt level zero.

; A ROUTINE TO RESET THE DHQii AND CHECK THAT IT IS FUNCTIONING
; CORRECTLY.
.

DHQARES:

1%:

#40,%DHQCSR

; SET MASTER.RESET AND

BIT

#40 ,#DHQCSR

; CLEAR INTERRUPT ENABLES.
; WAIT FOR MASTER.RESET TO

BNE
BIT
BNE

1%
820000 ,#DHACSR
DIAGER

; CLEAR.
; CHECK THE DIAGNOSTICS
; FAIL BIT.

MOV

#8.,R5

;
;
;
;

MOV
JSR
BCS

sRBUFF ,RO
PC,DIAG
DIAGER

SOB

R5,2%

; BEEN AN ERROR.
; GO BACK FOR NEXT CODE.

RTS

; RETURN - CARD IS RESET.

NOTE: TEST INSTRUCTION IS
OK BECAUSE THERE ARE
NO TRANSMIT.ACTS PENDING.
SET UP A COUNT.

; GET NEXT DIAGNOSTIC CODE.
; PROCESS IT.
; CARRY SET - MUST HAVE

DHQ11 HAS FAILED TO RESET PROPERLY, SO HALT AND WAIT FOR
THE FIELD SERVICE ENGINEER.

“ar

“s

2$:

MOV

DIAGER:

HALT
BR

DIAGER

3-31

3.4.2 Configuration
This routine.sets the characteristics of channel 1 as follows:
1.

Transmit and receive at 300 bits/s

Seven data bits with even parity and one stop bit

Transmitters and receivers enabled

No modem control |

No automatic flow control.

SETUP::

MOV

81 ,#DHQACSR

MOV

#052560,8LPR

MOV
MOVB

#4 ,8LNCTRL
#200,#TBFAD2+1

RTS

; LOAD INDEX REG
; WITH CHANNEL NO.
; DATA RATE, STOP BITS,
; PARITY AND LENGTH.
; ENABLE THE RECEIVER.
; ENABLE THE TRANSMITTER.

; RETURN - CHANNEL 1 DONE.

3-32

3.4.3

Transmitting

3.4.3.1 Single-Character Programmed Transfer (DHU11 Mode) — The following is a program
a message on channel 1.

to send

The CSR is polied for TX.ACTION reports, but 2 TX.ACTION interrupt could also be used.
Otherwise it would lose
DHQI11 with only this channel active.
This program would function on als.
too big to
TX.ACTION reports of other channe However, a program to control all channels would be
A ROUTINE TO WRITE A MESSAGE TO CHANNEL i USING FIFO OuTPUT

MODE (PROGRAMMED TRANSFERS).

use as an example.

FIFOUT::

i$:

MOV

#1 ,8DHACSR

; POINT TO CHANNEL WE WISH

MOV
MOV

#MESG,RO
MESIZE,RL

; POINT TO MESSAGE.
; PUT COUNT IN.

TSTE

sFIFOSIZE

; TO TALK TO.

SOB

Ri,1$

; CHECK THAT THERE 1S SPACE IN
; THE FIFO.
; MOVE CHARACTER TO TRANSMIT FIFO
; GO BACK FOR NEXT CHARACTER.

MOV

#DHQCSR ,R2

; WAIT FOR TX.ACT.

BIC

#170377 ,R2

BNE

; ISOLATE CHANNEL NUMBER.
; IGNORE THE TX.ACT IF IT IS

RTS

; MESSAGE SENT.

.~MESG

BEQ

MOVB

2%:

BPL

CMP

(RO)+,sFIFODATA

8000400 ,R2

; NOT OURS (SHOULD NOT HAPPEN).

MESG: .ASCII /A TRANSMIT FIFO MESSAGE FOR CHANNEL 1/
MESIZE

.EVEN

3-33

3.4.3.2 Single-Character Programmed Transfer (DHV11
Mode) — This is a program to send a message
on channel 1. The message (MESG) is an ASCII string
with a null character as terminator.

Polling is used, but a

TX. ACTION interrupt could also be used.

This program would function on a DHQI1 with only this
channel active. Otherwise it would lose
TX.ACTION reports of other channels. However, a program
to control all channels would be too big to

use as an example.

’

;

A ROUTINE TO WRITE A MESSAGE TD CHANNEL {
USING SINGLE-CHARACTER

; MODE.

SINGOT::

MOV

#1 , #DHQCSR

MOV

#MESG,RO

MOVB

(RO)+,8TXCHAR

BEQ

MOVB

2200, #TXCHAR+1

MOV
BPL

#DHQCSR,R!
2%

; WAIT FOR TX.ACT

BIC
CMP
BNE

174377 ,R1
*000400,R1

;

RTS

TXI

; POINT TO MESSAGE.

; MOVE CHARACTER TO TRANSMIT
; BUFFER.
; GO RETURN IF ALL CHARACTERS
; GONE.
; SET DATA VALID BIT TO START.

ISOLATE CHANNEL NUMBER.

; IGNORE THE TX.ACT IF IT IS
NOT OURS (SHOULD NOT HAPPEN).
; 60 BACK FOR NEXT CHARACTER.
“~a

1%:

; LOAD INDEX REG WITH
; CHANNEL NO.

3%:

MESG:

; MESSAGE SENT.

.ASCIZ /A SINGLE-CHARACTER MESSAGE FOR CHANNEL 1/

3-34

3.4.3.3

DMA Transfer -

; THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE DH@i{ AND
; HALTS THE MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED.

; THE MESSAGES ARE TRANSMITTED USING DMA MODE, AND INTERRUPTS ARE

; USED TO SIGNAL TRANSMISSION COMPLETION.
.

DMAINT::

MOV
MOV
MOV
CLR

. 8TXINT,8#TXVECT
8200, 8TXPSW
8. ,R0
Ri

; SET UP THE INTERRUPT VECTORS.
; INTERRUPT PRIORITY FOUR.
; EIGHT LINES TO START.
; START AT LINE ZERO.

MOVB
MOV
MOV
MOV

Ri,sDHQCSR
#DMASIZ,sTBFCNT
sDMAMES ,#TBFADY
#100200,8sTBFAD2

INC
SOB

R4
RO,1$

SELECT THE REGISTER BANK.
SET LENGTH OF MESSAGE.
SET LOWER 16 ADDRESS BITS.
START DMA WITH TRANSMITTER
; ENABLED (ASSUME UPPER ADDRESS
; BITS ARE ZERD).
; POINT TO NEXT CHANNEL.
; REPEAT FOR ALL LINES.

CLR
MOVB

RS
#100,8DHOCSR+1

; R5 IS USED BY INTERRUPT ROUTINE.
; ENABLE TRANSMITTER INTERRUPTS.

; WAIT FOR ALL LINES TO 'FINISH.

1%:

;
;
;
;

2%:

CMP

8. ,R5

BNE

HALT
BR

3$:

TRANSMITTER INTERRUPT ROUTINE.

RS IS INCREMENTED AS EACH LINE COMPLETES.

; ALL DONE, SO STOP.

TXINT::

MOV
BIT
BEQ

#DHBCSR,R0 ; GET LINE NUMBER OF FINISHED LINE.
#400000,
R0 ; CHECK FOR (ANOTHER) TX.ACTION.
44
; IF NOT, GO RETURN AND WAIT.

INC

TXINT

; FLAG THAT ANOTHER LINE HAS FINISHED.

4%
:

RTI
bs$:

HALT

; MEMORY PROBLEM

DMAMES:

.ASCII

(15)(12)(7)(7>{7)>/SYSTEM CLOSING DOWN NOW/

DMASIZ

=
.EVEN

.~DMAMES

3-35

3.4.3.4

Aborting A Transmission —

FIFO)
IN
PROGRESS
ON A SPECIFIED LINE.
THIS ROUTINE MAKES THE
(RATHER RASH) ASSUMPTION THAT THERE ARE
NO OTHER TRANSFERS
IN
PROGRESS.

ON ENTRY,

RO CONTAINS THE NUMBER OF THE LINE TO BE ABORTED.

; THIS ROUTINE IS CALLED TO ABORT A TRANSMISSION (EITHER DMA OR

TXABRT::

MOV
BIS

RO,#DHQCSR
81 ,8LNCTRL

; POINT TO THE CHANNEL TO BE ABORTED.
; SET THE TRANSMIT ABORT BIT.

MOV
BPL
SWAB
BIC
CMP
BNE

#DHRCSR,R1
1%
Ri
#177760,R1
RO,R1
is

; WAIT FOR THE TX.ACT.

i%:

; CHECK IT IS OUR LINE.

; IGNORE IT IF IT IS NOT (OUR

; ASSUMPTION WAS WRONG!)
BIC

1,8LNCTRL

; CLEAR DOWN THE ABORT FLAG

; FOR NEXT TIME.
RTS

; BUFFER COMPLETELY ABORTED.

; IF A DMA WAS IN PROGRESS, THE
; DMA REGISTERS REFLECT WHERE

; THE DHO4{ HAD GOT TO.

3-36

Receiving

INTERRUPT
THIS ROUTINE PROCESSES RECEIVED CHARACTERS UNDER
THE TRANSMITTER FOR THAT
IF AN XOFF IS RECEIVED,
CONTROL.
THE TRANSMITTER
CHANNEL IS TURNED OFF. IF AN XON IS RECEIVED,
IS TURNED BACK ON.

ALL OTHER CHARACTERS ARE IGNORED.

THIS IS JUST AN EXAMPLE.

A BETTER WAY TO PERFORM FLOW CONTROL IS

TO USE THE AUTOMATIC CAPABILITIES OF THE DHGii.

3.4.4

RXAUTO:.

1%:

MOV
MOV
MOV
CLR

#RXINT,8RXVECT
#200, sRXPSH
8. ,R0
R1

; SET UP THE INTERRUPT VECTORS.
; INTERRUPT PRIORITY FOUR.
; ENABLE ALL THE RECEIVERS,
;: STARTING AT CHANNEL ZERO,

MOVB
BIS
INC

R1,#DHQCSR
s4 ,sLNCTRL

; SELECT THE LINE.
; ENABLE THIS RECEIVER.

; SET POINTER TO NEXT CHANNEL.

SOB

RO,1%

MOVE

#100,*DHACSR

; ENABLE THE RECEIVER INTERRUPTS.

RTS

; RETURN - INTERRUPTS DO THE RESET.

3-37

; INTERRUPT ROUTINE TO DO THE MAIN TASK.
RXINT::

MOV
RXNXTC:

RO,-(SP)

MOV
BPL
MOV
BIC

#107777,(SP)+

BNE

RXNXTC

#RBUFF ,RO

RXIEND

;

GET THE CHARACTER.
IF NO DATA VALID, WE HAVE FINISHED.
CHECK FOR ERRORS, MODEM AND
4
]

RO,-(SP)

DIAGNOSTICS CODES.
- JUST IGNORE THEM (BAD PRACTICE).

I4
N

BIC

#170200,R0

SWAB

BIS
MOVB
SWAB
CMPB
BNE

#100,R0
RO, #DHACSR
RO

#21,R0
1%

BISB
BR

RXNXTC

CMPB
BNE

#23,R0
RXNXTC

BICB
BR

RXNXTC

MOV

(SP)+,R0

i%:

SAVE CALLER’S REGISTERS.

REMOVE UNNECESSARY BITS.
’
; POINT TO THIS CHARACTER’S LINE.
; (ADD THE INTERRUPT ENABLE BIT.)
-

; PUT CHARACTER BACK IN LOWER BYTE.
WAS IT AN °"XON"?
I 4
; NO - GO CHECK FOR AN "XOFF"
r
]

#200,#TBFAD2+1

;

WAS IT AN "XOFF"?
NO - GO CHECK FOR MORE CHARACTERS.

14
-

#200,#TBFAD2+1

;
-

ENABLE THE TRANSMITTER.

GO CHECK FOR MORE CHARACTERS.

DISABLE THE TRANSMITTER.

G0 CHECK FOR MORE CHARACTERS.

RXIEND:
RTI

RESTORE THE DESTROYED REGISTER.

3-38

Auto XON And XOFF

THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE DHRii AND
HALTS THE MACHINE WHEN ALL TRANSMISSIONS HAVE COMPLETED.

THE MESSAGES ARE TRANSMITTED USING DMA MODE, AND INTERRUPTS ARE
USED TO SIGNAL TRANSMISSION COMPLETION.

AUTOMATIC FLOW CONTROL
IS ENABLED ON THE OUTGOING DATA.

wEe

WNE

wWE

wNe

3.4.5

TXAUTO::

1%:

MOV
MOV
MOV
CLR

sATOINT,#TXVECT ; SET UP THE INTERRUPT VECTORS.
8200,sTXPSW
; INTERRUPT PRIORITY FOUR.
; EIGHT LINES TO START.
8. ,R0
; START AT LINE ZERO.
Ri

MOVE
BIS

Ri,#DHRCSR
824 ,8LNCTRL

MO¥
MOV
MOV

#AUTOSZ ,#TBFCNT ; SET LENGTH OF MESSAGE.
sAUTOMS ,#TBFAD1 ; SET LOWER 16 ADDRESS BITS.
#100200,8TBFAD2 ; START DMA WITH TRANSMITTER
; ENABLED (ASSUME UPPER ADDRESS

INC
SOB

Ri
RO,1$

; POINT TO NEXT CHANNEL.
: REPEAT FOR ALL LINES.

CLR
MOVB

R5
£#100,8DHACSR+1

: RS IS USED BY INTERRUPT ROUTINE.
; ENABLE TRANSMITTER INTERRUPTS.

CMP
BNE

#8.,R5
2%

: WAIT FOR ALL LINES TO FINISH.
.

; SELECT THE REGISTER BANK.
: ENABLE AUTOMATIC FLOW CONTROL
; ON THE TRANSMITTED DATA.

; BITS ARE ZERO).

2%:

3%:

HALT
BR

; ALL DONE, SO STOP.
3%

3-39

; TRANSMITTER INTERRUPT ROUTINE.
; RS IS INCREMENTED AS EACH LINE COMPLETES.
-

ATOINT::

MOV

#DHACSR,RO

; GET LINE NUMBER OF FINISHED LINE.

BIT
BNE

210000 ,R0
4%

; CHECK FOR DMA FAILURE.
; GO HALT - MEMORY PROBLENM.

INC

; FLAG THAT ANOTHER LINE HAS FINISHED.

2%:
RTI
4%:

HALT
BR
AUTONMS: .ASCII
AUTOSZ
=

;

MEMORY PROBLEM

43
(15> <12)(7>(7><(7)>/SYSTEM CLOSING DOWN NOW/
.—AUTOMS

.EVEN

3-40

Checking Diagnostic Codes

THIS ROUTINE CHECKS THE
DIAGNOSTICS CODES RETURNED FROM THE
DHA@11i.
ON
ENTRY,
RO CONTAINS THE CHARACTER RECEIVED FROM THE
DHE@11.
ON EXIT,
THE CARRY BIT WILL BE CLEAR FOR
SUCCESS,
SET
FOR FAILURE.

wWE

3.4.6

DIAG::

MOV

RO,-(SP)

; SAVE THE CODE FOR LATER.

BIC
CMP
BNE

#107776,R0
#070001 ,R0
DIAGEX

; CHECK THAT IT 1S A DIAG.

; IF NOT, JUST EXIT NORMALLY.

MOV

(SP),RO

; GET THE CODE BACK.

BITB
BEQ

#200,R0
DIAGEX

; CHECK FOR CHIP VERSION NUMBER.

#8201 ,R0

; SELF-TEST NULL CODE.

BEQ
CMPB
BEQ

DIAGEX
#203,R0
DIAGEX

; SELF-TEST SKIPPED CODE.

CMPB
BEQ

#305,R0
DIAGEX

CMPB

CODE.

; DH@ RUNNING CODE.

; ALL THE REST ARE ERROR CODES.
SEC
BR

DIAGXX

; AN ERROR CODE WAS RECEIVED, SO
; SET THE CARRY FLAG.

DIAGEX:

CLC
DIAGXX:

; EVERYTHING OK, SO CLEAR CARRY.

MOV

(SP)+,R0O

RTS

; RESTORE THE CHARACTER/INFO.

3-41

CHAPTER 4
TROUBLESHOOTING
4.1
SCOPE
This chapter explains how to isolate the cause of a communications problem between the DHQ11 and
the equipment to which it is connected.

4.2

PREVENTIVE MAINTENANCE
No preventive maintenance is needed for this option. However, you should always ensure that all cables
are clear of danger, and that all the connectors are secure.

Make sure that all cables are clearly labelled, so that you can easily identify which channel number and
which DHQI11 module are associated with each terminal.
4.3 TROUBLESHOOTING PROCEDURES
Troubleshooting procedures are to identify whether the problem is caused by:
®

The module

A terminal

The cabling and distribution panels.

First decide whether the problem is associated with one channel, a group of four channels, or all eight
channels.

If all channels are faulty, run the user diagnostics to test the module. Also check whether your software
has a driver for the DHQI11.
If a group of four channels are faulty, check the BCO5L-xx cable connected to the module.
For single-channel problems (EIA-232-D):
1.

Check for loose cables and connectors.

Verify that the terminal is working correctly. If necessary, swap it with another one.

When a modem line is suspect, check that the modem is correctly configured for modem
signals supported by the DHQI11. Also check that the software driver has the correct
baud-rate setting and that modem support is enabled for that line.

If the problem cannot be solved, call DIGITAL Field Service.

For single-channel problems (DEC423)
1.

Check for loose cables and connectors.

4-1

Verify that the terminal is working correctly. If necessary, swap it with another one.

Disconnect the BC16C-XX cable from the distribution panel, and connect it to the H3101
loopback connector.
'

Type characters at the terminal connected to the suspect line. If characters are echoed back
when the H3101 is connected, the cables and terminal are working. If characters are not
echoed back, the fault lies with the cable connection to the terminal, or with the terminal
itself.

Rectify the cable or terminal fault, if there is one. If not, make sure that the user diagnostics
for the module run correctly.

If the problem cannot be solved, call DIGITAL Field Service.

H3101 LOOPBACK
CONNECTOR

;

{

___—

[ 44

H3104

TO TERMINALS

BC16C-XX

RE3206

Figure 4-1
4.4

Troubleshooting DEC423 Installations

INTERNAL DIAGNOSTICS

Internal diagnostics run without intervention from the operator. There are two tests: the self-test and the
background monitor program (BMP).
4.4.1

Self-Test

The self-test starts immediately after the Q-bus or module has been reset. It performs a comprehensive
internal logic test but does not test the Q-bus interface. The DIAG.FAIL bit and the ‘diagnostics passed’
LED on the module give an indication of a successful self-test. The self-test also reports error or status
information to the host via the receive FIFO.

The self-test has completed successfully if the LED is on 1.7 seconds after the self-test has been initiated.
The self-test is started by setting the MASTER.RESET bit in the CSR, either by resetting the module
through the program interface or by a Q-bus initialisation sequence. The LED is turned off when the
self-test starts, and the test completes after 30ms. The self-test then finishes in one of three ways:

If skip self-test was used, the LED turns on and the MASTEFL.RESET is cleared
4-2

If the board is in DHV11 mode, the LED flickers, and the end of self-test is delayed for 1.2
seconds to maintain compatibility with DHV11. At the end of the delay period the LED turns
on and the MASTER.RESET is cleared

If the board is in DHU11 mode, the LED flickers, and the end of self-test is delayed for 1.7
seconds to maintain compatibility with DHU11. At the end of the delay period the LED turns
on and the MASTER.RESET is cleared.

In all three cases, if the self-test encounters a failure, the LED will be off after the self-test (and delay) has
completed.
NOTE

The DIAG.FAIL bit controls the LED; when the
DIAG.FAIL bit is set, the LED is off, and when it is
clear, the LED is off.
Self-test provides a high level of confidence that the majority of the module logic is working. The user
diagnostics must also be used to test the Q-bus interface and verify that the switch settings on the module
switchpacks are correct.
4.4.2 Background Monitor Program (BMP)
When the DHQI11 is not doing other tasks, the BMP carries out tests on the module. If an error is
detected, the BMP reports to the host via the FIFO, and also switches OFF the ‘diagnostics passed’
LED.
By writing codes to the line-parameter register, the host can cause the BMP to report the status of the
device, even if an error has not been detected. This facility is used if the host suspects that the option is
faulty. More information on the self-test and BMP diagnostics is given in Chapter 3 of this manual.
4.5

MicroPDP-11 DIAGNOSTICS

4.5.1 User-Mode Diagnostics
These tests can be used by an untrained operator to verify the basic operation of the option. User-mode
tests do not cause any disruption to data networks or devices to which the DHQ11 may be connected.
Such networks and devices do not have to be disconnected from the DHQI11 during the tests. The
MicroPDP-11 system manuals describe how to load and run these diagnostics.
4.5.1.1 Running User-Mode Tests — All user-mode tests are run by selection from the test menu
displayed when the user diagnostics are booted. See Chapter 2 for more details.

A MicroPDP-11 Maintenance Kit is available, which allows trained personnel to run individual
diagnostic programs under the XXDP + diagnostic monitor, and to configure and run DECX11 system
test programs. The XXDP+ functional diagnostic is VHQA**.BIN, and the DECX11 module is
XDHV** OBJ.
4.6 MicroVAX II DIAGNOSTICS
Diagnostics for MicroVAX II systems all run under the MicroVAX Maintenance System (MMS). The
MicroVAX II system manuals describe how to load the MMS into the MicroVAX 11, and how to run
MMS diagnostics. All the tests can be run by selection from the test menus displayed when MMS is
booted.

4-3

4.6.1 User-Mode Tests
These tests can be used by an untrained operator to verify the basic operation of
the option. User-mode
tests do not cause any disruption to data networks or devices to which the
DHQ11 may be connected.
Such networks and devices do not have to be disconnected from the DHQ11
during the tests. See
Chapter 2 for more details.

4.7

FIELD-REPLACEABLE UNITS (FRUs)

The FRUs are:

Reference No.

Item

M3107

Dual-height DHQI11 module

BCOSL-xx

Flat cable, 40 conductor

For EIA-232-D Installations

H3173-A

Distribution panel

For DEC423 Installations

H3100

Active distribution panel

BC16C-25

Multiway cable

H3104

Cable concentrator

70-22775-XX

Power cable

4-5

APPENDIX A
MODEM CONTROL

|
A.1 SCOPE
the programmer and the engineer. It defines control
both
to
useful
This appendix contains information
and warns against likely network faults. A detailed
methods,
control
signals, describes typical modem
example of auto-answer operation is included.
A.2

MODEM CONTROL

The DHQ11 supports sufficient modem control to permit full-duplex operation over the public switched
telephone network (PSTN) and over private telephone lines. Table A-1 lists the control leads supported
by the DHQI11, together with an explanation of their use and purpose. In this appendix, the terms
modem and dataset have the same meaning. They refer to the device which is used to modulate and
demodulate the signals transmitted over the communications circuits.
Table A-1

Name

EIA-232-D

GND

Modem Control Leads

V.24

25-Pin

Definition

102

Signal Ground. This is a reference level
for the data and control signals used at the
line interface.

TXD

103

RXD

104

RTS

105

CTS

106

From DHQI! to modem. This signal

contains the serial bit stream to be
transmitted to the remote station.

From modem to DHQI11. This signal is

the serial bit stream received by the
modem from the remote station.

From DHQIl1-to modem. Causes the

modem’s carrier to be placed on the line.

From modem to DHQI11. Indicates that

the modem has successfully placed its
carrier on the line, and that data presented
on circuit BA will be transmitted to the
communication channel.

DSR

107

From modem to DHQI11. Indicates that

the modem has completed all
and
functions
establishment
to
connected
successfully
communications channel.

call
is
a

Table A-1

Modem Control Leads (Cont.)

Name

EIA-232-D

V.24

25-Pin

Definition

DTR

108/2

From DHQI11 to modem. Indicates to the
modem that the DHQI1 is powered up
and ready to answer an incoming call.

DCD

109

From modem to DHQI11. Indicates to the
DHQI1 that the remote station’s carrier
signal has been detected and is within
appropriate limits.

125

From modem to DHQI11. Indicates that a
new incoming call is being received by the

modem.

The DHQI11 modem control interface can be used in many applicat
ions. These include control of serial
line printers, terminal cluster controllers, and industrial I/O equipme
nt, in addition to the more usual
applications in telephone networks. The use of the control leads
described in Table A-1 is therefore
completely dependent on the application, although there are internati
onal standards which telephone

network applications should obey. There are no hardware interlock
s between the modem control logic
and the transmitter and receiver logic. Program control manages
these actions, as necessary.

A subset of the leads listed in Table A-1 could be used to establish a

connected to the switched telephone network. Ring Indicato

communications link using modems

r (RI), Data Terminal Ready (DTR), and

Data Carrier Detected (DCD) are the absolute minimum requirem
ents. In some countries Dataset
- Ready (DSR) is also needed. It is usually desirable, however, to
implement modem control protocols
which will operate over most telephone systems in the world. Also,
some protection should be included
to guard against network faults, particularly in applications such
as dial-up timesharing systems. Such
faults include:
®

Making a channel permanently busy (hung) because of a misdiale
d connection from a
non-data station

Connecting a new incoming call on an in-use channel. This fault
might occur, for example,
after a temporary carrier loss, if the host system assumed that the carrier
was reasserted by the
original caller.

Modem control with some protection against common faults,
and which is compatible with the
telephone networks in most geographic areas, can be implemented by
using all the signals listed in Table
-1, in the way described by the CCITT V.24 recommendations. Section
A.2.] describes a method of
implementing a full-duplex auto-answer communications link through
modems over the PSTN. It is
provided here only to show the operation and interaction of DHQ11
modem control leads in a typical

application.

A.2.1

Example Of Auto-Answer Modem Control For The PSTN
The system operator determines which DHQ11 channels should be
configured for either local or remote
operation. Local operation implies control of data-leads-only,
while remote operation implies that
modem control will be supported. The host software will assert
DTR and RTS. together with the
LINK.TYPE bit in the LNCTRL register for all DHQI11 channels
configured for remote operation.
DTR informs the modem that the DHQI1 is powered up and ready
to acknowledige control signals from

A-2

the modem. RTS is asserted for the full-duplex mode of operation, and causes the modem to place its
carrier on the telephone line when the modem answers a call. Link Type (LNCTRL<8>) enables
modem status information to be placed in the receive character FIFO, where it will be handled by an
interrupt service routine. Modem status changes are always reported in the STAT register regardless of
the state of LNCTRL <8>. The modem is now prepared to auto-answer an incoming call.

Dialing the modem’s number causes RI to be asserted at the line interface. This informs the DHQI11 that
a new call is being received. RI has to be in a stable state for at least 30 ms, or the change will not be
reported by the DHQ11. Since DTR is already asserted, the modem will auto-answer the incoming call
and start its handshaking sequence with the calling station. The time needed to complete the
handshaking sequence can be in the order of tens of seconds if fallback-mode speed selection and
satellite links are involved. The modem will assert DSR to indicate to the DHQ11 that the call has been
successfully answered and a connection established.

NOTE

On some older types of modem used on the PSTN,
the opposite effect is also true. The RI signal may be
very short, or it may not even occur if DTR was
previously asserted. When this type of modem
answers an incoming call, it asserts DSR almost
immediately and deasserts RI at the line interface.
Programs must therefore expect RI or DSR or DCD
as the first dataset status change received from the
modem when establishing a connection.

As RTS was previously asserted, the modem’s carrier will be placed on the line when DSR is asserted.
When the modem has successfully placed its carrier on the line it will assert CTS. This indicates to the
DHQI11 that it can start to transmit data. If the incoming call is the result of a misdialed number, a
carrier signal may never be received. To guard against this, the host starts a timer when it detects RI or
DSR. This is usually in the range 15 to 40 seconds, within which time the carrier must be detected. When
the modem detects the remote modem’s carrier signal on the line, it will assert DCD. This indicates to
the DHQI1 that data is valid on the RXD line.

The modem can now exchange data between the DHQI11 and the calling station for as long as DCD,
DSR, and CTS stay asserted. If any of these three signals disappears, or if Rl is detected during normal

transmission, a fault condition is indicated. A change of state of any of these signals causes an interrupt

through the receive FIFO.

The handling of the fault conditions now becomes country-specific, since some telephone systems
tolerate a transient carrier loss, while others do not. In the USA it is usual to proceed with a call if carrier
resumes within two seconds. In non-USA areas it is possible for telephone supervisory signals, such as
dial-tone, to be misinterpreted by the modem as a resumption of carrier. In this case the host program
would assume that the connection had been re-established to the original caller and would cause a
‘hung’ channel. To prevent this, DTR should be deasserted immediately after the loss of DCD, CTS, or
DSR, to abort the connection. DTR should stay deasserted for at least two seconds, after which time a
new call could be answered.

APPENDIX B
FLOATING ADDRESSES

B.1 FLOATING DEVICE ADDRESSES
On Q-bus systems a block of addresses in the top 4K words of address space is reserved for options with
floating device addresses. This range is from 177600105 to 17763776s.

Options which can be assigned floating device addresses are listed in Table B-1. This table gives the
sequence of addresses for both UNIBUS and Q-bus options. For example, the address sequences could
be:

DJ11
DHI11

DQIl11

DUI11/DUV11

and so on.

Having one list allows us to use one set of configuration rules and one configuration program.
Table B-1

Floating Device Address Assignments

Rank

Device

Size

(Octal)

Modulus

Address

(Decimal)

1
2
3
4
5

DJ11 gap
DHI11 gap
DQI11 gap
DU11, DUVII gap
DUPI11 gap

4
8
4
4
4

10
20
10
10
10

17760010
17760020
17760030
17760040
17760050

6
7
8

LK11A gap
DMCI11/DMRI11 gap
DZ11/DZV11/DZS11/DZ32

4
4
4

10
10
10 ***

17760060
17760070
17760100

KMCI11 gap
LPP11 gap

4
4

10
10

17760110
17760120

11
12
13
14
15

VMV21 gap
VMV31 gap
DWR70 gap
RL11, RLVI11 gap
LPA11-K gap

4
8
4
4
8

10
20
10
10 *
20 *

17760130
17760140
17760150
17760160
17760200

16
17
18

KW11-C gap
VSV21 gap
RX11/RX211/RXV11/RXV2]l

4
4
4

10
10
10 *

17760210
17760220
17760230

9
10

gap

Table B-1

Rank

Device

19
20

DR11-W gap
DR11-B gap

21
22
23
24
25

Floating Device Address Assignments (Cont.)

Size
(Decimal)

Modulus
(Octal)

4
4

10
10 **

17760250

DMP11 gap
DPV11 gap
ISB11 gap
DMYV11 gap
DEUNA gap

4
4
4
8
4

10
10
10
20
10 *

17760260
17760270
17760300
17760320
17760330

26
27
28
29
30

KDA50/UDAS5SO/RQDX3 gap
DMF32 gap
KMSI11 gap
VS100 gap
TUS81 gap

2
16
6
8
2

4 *
40
20
20
4

17760334
17760340
17760360
17760400
17760404

31
32

KMV11 gap
DHVI11/DHUI11/DHQI11 gap

8
8

20
20

17760420
17760440

Address

17760240

The first device of this type has a fixed address. Any extra devices have a floating address.

The first two devices of this type have a fixed address. Any extra devices have a floating address.

*** The DZ11-E and DZ11-F are treated as two DZ11s.

The address assignment rules are as follows.
1.

Addresses, starting at 17760010, for Q-bus systems, are assigned according to the sequence of
Table B-1.
Option and gap addresses are assigned according to the octal modulus as follows.
Devices with an octal modulus of 4 are assigned an address on a 4; boundary (the two
lowest-order address bits = 0)
Devices with an octal modulus of 10 are assigned an address on a 10; boundary (the
three lowest-order address bits = 0)
Devices with an octal modulus of 20 are assigned an address on a 20;) boundary (the
four lowest-order address bits = 0)

Devices with an octal modulus of 40 are assigned an address on a 40; boundary (the five

lowest-order address bits = 0)

Address space equal to the device’s modulus must be allowed for each device which is
connected to the bus.
A 1-word gap, assigned according to rule 2, must be allowed after the last device of each type.
This gap could be bigger when rule 2 is applied to the following rank.

B-2

A l-word gap, assigned according to rule 2, must be allowed for each unused rank on the list if
a device with a higher address is used. This gap could be bigger when rule 2 is applied to the
following rank.

If extra devices are added to a system, the floating addresses may have to be reassigned in agreement
with these rules.

B.2

FLOATING VECTORS

Each device needs two 16-bit locations for each vector. For example, a device with one receive and one

transmit vector needs four words of vector space.
The vector assignment rules are as follows:

Each device occupies vector address space equal to ‘Size’ words. For example, the DLV11-J
occupies 16 words of vector space. If its vector were 300;, the next available vector would be at
340;.

There are no gaps, except those needed to align an octal modulus.
Table B-2

Rank

Device

1
1
2
2
2

Floating Vector Address Assignments

Size

Modulus

(Decimal)

(Octal)

DCl11
TUSS8
KL11
DLI11-A
DL11-B

4
4
4
4
4

10
10
10 **
10 **
10 **

2
2
3
4
5

DLV11-]
DLV11, DLV11-F
DP11
DMI11-A
DNI11

16
4
4
4
2

10
10
10
10
4

6
7
8
9
10

DMI11-BB/BA
DH11 modem control
DR11-A, DRV11-B
DR11-C, DRV1I
PAG611 (reader + punch)

2
2
4
4
8

4
4
10
10
10

11
12
13
14

4
4
4
4

10
10
10
10

LPDIl11
DTO07
DX11
DL11-C to DLVI1I1-E
DJ11

16
17
17
18

DHI11
VT40
VSV11
LPS11

4
8
8
12

10
10
10
10

Table B-2

Floating Vector Address Assignments (Cont.)

Rank

Device

Size
(Decimal)

Modulus
(Octal)

DQI1

20
21

KWI11-W, KWV11
DUI11, DUV11

4
4

10
10

DUPI11

DV11 4+ modem control

LKI11-A

DWUN

26
27

DMCI11/DMRI11
DZ11/DZS11/DZV11, DZ32

4
4

10
10

KMCl11

LPP11

30
31

VMV21
VMV31

4
4

10
10

VTVO01

33
34

DWR70
RL11/RLV11

4
2

10
4 *

35
36
37
38
39

TS11, TU80
LPAl1-K
IP11/IP300
KW11-C
RX11/RX211 RXVI11/RXV21

2
4
2
4
2

4 *
10
4 *
10
4 *

DR11-W

DRI11-B

4 *

DMP11

43
44

DPVI11
MLI11

4
2

10
4 ***

45
46
47
48
49

ISB11

50
51
52

2
16

10
4 *
4 *
4

KMSI11

PCL11-B
VS100

4
2

10
4

53
54

TUS81
KMV1l1

2
4

4
10

55
56

KCT32
IEX

4
4

10
10

DMV11
DEUNA
KDAS0/RQDX3
DMF32

4
2

DHV11/DHU11/DHQI11

B-4

Table B-2

Rank

Device

58
59

60
61
62
63
64
65
66

Floating Vector Address Assignments (Cont.)

Size

Modulus

(Decimal)

(Octal)

DMZ32/CPI32(async)
CPI32(sync)

12
12

4
4

QNA
QVSS
VS31
LNVI11
QPSS
QTA
DSV11

12
4
2
2
2
2
2

4
10
4
4
4
4
4

The first device of this type has a fixed vector. Any extra devices have a floating vector.

Ifa KL11 or DL11 is used as the console, it has a fixed vector.

*** ML11 is a MASSBUS device which can connect to UNIBUS via a bus adapter.

B-5

APPENDIX C

AUTOMATIC FLOW CONTROL
OVERVIEW
along a communications line, to prevent an overspill of
Flow control is the control of the flow of datadata
which the receiver is unable to accept.

C.1

queues or buffers, or to prevent the loss of

is datastream-embedded ASCII control characters.
The method of flow control adopted for the DHQ11and
XON (octal 021). XOFF stops transmission and
The control characters used are XOFF (octal 023)
they
XON starts transmission. The codes are transmitted in the opposite direction to that of the data
control.

data (received flow-control characters) and twod
The DHQ11 has one mode of operation for transmitted
be enable
mitted flow-control characters). Each mode canix.
modes of operation for received data (trans
append
this
within
ely
separat
ed
discuss
on a ‘per channel’ basis. Each direction of flow is
C.2 CONTROL OF TRANSMITTED DATA

The transmitted-data mode of flow control is the simplest of the three flow-control modes of
DHQI11.

the

bit for that
ter for a particular channel, the TX.ENAthat
When the DHQ11 receives an XOFF charac
channel;
on
the DHQI1 will not transmit any data XON charac
channel is cleared. When this bit is clear,charac
ter
an
ters will still be transmitted. When
however, internally generated flow-control
the
of
ion
operat
the
is received, the TX.ENA bit for that channel is set. Figure C-1 illustrates
transmitted data flow control.

OAUTO=0

XON
RECEIVED

OAUTO=1

OAUTO=0
XOFF RECEIVED

OAUTO=0
RECEIVED

RD225!

Figure C-1

Transmitted Data Flow Control

Only characters without transmission errors are checked for XON and XOFF codes. The characters
have their parity bit stripped before comparison.

NOTE
For the automatic flow control to operate correctly,
the terminal must also recognize and respond to
flow-control characters.
The transmitted-data mode of flow control is enabled by setting OAUTO (bit 4 of the line control
register), and is disabled by clearing it. The default for this mode is disabled.
Received flow-control characters are processed in the same way as normal characters, and are placed
into the receive FIFO. This is not affected by OAUTO, but these characters can be filtered out by setting
DISAB.XRPT. If DISAB.XRPT is set, you do not need a routine in your software driver to filter
flow-control characters from the data stream.

C.3 CONTROL OF RECEIVED DATA
Received-data flow control is slightly more complicated than transmitted-data flow control. Therefore
the two modes of received-data flow control are described separately.
C.3.1 Flow Control By The Level Of The Receive FIFO
Occasionally, the program may not be able to empty the receive FIFO as fast as the received data is
filling it. Because the program does not know how full the receive FIFO is, it cannot take action to
prevent data loss. To overcome this problem, the DHQ11 can be programmed on a ‘per channel’ basis.
When the receive FIFO becomes three-quarters full, an XOFF is sent to the channels from which data is

‘received. An XOFF character is then sent in response to every second received character, until the
receive FIFO level drops below half full. An XON character is then transmitted. The operation of
receive FIFO-level flow control is shown in Figure C-2.

IAUTO=1

FIFO.CRIT=F

CHAR

RCVD

SEND
XON

FIFO.CRIT=T

IAUTO=0

IAUTO=1

FIFO.CRIT=F

CHAR

RCVD

FIFO.CRIT=T

IAUTO=0

IAUTO=1

IAUTO=0

~
~\ STATE

FIFO.CRIT=T

SEND
XON

CHAR
RCVD

IAUTO=0

FIFO.CRIT=F

FIFO.CRIT=

RD2252

Figure C-2

Receive FIFO-Level Flow Control

C-3

The receive FIFO-level flow-control mode is enabled by setting IAUTO (bit 1 of the line control
register), and disabled by clearing the bit. The default for this mode is disabled. If IAUTO is cleared
after an XOFF is sent, but before the receive FIFO level drops below half full, an XON is still sent.
NOTE

FIFO.CRIT is set (T) when the receive FIFO is being

filled, and contains 192 characters. It is cleared (F)
when receive FIFO reaches 127 characters as it is
being emptied.

C.3.2

Flow Control By Program Initiation

Occasionally, the program itself may need to invoke flow control, for example, when host buffers
become full. To allow this, the DHQ11 has a FORCE.XOFF bit (bit 5 of the line control register). When
the FORCE.XOFF bit is set, the DHQ11 transmits an XOFF character for that channel. A further
XOFF bit is transmitted for every second character received on the channel afterwards. An XON is sent
when the FORCE.XOFF bit is cleared. Figure C-3 shows the operation of program-initiated flow
control. The FORCE.XOFF bit is cleared by a DHQ11 reset sequence.

CHAR RCVD

FORCE.XOFF=1

CHAR RCVD

CHAR
RCVD

FORCE.XOFF=1

FORCE.XOFF=0

CHAR RCVD
FORCE.XOFF=0

RD2253

Figure C-3

Program-Initiated Flow Control
NOTE

If the program sets the FORCE.XOFF bit and then
immediately clears it, the XOFF code may not be
transmitted. This is because there is a delay of up to
350 microseconds before the DHQ11 detects the need
to send an XOFF. If the conditions for sending an
XOFTF clear before within this time delay, no XOFF
code will be sent.

C.3.3

Mixing The Two Types Of Received-Data Flow Control

To calculate the effect of using the two modes, they should be logically ORed together; an XON will not
be sent until both sources are inactive. An XOFF will be sent when FORCE.XOFF is set, even if
FIFO-critical mode is active and an XOFF has already been sent on that channel. If the receive FIFO
critical mode becomes active whilst FORCE.XOFF is set, then another XOFF is sent in response to the
next received character.

APPENDIX D

GLOSSARY OF TERMS
D.1 SCOPE
This appendix contains a glossary of terms used in this manual and in other DIGITAL technical
manuals in this series. The terms are in alphabetical order for easy reference.
D.2 GLOSSARY
Asynchronous. A method of serial transmission in which data is preceded by a start bit and followed
by a stop bit. The receiver provides the intermediate timing to identify the data bits.
Auto-answer.

A facility of a modem or terminal to answer a

Auto-flow. Automatic flow control. A method by which
means of special characters within the data stream.
Backward channel. A channel which transmits in
Normally used for supervisory or control signals.

Base address. The Q-bus address of the

BMP.

the

first (lowest)

call automaticallly.

the DHQI1 controls the flow of data by

opposite direction to the usual data flow.

device register (CSR).

Background Monitor Program.

CCITT. Comité Consultatif International de Téléphonie et de Télégraphie. An
standards committee for telephone, telegraph, and data communications networks.

Dataset.

international

See modem.

DMA. Direct Memory Access. A method which allows a bus master to transfer data to or from system
memory without using the host CPU.
Duplex. A method of transmitting and receiving on the same channel at the same time.
EIA. Electrical Industries Association.
CCITT.

American

organization with the same function as the

FCC. Federal Communications Commission. An American organization which regulates and licenses
communications equipment.
FIFO. First In First Out.
removed first.

The term describes a register or memory from which the oldest data is

Floating address. An address assigned to an option which does not have a fixed address allocated. The
address is dependent on other floating address devices connected to the bus.
Floating vector. An interrupt vector assigned to an option which does not have a fixed vector allocated.
The vector is dependent on other floating vector devices connected to the bus.

D-1

FRU.

Field-Replaceable Unit.

IC.

Integrated Circuit.

I/O.

Input/Output.

LSB.

Least-Significant Bit.

MMJ.

Modified Modular Jack.

Modem. The word is a contraction of MOdulator DEModulator.
a transmission line.

MSB.

A modem interfaces a terminal to

A modem is sometimes called a dataset.

Most Significant Bit.

Multiplexer. A device which allows a number of inputs to share one common output.

Null modem. A cable which allows two terminals which use modem control signals to be connected
together directly. It is only possible over short distances.
OCTART.

PCB.

A single IC containing eight UARTs.

Printed Circuit Board.

Protocol.

PSTN.

A set of rules which define the control and flow of data in a communications system.

Public Switched Telephone Network.

Q-bus. A global term for a specific DIGITAL bus on. which the address and data are multiplexed.
RAM.

Random Access Memory.

RFI.

Radio Frequency Interference.

ROM.

Read Only Memory.

Split-speed. A facility of a data communications channel which can transmit data at a different speed
from the received data.
UART. Universal Asynchronous Receiver Transmitter. A device which converts between serial and
parallel data, used for transmission and reception of serial asynchronous data on a channel.

XOFF. A control code (23;) used to disable a transmitter. Special hardware or software is needed for
this function.
XON.

A control code (215) used to enable a transmitter which has been disabled by an XOFF code.

D-2

APPENDIX E

DHQ11 Q-BUS CONNECTIONS

Table E-1