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Document:	DHQ11 User Guide
Order Number:	EK-DHQ11-UG
Revision:	000
Pages:	104
Original Filename:

OCR Text

EK-DHQ11-UG-01

DHQ11

User Guide

dligliltiall}

DHQ'1 'l

u |de

Prepared bv Educatlonal Servnces
of

S Dl

gltal Equmfm

’*"t °°’p°'

a“°" :

GLOSSARY ............
...
e e

APPENDIX E

DHQll Q-BUS CONNECTIONS
|

Figure No.

Title

1-1

FIGURES

PSR

- Layout of the DHQll Module T

TEHP SR

T e et e

1-3

DHQI! Connections (EIA-232-D) .....ovuoiie

i S

DHQI1 Connections (DEC423)

T PEAP S

DHQI1 Functional Block Dlagram e

o 2-1
- 2-2
- 2-3

Location of Swntchpacks ............ e e
e
e
Setting the Device Address ... ..e A
T
Setting the Vector Address .......... e

~
-

241

[/O Insert Panel (DEC423) S

A A ..

2415

- H3173-A Circuit Diagram ...
Null Modem Cable Connectxons .. »..f.‘_.“. e e

2:1T
2920

"H3101 LoopbackConnector ‘ e

Transmitted Data Flow Control ..... L
PRI
SRR (DTSR
- Receive FIFO-Level Flow Control
e
eP
Program-Imtxated Flow Control ....... ..o
|

- Table
No.

1-1

A P

EIA/CCITT Sngnal Relatxonshlps eeenaed e e

- 2-3
3-1

DHQIlI1 Optxons e e aian
s
‘H3173-A Connections ............ e

|
S

C-4

RPN

- Serial-Line Connectlons for the 36—Pm Connector e
DHQI1 Regxsters e

ee e
e

e T

B §
- 2-2
2218

2220

3-2

~Data Rates ....... e e

A-1
B-1
B-2

Modem Control Leads ........... i
i
Floating Device Address Assxgnments P
Floating Vector Address Assxgnments
R

e, AR
TSR - 01
SR
P
- X
I

E-1

DHQll QBus Connecnons ....... I S

SIS SO edeieeoos

Page

e e e L 1-9

Maximum Distance Guxdehnes for DHQll U

2-1
2-2

D
422
Gy
O

TABLES

Tltle

2412
2413

C-3

-1
4

Installing the DHQ11 (DEC423) ............SR |

2-8

1-6

e 24
TN PR - 2-5
e el
246

I/O Insert Panels and Adapter Plate (EIA-732 D)......... e

3-1
4-1
C-1
C-2

-5

247
2410

- 2-6

-3

Bus Grant Continuity ............... I T
S Ne
Installing the DHQI| (EIA 232-D) el '; e
i

2.7

2-10
2-11

Page

IS RS

1-5

Example ofa DHQ!! Configuratxon e

- 1-4

24
25

DHQI!1 Self-'l'est Error Codes P

3-10

. TR

E-l

PREFACE
-."'The DHQI / User Guzde provrdes reference mformatxon on physicalIayout system configuratlon o

~installation and testmg, programming characteristics, and maintenance. Thereis a glossary of technical S

terms generally used n DIGITAL techntcal manuals The manual 1S dmded Into four chapters as
follows
;
r
.
|
|

-CHAPTER 1 INTRODUCTION This chapter gives aphysncal description of the DHQll explams .
how rt can be configured and explaxns how it 1nterfaces thh the system bus and serial data lines.

| CHAPTER 2 INSTALLATION Chapter 2 describes how to install a DHQll option, W1th detaxled,f

“information on device and vector address selectlon backplane posmonmg, cabIes and connectors and’ i
| testmg after 1nstallat10n :
o
o
|
.
|
o

SERE

CHAPTER 3 PROGRAMMING Thxschapter descnbes the DHQII regxsters Some programmmg S e

o examples are also mcluded

’ "CHAPT ER 4 TROUBLESHOOTING Chapter 4 eprams maxntenance strategy, and how to use
‘--dlagnostxc programs to locate a faulty module Sl

-'APPENDICES These 1nclude addltlonal mformatlonon toplcs dlscussed in thls manual
.

APPENDIXA
.~ APPENDIXB

APPENDIXC

APPENDIXD

—
—

MODEM CONTROL
FLOATING ADDRESSES

—

GLOSSARY OF TERMS

—

APPENDIXE =~ —

AUTOMATIC FLOW CONTROL

DHQIl BUS CONNECTIONS

CHAPTER1
-

1.1

SCOPE

This chaptergives anoverview of the DHQll asynchronous multlplexer describes the features thatit
offers and defines its physrcal parameters and electncal requxrements

| '1 2 OVERVIEW
1.2.1 General Descnptlon

The DHQI1 option is a serial-line mterface which provrdes elght full-duplex serial data channels on
~

Q-bus systems. The DHQI1 option consists of a single Q-bus module, and one of two groups of cabinet

kits, depending on the communication standard supported The cabinet kItS contain the cabmet,_ o

bulkhead panels and ‘connecting cables

| The main appllcatton of the DHQll is for mteractlve terrmnal handhng, it can also be used for data

“

concentration and real-time processing. The DHQll reglster set 1s compatlble with the reglster set of the | 4' -

DHVII The main features of the DHQll are:
| _.-1-

-Etght full duplex asynchronous data channels

e For transrmssmn DMA transfers or program transfers to a 1-character transmtt bufi'er for‘f
B ._‘.each hne S

o o B For receive: a 256-entry FIFO bufi'er for recerved characters dataset status changes and-‘i_f’;-f"a ':.
|

dtagnosuc information

L e ‘; 7 It supports EIA-232-D/V 28 or DEC423 W1th the appropnate cabmet klt

NOTE

’v B DEC423 is a term usedin tlus manual to 1nd1cate a
~

data-leads-only unplementatlon of the RS-423-A

electrical standard. DEC423 uses MMJ connectors
__mstead of the 37-way connectors spectfied by RS—449

L ] -:ItIs compatlble with all DIGITAL DHVlI dewce drlvers

e It can auto-answer on a swrtched hne
" 0 | The transmtt and recexve baud rates for each ltne canbe tndmdually programmed
o

It has a total module throughput of 60 000 characters per second using 8-bit characters w1th"”_; e
| all channels operatmg at 38 4 kbaud for both character receptlon and transmxssxon

- 0 -TheIHQll supports l6- 18— or 22blt addressmg, mcludmg block mode data transfer wrth;‘" o

_y’suxtable memories

)

1.1

The DHQl 1 can be programmed to filter XON/XOFF characters from the recexved data flow

Self-test and background mon1tor testing |

Dual-height module, M3107

o Swrtchpacks for selectmg the Q-bus baseaddressand vector address
| All other functtons are selected by program
1.2.1.1 Modem Control Facrhty All exght channels have sulficxent modem ‘control to allow
~auto-answer dial-up operation over the public switched telephone network using suttable modems, such
as DIGITAL’s DF 124, or Bell models 103, 113, 212. Equivalent modems from other manufacturers can
also be used. The DHQI1 is designed to minimize software requirementsfor modem link control.
Appendix A gives further information on modem control. Modem control can be used for driving
modems over both public and private lines. Please note that, in' some countries, modems must be

approved by the P‘I I for that country for connectxon to the publlc network
1.2.1.2 Self-Test

F aclhty The DI-IQll tncorporates self-test sequencers

“which

operate |

independently of the host. The result of the self-testis provided to the host system through the receive

FIFO buffer. A green LED mdtcates GO/ NO- GO status for the device. More detanls are glven in Sectlon |

4.3.

| l 2 1.3 Dlagnostlc Programs A full range ofdtagnostlc programs is avallable These run under the,
MicroPDP-11 diagnostic superwsor or MicroVAX II maintenance system. Loopback test connectors
are not needed when running the user-mode. dlagnosttcs Servxce-mode dlagnostlcs and loopback

| connectors are avallable from DIGITAL

1.2.1.4

Preventmg Data Loss The DHQll can be programmed for automatlc XON and XOFF

operation, to prevent the loss of data at high throughput. The reportxng of recetved XON/XOFF
characters to the software dnver can be enabled or disabled.

| 12 2 Physlcal Descnptlon |

The DHQIl1 is an M3107 dual-height Q bus module Itis 21.6cm (8 51 mches) long and l3 2cm (5.19

inches) wide. Figure 1-1 shows the layout. Connectors A and B are for the Q-bus, while connectors J1

and J2 interface to the communications lines via BCOS5L-xx cables and distribution panels. Two
distribution panels are supplied with an EIA 232-D option, and a single panel is supplied with a
DEC423 option. Connector J3 provides power to the active distribution panel supplied with DEC423

options. This connector is not used with EIA-232- D options. Mixed use, thatis, one EIA-232-D and one

DEC423 panel connected to a smgle module lS not supported by DIGITAL
1221

On-Board Swrtchpacks The DHQII has two on-board swrtchpacks to select the followrng

functions.

v- o Swntchpack E 19 (lO-posmon)
) »’watches 2 to 10 select the devxce address |

.v Swnchpack Ell (8posmon)
Switch 1 enables the on-board oscxllator ThtslS a manufacturtng test sw1tch andis closed fo r

S norrnal operatton

watch 2 selects manufactunng self-test mode Thxsisa manufactunng test sw1tch and1S open R
for normal operatlon
Swrtches 3 to 8 select the dev1ce vector address

Chapter 2 glves further mformatlon about these swm:hpacks

1.2. 2 2 Commumcatlons Standard -The serial dnvers on the M3107 module are compatrble w1th

EIA- 232 D However the CK- DHQll W cabmet krts prov1de level conversxon for DEC423

~ J2 CONNECTOR

——

'CHANNELS 4 - 7

—

———

o CONNECTOR

|rower

|CONNECTOR

CHANNELS 0-3

~ OCTART

- CONTROL
|

| Aporess | |

CHIP

vector

10 POSITION

8 POSITION

SWITCHPACK

aaarzoo}

| I'Figure -1 Layout of"the‘DHQl’ 1 ‘Modu’le

'1.2.3

Versions Of The DHQll

- The DHQ11-M option consists of the M3 107 Q bus module and the User Guzde It can be used with one

of six cabinet kits. The choice of kit depends on the type of system cabmet andon whether a EIA-232-D
or a DEC423 commumcanon mterface is needed

| - The cabinet kits avaxl_able for use thh. th'e DHQI'I-M are:
-

EIA-232-D
e

CK-DHQll AA for BA173/BA11 M boxes

0 | CK-DHQ_l..li.AB for BA23, boxes, -

| ,'_o

CK-DHQILAF fo‘r..H9642 cabinets

DEC423

_’0 CK- DHQll WA for BA123/BA11M boxes

- e
0
1.2.4

CK- DHQll WB for BA23 boxes
CK DHQII WF for H9642 cabmets
Configuratlons

~ The DHQ!1 can be used m many dxfferent system configurauons F1gure 1-2 shows a typlcal EIA-232-D
application.

)

-0

[

HOST

PROCESSOR|

\L_/“\

DEvICE | | Device |

LocaL

EQUIPMENT

—

qrocac 4

;

—

- :

I‘ EIGHT

CHANNELS

‘L-__-.-., Lo .;.---!L-i--i-l

MODEM

OR DATA COMMS
LUNES

—

MODEM

|MODEM |
!

REMOTE
| memoTe |
(EQUIPMENT | TeRMINAL |

[

MODEM

DHQ11 OR

ASYNCHRONOUS

|oevice

|DATACHANNELS
| tI I I I i [

remor

ANY
\

TELEPHONE

| Remore
7 merminaL

DHVIT

~|REMOTE |

_|PROCESSOR|

RE1703

| D

»Fviguré: -2 Example of a DHQll Cor»ifi'gur'a,tidn B

- 1.2.5

Connecnons

The DHQI1 moduleis connected dxrectly to the Q bus by connectors A and B Fxgures 1 3 and 1-4 show |

the mterconnectlons for EIA-232-D and DEC423.

' 40-PIN BERG

' CONNECTORS'

CHANNELS

" H3173-A
DISTRIBUTION PANELS

BACKPLANE (Q22/LSI11 BUS)

0TO3

25 PIN D-TYPE
CONNECTORS

{

CHANNELS

4TO7

" NOTE: BCOS5L-01 = 30 cm (12 INCHES)
|

BCOSL-1K = 53 cm (21 INCHES)

BCO5L-03 = 92 cm (36 INCHES)
REJ

Figure 1-3 DHQll Conn}ections»(EIA-232-D)

1-6

<«

_BACKPLANE

COLOURED STRIP

___——(aunsiaus)

‘P_OWER CABLE

0 ACTIVE
70-22775-XX H310
BULKHEAD PANEL
40-PIN BERG

" CONNECTORS

BCOSL-XX

NOTE:

- H3104 CABLE

CONCENTRATOR

CONNECTOR

CABLE
|

_BC16C-25

BCO5L-01=30cm (12 INCHES)
BCOSL-1K=53cm (21 INCHES)

BCOSL - 03 92cm (36 INCHES)
REJ201

Figure 1-4 DHQI! Connections (DEC423)

13 SPECIFICATION
1.3.1

’

Enmonmental Conditions

The followmg envrronmental constraints for storage and operatlon apply to the DHQll
®
-

The storage temperature must be wrthm the range O degrees Cto 66 degrees C (32 degrees F to
151 degrees F).
o
B

The operatlng temperature must be w1th1n the range 5 degrees C to 60 degrees C (41 degrees F

to 140 degrees F.

,When operatmg, the relatxve humxdlty must be w1thm the range 10 percent to 95 percent “

non-condensing, at a maximum wet- bulb temperatureof 32 degrees C and a minimumdew
pomt of 2 degrees C
,
SR

§-

| D[GITAL normally defines the operatmg temperature range for a system as s degrees Cto 50 degrees C - L
for_
F to 122 degrees F); the 10 degrees C difference between the upper hmlts quoted allows
(41 degrees

the temperature gradrent w1th1n the system box.

R
e

The maximum operating temperatures must be derated by 1.8 degrees C/lOOO m above sea level (1
degree F/1000 ft) for operauon at high-altitude sites.
-

1.3.2

Electrical Reqmrements

The DHQll needs the following electrical supplles
@

For EIA-232 D optlons 5 volts dc plus or minus
|

percent at 1. 8 A maxrmum current, 1.4 A

typtcal

For DEC423 optxons 5 volts dc plus or rnmus 5 percent at2.3 A maximum current, 1 9 A |
typtcal

@ For EIA 232- D and DEC423 optxons 12 volts dc plus or minus 5 percent at 380_rnA :
maxxmum 300 mA typical

)

An on-board sw1tched mode power supply generates"va--lo 'V supply for theserial-line drivers.
1.3.2. l

Q-bus Loads The loads applied to the Q-bus are:

‘@

32ac loads

e 0.5 dc loads

1.3.3 Performance

1 3 3.1 Data Rates
- Each channel can be separately programmed to operate at one of 16 speeds (m
|

- bits/s):

50
75
110
134.5

150

300

600

1800
2000
2400
4800

7200

9600

19200

SRR

- NOTE

) ' See also Sectlon 1.4.4 (Speed and Dlstance
Consnderano-)

Chapter 3 contains further mformatxon on data rates for EIA- 232 D.

1332 Throughput Each channelis capable of t'ull-duplex operatlon at the maxxmum data rate The
followmg maximum throughputis obtalnable
e

At 7 bits per character w1th 1 start blt l stop blt and 1 panty blt the throughput1S 61440
characters per second
|

)

bits per character w1th 1 start b1t 1 stop blt and no panty, the throughput IS 87771

characters per second

This throughput may be limited by your driver software.

14 SERIAL INTERFACES
-

1. 4 1

Interface Standards

The DHQ! 1 provides modem control signals which conform to EIA/CCITT standard EIA-732 D/V.24.

‘The electrical characteristics of the data 51gnal lines conform either to EIA-232-D/V.24 or to
RS-423-A/V.28, depending on which cabinet kitis fitted. The interfaceis compatible with X.26/V.10
standards. The slew-rate requirements for RS-423-A/V.28 are different from the slew rate requtrements
for X 76/V 10

Connections to external equipment are made via 25--pin male submtmature D-type connectors as
specified for EIA- 232 D, or 6-pin MMJ connectors for DEC423
|
—
\lOTE

The H3173-A dlstrlbutlon panel does not support |
separate transmnt and receive grounds

Table l | shows how the sxgnals in EIA 232 D, V.24, and RS-449 are related and hsts the pm?
connectlons for male subrmmature Dtype connectors.
|
Table 1-1

Signalv Name

L |

EIA/CCITT Srgnal Relatlonshtps

‘Signal Groond ~

D-type

" EIA-232-D - Circuit

Circuit

CCITT

RS-449

(SIG

| 'Transmitte_dData R

(TXD)_ :

o ~ RC
102B
S BAr, = 103

- SD

Received Data

RXD)

102

Request To Seed

(RTS)

; 4

‘ 105

. ClarToSed

(€T

* Not Connec‘ted‘

Table 1-1 EIA/CCITT Signal Relationships (Cont.)
Signal Name
D

Ring Indicator

N (RI)

Data Set Ready
Data Terminal Ready

. DataCarrierDetet

| ,l 4.2

|
-

D—type" - EIA-232-D
Pin

- CE

(DSR)

(OI®»

(DCD)

Circuit
CCITT

Circuit
RS-449

125

107

1082

109

Line Receivers

The DHQI! uses octal serial-line receivers which convert lme mput 51gnals to TTL levels for the
OCTART. Signals are mverted by the receivers.
1.4.3

Line Transmltters -

The DHQI11 uses EIA transmxtters Wthh convert TTL Ievel Sgnals from the OCTART to hne levels on
‘the data lmes

1.4.4 Speed And Dlstance Consrderanons |

As of December 1985, the Electronics Industries Assocratxon (EIA) have replaced the “RS-" identifier

for RS-232-C with “EIA”. Therefore RS-232-C has been replaced by EIA- 232- D These two standards |
are compatible with each other. ThlS manual uses EIA-232-D.

~ The RS-232- C/CCITT V.28 standard was originally designed to specrfy the connection between a local
‘interface and a modem. It was not intended to be used for connecting to terminals over long distances.

The maximum specified cable lengthis 50 feet (15 metres). Shielded cable must be usedin order to meet
the requirements of FCC and VDE Radio Frequency Interference (RFI) regulations.

7 Although cable lengths greater than 50 feet can be used with reasonable success, cable capacrtance noise
and ground potential difference restrict the line speed as the distances increase. Consequently, the

performance of long-distance communications to a terminal usmg EIA 232-D often does not meet
today s requirements for terminal wmng

DEC423is a data—leads-only implementation of the RS-423- A/CCITT V.10 standard RS-423 A has a
different groundxng and sxgnal return path arrangement from EIA- 232 D.

‘DEC423 uses line dnver and receiver chips which have better filtenng and txghter level tolerances than
those specified by RS-423-A. In addition, DEC423 devices include transient suppressors. for electrical
overstress (EOS) and electrostatic dxscharge (ESD) protectlon ‘DEC423 devrces may also be connected
with unshielded cable

The t‘eatures provxded by DEC423,' devices are reliable data communication over increased distances,
typically 1000 feet (300 metres)
at 9600 baud. See Table 1-2 for maximum-distance guidelines.

Table 1-2 Maximum Distance Guidelines for DHQ11
S

~Upto

48Kb

DEC423 to DEC423

1000ft

DEC423 to EIA-232-D

300m

96Kb

1000
ft
300m

192Kb

000 ft

300m

2008

25066

—

|
38.4Kb

500 ft

150m

The DEC423 standards for data- leads-only connections to terminal equlpment and1S not suttable for :

connection to modems or other Wide Area Network equipment. The standard also specifies the use ofa
6-pin Modified Modular Jack (MMJ) connector, 1nstead of the much larger 37-pin. Dtype connector
|

| used w1th RS-423A.

| 'DEC423 is 51gnal-compat1ble w1th the EIA-232-D standard when used for data leads only
interconnection, in that interconnection between devices using the different standards is possible.
However, the restncttons on the speed and dlstance of EIA-232- D W1ll Stlll apply |

DEC423 should always be used in preference to EIA 232- D for dlrect termmal connection over
:

~ extended dxstances

NOTE

~An H310S active terminal adapteris necessary when
using an -EIA-232-D terminal with a DEC 423
interface if the longer cable lengths obtamable with
DEC423 are reqmred
|

| _'The recommended cable for DEC423is BC16E XX whxchis avaxlable with 6—ptn MM]J plugs at each ,‘ |
end, in lengths up to 100 feet. This cableis also available without MMJ connectors in 1000-foot reels,

DIGITAL part number H8220. Unshielded four-twisted- pa1r cable can also be used. Thisis availablein (R

o lOOO-foot reels DIGITAL part number H8245 A

NOTE* ;
DEC423 to EJA-232-D is intended for local
communication. In general, communication devices
can become non-operational or be damaged if the
- total cable length exceeds 300 metres (1000 feet) for
- DEC423 devices. The cable should not be run outside
the building, and the low-voltagedata wiring must be
separated from ac power wiring. The installation or
sites may require additional devices to correct'
problems in commumcatlon

—

]
/

NOTE

Under ldeal conditions, DEC423 devrces can drive
cables considerably longer than the 1000-foot
maximum

stated above.

However, differences in

ground potential, pick-up from mains ac power
'cabhng, and risk of induced interference limit the
maximum distance for reliable communications in
most practical srtuatlons

'1 5

FUVCTIONAL DESCRIPTION

1.5. 1 ‘General

The DHQI11 functional blocks are shownin Fi1gure l 5 Most of the functxons are prov1ded by two chips:
“the control ch1p and the OCTART chip.
|
|
Q bus bufi'ermg uses six DC021 bidirectional buffers. Serlal lme mterface bufi'enng uses five octal line

receivers (5180) and three octal line transmxtters (5170) used for data and modem signals.

A 2k x 8 static RAM chlp (2018D-45) prowdes the memory requxrements Swrtchpacks provrde vector
address and module address.

152 Main Functions
-

The main functions of the DHQll are:

Transnnssron — Stngle characters can be
Characters can also be transferred by DMA

transrmtted

usmg

programmed

transfers.

Receptlon — Recexved characters are desenahzed by the OCTART and transferred to a

four-character area in the RAM (one such area per line) by the control chip’'s OCTART

sequencer, following an interrupt from the OCTART. The control chip’s OCTART sequencer

later removes characters from the bottom of the 4-character F IFO, and places themIn the 256
x 16 receive FIFO, whrch can be read by the host

Modem Control — The modem control latches are external to the control chrp Data is

written to the latches from RAM by the UART interface sequencer. The sequencer also
samples modem status lines every 10 milliseconds and reports on changes via the STAT
reglster (and also via the recexve FIFO if programmed to do so).
.

1 5 3 Coatrol Clnp
|
|
|
The control cth contalns the followmg functlonal blocks

Q-bus Interface — Matches addresses, generates vector addresses and handles mterrupts It
‘also mterfaces the Q bus sngnals to other functronal blocks

Data [/O Sequencer — Controls host access to devnce regrsters

OCTART Sequencers— Transfers data between the OCTART and RAM and handles fiow |

control

o
N

Self-Test/Power-Up Sequencer
— This section powers-up the module to a fixed set of m1t1al

condmons such as 9600 baud rate on all lines; it also handles self—test
B

‘DMA Sequencer — Imtxates and manages all DMA data transfers to the module

RAM Arbltrator —Prov1des RAMand OCTARTbus access to the various sequencers

1.54 OCTART Chlp
o
|
This chip contains eight UARTSs. which perform parallel to-serial and serial-to- parallel data
conversions. [t interfaces with the control chip through eight registers. Four are read-only and four are
write-only. An index register is used to access individual lines. The OCTART chip shares the RAM bus

w1th the control chip, and the RAM 1tself The OCTART chxp also mcludes
o

Recerve and transmit control blocks

Interrupt logic for mterfacing with th’e control chip

A 16output baud rate generator

@
0

All necessary hneparameter registers
Dtagnostlc ,loopback logic

Modem status multiplexers. |

-3

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CHAPTER 2

~ INSTALLATION |
‘2.1 SCOPE

This chapter describes the preparatlon and mstallanon of the DHQI11 option. It contains the followmg

sections.

Unpacking

‘Preparation

Installation

o | Testmg
22

UNPACKING AND INSPECTION

If ordered as part of a system, the DHQI1 W1ll already be lnstalled and you should refer to the

mstructxons for unpackmg the system

If ordered as an add--on optron to an exrstmg system a DHQllM (Q- bus module) w1ll be supplied

together with a cabinet kit, distribution panels, and interconnecting cables. The choice of cabinet kit

depends on the type of system and on whether EIA-232-D or DEC423 connection standards apply; s
(Table 2-1 gives details of these options)..
|

DEC423is a term usedm tlns manual to mdrcate a

data-leads-only rmplementatmn of the RS-423-A

| electncal mterface standard

If the equrpment is to be installed by DIGITAL Fleld Servrce the customer should not open the_ L
packages.

If the DHQll was ordered as an add-on option, find thecarton marked OPEN F IRST and carefully L
_unpack it. There is a shxpprng list inside the carton R

Undo each package and examine the contents for phy51cal damage. Check that the contents of each "
e package are complete. Report any damaged or missing items to the shipping agent and to the DIGITAL

- representative. Do not drspose of the packmgmaterlal until the unrt has been 1nstalled and 1s
operatlonal

"//
N
.

Table 2-1

DHQII-M
|

DHQll Options

M3107 module + DHQII User Guide (EK- DHQll-bG)

(Base Opuon)

EIA-232-D Cabinet Kits

CK-DHQI1-AA

BA123 boxes
BA23 boxes
H9624 cabinets

CK-DHQII-AB
CK-DHQ!1-AF

Contents

|
|

H3173A

BCOSL-1K
BCOS5SL-01
BCOSL-03

4-line 25-way dlS[I‘lbuthn panel

40-way ribbon cable, 21 inch
40-way ribbon cable. 12 inch
40-way ribbon cable, 36 inch

'DEC423 Cabmet ths
- CK-DHQI11-WA
CK-DHQI!1-WB =
CK-DHQI11-WF

BA123 boxes
BA23 boxes
- H9624 cabinets

Contents
|

H3100
BCOSL-1K
BCOSL-01
BCOSL-03
70-22775-1K
70-22775-01
70-22775-03

H3104
BC16C-25
| H»3'101
~

Active bulkhead panel
Ribbon cable — 2 inch
-

Ribbon cable — 12 inch
Ribbon cable
— 36 inch
Bulkhead power cable
Bulkhead power cable
Bulkhead power cable

2
o

Multiway cable
Multiway 'c':a»ble‘ Ioo.p'b‘ack'

l
2

‘Cable concentrator

1
l
1
1

1
o

l
1

2. 3 PREPARING THE DHQ11 MODULE
ISR
|
|
Please check that your system has sufficient power and bus load capacxty beore mstallmg additional
‘modules; see your system manual. Before installing the DHQI11, you must define two pararneters by
selectmg them on the DHQI1! on-board sthchpacks The parameters are:

Module address

o | [nterrupt vector

———

. e
<=

NOTE
Ensure that you are wearmg an antistatic wnststrap,
- part number 29-11762-00
2.3.1
Address And Vector Assngnment
|
‘The DHQ! has a floating device address and vector. It s shxpped from the factory with a device address |

~ of 17760440, and a vector of 300,. These assignments are determined by the floatmg address and vector

rules. The factory settings are only correct ifno other floating address option is installedin the system.
Otherwise. the proper rules for address assignment must. be applied: these are given in Appendix C.

2.3.2 Setting The Address Swntches
|
The device address for the DHQILI is set on the 10-position smtchpack EI9: the locatlon of this

'\\

~switchpack is shown In Fuzure
2-1. SW-1 is not used and must be set OFF (open).

)
/!
A\\
10 POSITION

SWITCHPACK

(ADDRESS)

8 POSITION

SWITCHPACK

(VECTOR)

R
IEs

Figure 2-1

Loéétion of Switchpacks

Figure 2-2 shows how to set the device address on the swflchpack The etample shown is for the

factory set address of 177604408

OHV/DHU MODE SELECTION

LEGEND

DEVICE ADDRESS SELECTION

PART OF SWITCHPACK E36

D = SWITCH OFF (BINARY
0)
o

~ (DHU MODE SELECTED)

PART OF SWITCHPACK E36

3 4

5 6

INTERPRETED

AS ALL ONES ~

—

]

DEVICE

20] 1918 ]| 17|

ADDRESS

‘

NOTE:

16|15 |1al13]{12]|
7
|

USE THE BLANK ROW TO

|
'

.
1
1
1y
1

EACH

PATTERN YOU NEED

GROUP

\\,

oecooen
BYDEVICE
—

—

]

05| 0a|03]|02]01]|

|
o

11| 10| 09| 08|07 |06

EXAMPLE

SETTING

=17760440

'
1
b

PENCIL-IN THE ADDRESS
fffff

10
|

‘

—
0
ot

SEE NOTE

aiTno. | 21|

’

l = SWITCH ON (BINARY
1) - °
|

:
IDENTICAL

\\I/

o]=8

ojlolof=o0

o0l=2

11]l=3"

olof=4

)
1

11|

o0|=6

EERREE

;

1]=5

Qg2719

F1gure 2-2 Settmg the Dev1ce Address

| 2 3.3

Settmg The Vector Smtchel
The six high-order bits of the interrupt are set on the exght-posmon sthchpack Ell. F:gure 2-1 shows

|
N

)

the location of this switchpack. Figure 2-3 shows an example of these switches set to the factory setting

0f300;. Switches | and 2 are used during manufacture, SW-1 must be set ON (closed) and SW 2 must be
set OFF (open) for correct operatxon of the DHQll

; MANUFACTURING TEST SWITCHES-

SW1 MUST BE ON
- CLOSED
'SW2 MUST BE OFF
- OPEN
PART OF SWITCHPACK E11

LEGEND

D SWITCH .OFF

(BINARY 0) OPEN

EXAMPLE

TTIN G
25300

l. SWITCH ON

(BINARY 1) CLOSED

S[ NO B

———r—————

|
-

VECTOR ADDRESS SELECT!ON
PART OF SWITCHPACK E11

INTERPRETED |

AS ALL ZEROES

-1

DECODED

| BY/DEVICE
-

SEE NOTE

N0
VECTOR =~

- ADDRESS:
NOTE:

[ 15 1a
0

132|110 09]08|07| 06|

05|04 0302|0100

USE THE BLANK ROW TO

PENCIL-IN THE ADDRESS
" PATTERN YOU NEED
M

BOTH GROUPS IDENTICAL

21010
Qo1

7]=0
=1

o|1]0{|=2

o '

1ol

|=5

1110

|=6

REJ224

‘Figure 2-3 Setting the Vector Address
2.4 BUS CONTINUITY
|
|
|
Bus grant continuity jumper cards (M9047) are usedin vacant backplane slots to provide bus contmmty

(see Fxgure 2-4).

NOTE

To find out the type of backplane on your system,
consult your system manual

Q/Q BACKPLANE
A

PROCESSOR

-~ T

1 —A—|-—}F - — -

Q/CD BACKPLANE

TERMINATOR

11
12

13
REI202

Figure 2-4

Bus Grant “C,ontin_u'ityA

2.41 Bus Grant Continuity Jumpers

‘Backplanes suitable for DHQ!1

fall into two groups.

- QICD —

Q-bus on A and B conneé'tors,' .uscrrdéfined. signals on C and D

| Q/Q

QQbus on A and B, and C .andD_‘conn‘ectors.. |

—

In Q/CD backplanes, bus grant 51gnals pass through each 1nstalled module via the A and C connectors
of each bus slot

Q/Q backplanes are de51gned 50 that two dual-hexght optlons can be lnstalledin a quad height bus slot.

The Q-bus lines are routed as follows
1.

AB, first slot

2. CD first slot

CD, second slot

4. AB. second slot
and sO on.

Each dual hexght module extends the contmulty of the bus grant sngnals BIAK and BD MG to the next
module. Therefore, with a Q,Q backplane,. if a quad module (DHV11) is replaced with a dual module
DHQI 1), a Q-bus grant continuity card M9047 is needed for the vacant slot

2.5

PRIORITY SELEC‘T ION

The bus (backplane) position may be a compromlse between DMA and interrupt priority requxrements
As a general rule, consider DMA request pnontles first, and then consider 1nterrupt (bus) requests.
2.5.1

DMA Request Pnonty

DMA request priority is usually assigned accordxng to throughput Faster devices (hxgher throughput)' |
usually have priority over slower DMA devices; for example, disk has priority over tape, which itself has
priority over communications devices. Thisis because fast devices usually reach overrun or underrun

conditions sooner than slower ones.
2.5.2

Interrupt Request Pnonty

2.5.3

Recommendations

The DHQI1 has a fixed interrupt priority level of 4, and cannot be changed to other priority levels. It
does not monitor any of the higher-level interrupt request lines. Because of this, both the
interrupt-request and DMA (non-processor request) priorities of the DHQI1! are selected by the
position of the DHQ!1 on the bus; it must therefore be positioned after any device that does monitor
any of the request lines. Devices closest to the processor module have the highest prionty.

.In general the DHQI1 bus posmon is not critical. However it is recommended that you place the
module after any mass-storage interfaces and high-speed synchronous communications optlons these
are more sensitive to bus position.

INSTALLING THE DHQ11

2.6

Once you have defined the backplane posmon for the DHQII you can begm to mstall the DHQII

‘module.

" 261 Installing The M3107 Module
WARNING |
Shut off the svstem power and dlsconnect the main

system power cord before performmg any procedure

)

- .m this chapter |

ATTENTION

Avant d’effectuer I'une des procédures de ce chapitre,

~ mettez le systeme hors tension et debranchez le
cordon d’ahmentanon
,

VORSICHT!

L
|
"
)

SRR

Sie das System ab, und ziehen Sie das
~ Schalten
~ Netzkabel, bevor Sie die in diesem Kapltel
vbeschnebenen Anwelsungen ausfiihren.
|
ATE‘\JCION

| Apague el sistema y desconecte el cable principal de

alimentacion antes de realizar mngun procedumento

~ de este capltulo

Connect the BCOSL cables to J1 and J2. Figuré 2-5 for EIA-232-D installations and Figure

Install the module in its correct backplane position as previo'u‘sly defined.

2-6 for DEC423 installations show how the parts of the option connect together.

NOTE

o
)

e
|

' Be careful not to snag module components on the card

- guides or adjacent modules.

Check that bus continuity exists. If necessary. install bus grant’co‘ntinuity cards.

y;
«

Do not connect the cables to the bulkhead panels.

A PRINTED|

ON PCB

40-PIN BERG
CONNECTORS

;

CHANNELS

"~
i

“\

RED LINE

TO A

RED LINE

TOA

0TO3

BACKPLANE (Q-BUS)

H3173-A
DISTRIBUTION |
PANEL

/25 PIN O-TYPE

RED LINE

NNECTORS'

BCOSL-XX

CABLE

)

|
CHANNELS

aTO7

NOTE:

B8COS5L-01 =30.48CM (12 INCHES)

BCOSL-1K = 53.34 CM (21 INCHES)
8CO5L-03 = 91.44 CM (36 INCHES)

Figure 2-5

Installing the DHQI1 (EIA-232-D)

A(;Eooo'o

BDFooooO

70-22775-XX _

\t PIN A

RED LINE

< BACKPLANE

TOA

__\— (Qasisus)

|
A

) ..j’" . "‘:‘:‘4 \

2
-

’® .~ BULKHEAD PANEL

/,.

v- ’l\‘-' )

~40-PIN BERG

' '

CONNECTORS

. )

~COLOURED STRIP
“\BCOSL-XX
CABLE

. POWER CABLE

70-22775-XX
NOTE:

P
S
BCO5L-01 =30cm (12 INCHES)

BCOSL-1K

=53cm (21 INCHES)
BCOSL-03=92cm (36 INCHES)
- 2€3203

* Figure 2-6
- 2.6.2

Installing the DHQLL (DEC423)‘

Dlstnbunon Panels

The rear [/O distribution panel has
six cutouts: two type-A cutouts and four type-B cutouts [n addition,
a removable bracket between the third and fourth cutout allows you to install three more type-A insert
panels by mounting an adapter plate Fi1gure 2-7 shows typical type-A and type-B msert panels and the
adapter plate.

- 2.6.3

Instalhng The EIA-232-D Dlstnbutlon Panels

The DHQ! 1 has two type-B distribution panels Figure 2-7 shows how these are 1nstalledina BA23 box

: Installatlon in BA123 and H9642 cabmets lS snmxlar

To fit the dlStl’lbthlOt‘l panels

' 1 ! | Remove the two type-B blanking panels.
R

Bolt the two H3l73 A distribution panels into the cutouts
Connect the free end of the BC05LXX cable frorn connector Jl of the module to the first
dxstnbutlon panel.

Connect the free end of the BCO5L-XX cable from connector J2 of the module to the second
distribution panel.

TYPE 8

~ REMOVABLE INSERT

tt)

(1)

)

PANELS

50-PIN CONNECTOR

'EXPANSION SLOTS-TYPE A

Figure 2-7 I/’O I'néert Panels and Adapter Plate (EIA'—’232-D)
2. 6 4 Instaumg The DEC423 Distribution Panels

The DHQll has one type-B distribution panelFigure 2-8 shows how this 1s mstalledin a BA23 box |
|

Installauon in BA123 and H9642 cabinets 1s smxlar

To fit the distribution panels
1.

- 2.

‘Bolt the H3100 actxve dxstnbutlon panel mto the cutout

Connect the free end of the BCOSL-XX cable frorn connector Jl ot’ the module to the upper
|

(J2) connector on the distribution panel

4. | Connect the free end of the BCOSL XX cable from connector J7 of the rnodule to » the 1ower
|

Jn connector on the distribution panel

Connect the free end of the power cable (70-72775XX) to the left hand power connector (J3)
o

on the distribution panel

)

Removea type-B blanklng panel

()

(4)

REMOVABLE INSERT

50-PIN CONNECTOR

* EXPANSION SLOTS

thure 2. 8 I/O,. I.fttsert- Panel (DEC423)
2.7

INSTALLATION TESTING

This section details the diagnostics used to test the option during and after mstallatton The dtagnosttcs
are also used to test other Q-bus modulesin the same farmly, for example, DHV1 l The dtagnosttcs will
~ automattcally size’ the option to determme which one 1S bemg tested

| _.._Both MicroPDP-11 and MtcroVAX 11 dtagnosttcs are descnbed After successful completton of the |
- appropriate system test, the DHQ!1 may be connected to extemal equtpment F urther tnforrnatton on
the diagnosticsis ngen in Chapter 4.

2.7.1 Installanon Tests On chroPDP-ll Syste

To verify that the MicroPDP-11 system and the DHQIImodule are functtomng correctly
l.

Sthch on the system

After 2 seconds, check that the green self-test LED on the DHQI l rnodules on. Ifit does not |

come on, call DIGITAL Field Service.

3. - Boot the Micro-11 Customer Diagnostic media. Refer to your \/IzcroPDP [1 System Manual
~

for further information.

Type T’ at the main menu to allow the dtagnosttcs to 1dent1fy the new module and add it to
the configuratton file.

NOTE

Look at the list of devices displayed, and make sure
that the new module is included. If it is not included,
repeat the installation sequence, and make sure that

the module switches have been set correctly.

Type'T at the main menu to run the system tests. These should complete wnthout error; if an
|
erTor occurs, call DIGITAL F 1e1d Service.

A MicroPDP-11 Maintenance Kitis avaxlable and may be ordered from your local DIGITAL office
This kit allows trained personnel to run individual diagnostic programs under the XXDP + diagnostic
monitor, and to configure and run DECXI11 system test programs. The XXDP + functional dxagnostxc
|
‘
is VHQA**.BIN, and the DECXll moduleIS XDHV" OBIJ.
2. 7 2 Testing In MrcroVAX II Systems

To verify that the chroVAX [T system and the DHQll rnodule are functlomng correctly:
1. Check that the oreen self-test LED on the DHQI1 module iS on. |

- 2.

Bootthe chroVAX Maxntenam.e System media. Refer to your MicroV4X [ S_t_"stem Moanual

for further information.

Type 2’ at the main menuto show the system configuration and devices.
VOTE

Look at the list of devices displayed, and make sure
that the new module is included. If it is not included,
repeat the installation sequence, and make sure that
the module swrtches have been set correctly

4.
-

Type |’ at the main menu to run the system tests. These should complete w1thout error 1fan
error occurs, call DIGITAL Freld Serv1ce
»

2.8 H3101 LOOPBACK CONNECT OR
The H3101 loopback connector (see Figure2-9)is used during diagnostic tests for DEC423 installations.

-~ Itistwo loopback connectors in one package, and consists of a female 36-way loopback connectoranda
male 36-way loopback connector. It can be inserted into the cabling at the distribution panel, or at the
cable concentrator. To test the cables, type characters at the keyboard and make sure that they are

echoed to the screen (refer to Chapter 4)

Tx#-o—-j'1’——oT~<+

(
\

| - Rx + o— 2 e Rx +

(

LINEO

[

Tx +

LINE 2 3

Rx +

Tx *

[‘

LINE 3 | ;

T+
Rx + :10 ‘

Ll NE 4 ,

MALE CONNECTOR

LINE 2

Tx +

LINE 3

Rx+ s

LINE4

Rx +

LINE 5 %Ax +

[

A+ .

LINE S

CRx e+
LINE 6 ;

[

Ax +

| LINES

Tx +

18 -

NOT USED

LINE

Tx +

Rx + Z::] 18

NOT USED

LINET1

LINE 2

LINE 3
LINE 4

;

Tx -

L,'NE

Rx +

L |

Rx =

21 Tx - ;

22 Rx -

_ l

23
Tx - :

Tx =

Rx =

Rx -

25
- C
:v —l
; _ Tx
26
Rx -

Tx =

Tx - : 27

Tx =

- :
31

Tx =

Ao-

LINE3
s
%

Q=i

O—-[33:Tx—

%Rx-O——J34

Rx -

LINE1

LINE 2

Rx -

:LINE 6

X+

Rx -

-~ LINE S

.
LINE 7

120

Ax =

LINEO

LINE

FEMALE CONNECTOR

LINEO

LIN

L|NE4‘

LINE S
LINE 6

LINE 7

NOT USED : : NOT USED

NOT USED

NQT USED

agl418

Flgure -9

H3101 Loopback Connector

2-15

/
N

29 CABLES AND CONNECTORS — EIA-232 D
2.9.1

Distribution Panel

Each H3173-A distribution panel adapts one of the DHQll Berg connectors to four subrmmature

D-type EIA-232-D connectors. Noise filteringis provided on each pin of the EIA-232-D connectors.
This reduces electromagnenc radiation from the cables and also provxdes the logic thh some protecuon |
against static dlscharge |
~

Figure 2-10 shows the cu'cuxt of the H3173- A There IS nO CCITT equivalent of EIA circuit AA

(Protecuve Ground). You can remove the 0-ohm lmk Wi to dxsconnect this circuit if necessary.

_RING INDICATOR 2/6

‘w N“\JI

< 9C 9 g P> 90 92 o=

'SIGNAL GROUND

TRANSMIT DATA 1/5
RECEIVE DATA 1/5

TRANSMIT DATA 2/6
SIGNAL GROUND

K Y ooké
U ¥
H

DATA CARRIER DETECT 0/4

_RECEIVE DATA 2/6

_DATA SET READY 0/4

d-bo bo

DATA TERMINAL READY 2/6

REQUEST TO SEND 0,4

CLEAR TO SEND 2/6

CLEAR TOSEND 0/4

_REQUEST TO SEND 2.6

N -

RING INDICATOR 0/4

__DATA SET READY 2/6

" YO TSN YRS

DATA TERMINAL READY 0/4

DATA CARRIER DETECT 2/6

DATA CARRIER DETECT 3/7
DATA SET READY 3/7_

‘m ® ‘~4 |

RECE!VE DATA 0/4

5 0w en L\l <

_TRANSMIT DATA 0/4

o~ o
&N
N

SIGNAL GROUND

RING INDICATOR 1/5

REQUEST TO SEND 3/7

| CLEAR TOSEND 1/5

CLEAR TO SEND 3/7

'REQUEST TO SEND 1/5

RING INDICATOR 3/7

. 2> 9

DATA SET READY 1/5

DATA CARR__!ER DETECT 1/5

—

®— O QO

_DATA TERMINAL READY 3/7

' RECEIVE DATA 3/7

TRANSMIT DATA 3/7

_SIGNAL GROUND

PROTECTIVE GROUND

Figure 2-10

H3173-A Circuit Diagram

¢ or ‘w o> bs e &b

DATA TERMINAL READY 1/5

Table 2-2 18 for two distribution panels. The numbers within p'arentheses apply to channels 4 to 7.

Table 2-2 H3173-A Connectiom
Signal

- Name

SIG GND 0(4)
TXDO0(4)
=

RXDO0(4)
-

DTRO(4)
RIO(4)

CTS0(4)

'RTS0(4)
- DSRO0(4)
DCDO0O4)

Cu'ctut No

o
o
Transmitted Data

102
103

[-A (2-A)
1-B (2-B)

Received Data

104

1-C (2-C)

Data Terminal Ready
Ringing [ndicator

Clear to Send

Request to Send
-

Data Set Ready
Datd Camer Detected

SIG GND 1(5)
TXDI(5)
- RXDI(J)

DTRI(5)

108,2
125

1-D (2-D)
l-E (2-E)

106

[-F (2-F)

105

[-H (2-H)

107
109

[-K (2-K)
l-L (2-L)

102
- 103
104

1-M (2-M)
1-N (2-N)
I-P (2-P)

108/2

RII(5)

1-R (2-R)

125

- 1-8 (2-S)

CTSI1(S) .

106

[-T (2-T)

RTSI(9)
DSRI(5)

105
107

1-U (2-U)
1-W (2-W)

DCDI1(35)

- 109

- 1-X (2-X)

DCD2(6)
- DSR2(6)

109
- 107

1-Y (2-Y)

RTS2(6)
CTS2(6)
RI2(6)
RXD2(6)

108/2

I-EE (2-EE)
|-FF (2-FF)

103
102

DCD3(7)
DSR37)
RTS3(7)
CTS3(7)
RI(7)
DTR3(7)
RXD3(7)

109
107
105
106
125
108/2
104

1-BB (2-BB)
1-CC (2-CO)
1-DD (2-DD)

104

TXD2(6)
|
SIG GND 2(6)

- TXD3(7)
SIG GND 3(7)

1-Z (2-2)

105
B
106
125

DTR2(6)
-

J5 Pin No.

1-HH (2-HH)
1-JJ (2-1))

[-KK (2-KK)
- 1-LL (2-LL)
1-NN (2-NN)
1-PP (2-PP)
[-RR (2-RR)
1-SS (2-SS)
I-TT 2-TT)
- 1-UU (2-UU)
| VV 2VV)

103

102

The fcllowing examples show howto use Table 2-2.
Signal TXDO is the transmitted data line for channel 0; the CCITT circuit number is 103 and it is

connected to J5 pin B on the first H3l73 A for channels 0 to 3.

Signal TXD4 is the transmitted data line for channel 4; the CCITT cxrcuxt number 1S 103 and It is
connected to J5 pin B on the second H3173-A for channels 4 to 7.

2.9.2 Null Modem Cables

~ Null modem cables are used for local EIA-232-D connection, when a modemis not used. Because of
Federal Communications Commuission (FCC) regulations, the cable specxficanonsfor the United States
‘and Canada are different from those for non-FCC countries. Other countries may also have similar
electromagnetic interference (EMI) control regulations. EVIC/ RFI shlelded cabinets are now avallable

for systems whlch conform to FCC requirements.

Recommended null modem cables are as follows

BC22D (for EMC RFI shielded cabinets)

| o

Rounded 6-conductor fullyshielded cable to FCC spemficauon

Submxnlature 25-pin D-type female co_nnector moulded on each end

°
-

)

l_engthsfla'vailable:

'BC22D-10

3lm

(10 fr)

BC2D-35

BC22D-50

107m

BC22D-75

152m

(35ft)

BC22D-A0
BC22D-BS

229m

30.5m
762m

(I5f)

(100 ft)
(250 ft)

BC22D-25

|
76m

(25f)

(50 ft)

BCO3M

Round'6-conductor'(three twistedpairs) each pair shielded

Cables over 30.5m (100 ft) have a 25-pin submlmature D-type female connector at one

end. The other end 1s unterminated, for passing through the condult

Cables 30 Sm (100 ft) and less have a similar connector at each end

V-Lengths available:
BCO3M-25

~ BCO3M-A0

BC22A

76m

(25ft)

76.2m
152.4m
3048
m

(250 ft)
(500 ft)
(1000 ft)

305m (l00f)

BCO3M-BS
BCO3M-E0
BCO3M-L0

Round 6-conductor cable

Subminiature 25-pin D-type female connector moulded
at each end

Lengths availablez

BC22A-10

BC2A25

3.1

(10
fr)

76m

(25f)

Cables of groups |, 2, and 3 are all connected as m Flgure 2-11. The cables are not polanzed They can
be connected exther way round

NUMBEHS

) %TRANSMH'TEDDATA _

oRECEIVED DATA _

. e RECE!VED DATA o
TRANSMITTED DATAfiO ,

b6 SIGNAVL GBOUND o o SIGNAL GROUNDfl.
| * DATA TERMINAL READY 020
" c DATA SET READY

READY—06
DATA SET
"~
DATA TERMINAL READY —_—
_

20 O—

Figure 2-11

Null Modem Cable Connections

2.9.3 Full Modem Cables

Recommended full modem cables are as follows:

BC22F (for EMC/RFI-shielded cabinets)
e

Rounded 25-conductor fully shlelded cable

Subtmmature 25-pin D-type female connector on one end male connectoron the other

)

Lengths avaxlable.

151525 BC22F-10
3.1 m

(10 ft)

29m

(75 )

BC22F-25
BC22F-35
BC22F-50
BC22F-75

76m
107m
152m

(2511
(35f)
(50 fr)

BCOSD

| 0"

RoundZS-conductor cable

Subminiature 25-pin D-type, female connector on one end. male connector on the other

PROTECTIVE GROUND

. o_PROTECTIVE GROUND

)

NUMBERS

Lengihs available:

BCOSD-10

3.1 m

(10 ft)

BCO5D-50
BCO05D-60
BC05D-A0

15.2 m
18.6 m
30.5 m

(50 fr)
(60 ft)
(100 ft)

BC05D-25

7.6 m

(25 ft)

\JOTE |

In some countr:es. protectlve hardware may be
needed when connecting to certain lmes Refer to the
national ,regulanons before making a connection.

2.10

CABLES AND CONNECTORS — DEC423

The H3 100 active distribution panel adapts the the (WO DHQI!I Berg connectors to one 36--Way fi\\IP
“connector. Noise filtering is provided on each pin of the connector. This reduces electromagnetic

radiation from the cables and also provides the logic with some protection against static dlSLhdrUE .

fifiltered connectors used on DHQI 1 with DEC423
Table 2-3 shows connectxons to the 36-pin AMP

“installations.

Table 2-3 Serial-Line Connections_for the 36-Pin Connector

BlwWht

Line0

Transmit +

Line |

Transmit +

Line0

Transmit -

WhtBlu

Line0
Line0

Receive -

Wht/Gmn

Line |

- Transmit —

WhySkt

Line 2

Transmit -

Red/Org

Line 3

| ~Transmit-

Wht/Org

Receive +

Org/Wht

Grn/Wht
Brn/Wht

Line |

SlyWht

Line?2

Line 2

Receive +

7 Org/Red

Grn/Red

Line 3

Transrnit + 25

‘Red/Gmn

Brn/Red

Line 4

" Transmit + 27

Red/Brn
Red/Sit

Line 4

Transmit - |

4
6

Blu/Red

Slt/Red

Line 4

Receive+

Transmit + 23

Receive +

‘Wht/Bm
Red/Blu

Line 1
Line 2

Line 3

Recetve -

Receive -

Org/Blk

BluBlk

LineS

Transmit + 29

Blk/Blu

LineS

Transmit -

Grn/Blk

Line 6

Transmit + 31
Receive +

Blk'/’Grn'

" Line 6

Transmit -

Line7

Transmit +

SlyBlk

Blu/Yel

Line 7

Org/Yel

Spare

G/ Yel

Receive +

Blk/Org

Blk/Bm

Line 5

Line 6

Yel/Blu

BlkSlt

Line7

Yel/Org

| Spare

Spare

Brn/Blk

Line 6

Receive +

Line 5

Yel,Grn

Line 7

- Spare

Receive -

Transmit -

~ Recerve -

CHAPTER 3
PROGRAMMING
3. l SCOPE

This chapter descrtbes the devxce registers. and how they are used to control and momtor the DHQl l.
The chapter covers:

The bit functions and format of euch register

Programming features available to the host.

Some prOgramming examples are also included.
|
|
:
3.2 REGISTERS
~ The host system controls and momtors the DHQL1I module through several Q-bus-addressable rezxsters

.Command words or bytes written to the registers are mterpreted and exccuted by the module Status
reports. and data are also transferred through the registers.
3.2.1

The DHQH regxsters occupy 8 words (16 bytes) of Q bus memory-mapped [O space

" The base physrcal address of the exght DHQl 1 reglsters is selected by usmg swrtches on the module The

‘address selected is in the peripheral [/O space. The term ‘base’ means the lowest I/O address on the

- module; that is to say, when the four low-order address bltS = 0.

Table 3-1 lists the DHQIl1 reg1$ters and thexr addresses. The suffix (I) means that there are exght of these

registers, one for each channel. When an (I) register is accessed, the contents of CSR<3:.0> selectsy
which of the eight registers at that addressis actually accessed
'NOTE

CSR<3:0> allows up to 16 channels to be

addressed. However, only the lower eight channels are
used Therefore CSR blt 3 must always be 0.

Table
-1 DHQII Registers

Control and Status
-

Receive Buffer

'_ |

|
|

Transmit Character

(»Oct‘a_l)__,r’

Type
S

(CSR) | Base
|

~
|

- Address

B Read Write
|

(RBUF) Base+2
(TXCHAR)

Base+2(I)

-1

Read Only

Write Only

Table 3-1
Register

DHQI11 Registers (Cont.)

Line-Parameter
Line Status
Line Control

(LPR)
n

Transmit Buffer

~ Address |

Transmit Buffer

Address 2

Base+4 (D)

Base+ 12(I)

'Read/Wrnite

Base+!HI)

Base+ 16(])

(TBUFFCT)

Read Only
Read; Write
|

- (TBUFFAD2)

Transmit Buffer Count

Type

(STAT)
Base+6 (I)
(LNCTRL) Base+ 10(I)

(TBUFFADIL)

Address
(Octal)

Read. Write

Read Write

NOTE

It is possible to write to the line-status register.
However, the host should not write to this register

There are eight line-parameter registers, only one of which is accessed at any one time. The register
which is accessed1S associated w1th the line selected using CSR < 30>,

For example to read the line-parameter reglster of channel 3 the tollowmg I/O commands would be

executed:

MOVB !CHGN‘,QOBASE-'

- MOVB @®BASE+4, RO

~ ;WRITE CHANNELNUHBER’ (SEE BELOW) TO CSR
READ THE LINE PARAMETER REGISTER

»In the above example CHAN OerOOOl l(bmary)
W_here.y

0011

--the RXIE bit of the CSR

the MASTER.RESET blt (whxch would be 0)

channel number 3

_NOTE_}'

L ‘Not ,au-register bits are used. In a write action,

all unused bits must be written as 0s. In a read

, actlon, unused blts are undefined

Read-modify-write instructions may be used on

all registers except CSR and RBUF.
3 2.2

Reglster Bit Defimtrons

Registers Wthh are modxfied by reset sequences are coded as shown in Figure 3- l

Av/

PUSER——

= CLEARED BY MASTER RESET

= SET BY MASTER RESET

CLEARED BY BINIT
BUT NOT 8Y MASTER RESET
anrzag

| Fi2ure‘3 l' R_eg_‘i‘s'te‘r Coding;
3.2.2.1

Control And Status Regxster (CSR) -

CSR (BASE)
95

|
12

| R R/W‘ R

R | R | R| R | R |RW|RW

DIAGNOSTICS

ACTION | FAILURE

TRANSMIT

r
" Bit

DMA ERROR

Name

AVAILABLE

’R/vv R'W |R/W | R/W
|

| l

NagLe | NDIRECT ADDRESS REG POINTER

Axiey

RCVEDATA

| Reve |

LINENUMBER

T,\Tfi“éi‘“zgl_é TRANSMIT
INT-

14
13

(CHANNEL NO)

MASTER
RESET

2€3228

Description

TXACTION

This bit is set by the DHQlI When: |

(Transmitter Action) (R)

The last character of a DMA buffer has left the
OCTART.

A DMA transfer has been aborted.

3. A DMA transfer has been terminated by the
-

DHQI1 because non-existent memory has been
addressed, or because of a host memory party

error.

4. A single’-character programmed output has been
-

3-3

accepted; that is to say. the character has been
taken from TX. CHAR

Bit

o Descnptlon

Name

The bitis cleared if the host reads the CSR after the
"TX.ACTION FIFO has become empty. To avoid
losing TX.ACTION reports, the host must not let
- more than 16 reports accumulate. [t is advisable to
- read the CSR until TX.ACTION becomes clear.

NOTE

- TX. ACTIOV reports may be lost if the upper byte of
the CSR is discarded following a read of the CSR

TXIE
(Transmit Interrupt Enable)

When set, thrs bit allows the DHQ! ! to interrupt the
host when CSR< 15> (TX. ACTION) becomes set.

is cleared

MASTER.RESET.

- DIAG.FAIL

by "BINIT,. but
|

oot

When set, this bit indicates that the DHQ1! internal
diagnostics huve detected an error. The error may
have been detected by the self-test sequencer or by
the 'background monitor program (BM‘P) |

(Diagnostic Fail) (R)

This bit is assocrated with the dxagnostxc-passed
LED. When it is set, the LED will be off. When it is
~ Cleared, the LED will be on.
|
|

The bitis set by MASTER.RESET. Ttis cleared after the self-test has run successfully.

~
12

TX.DMA.ERROR

(Transmit DMA Error) (R)

Not valid if MASTER.RESET is set.

If this bitis éet 'and TX.ACTIONis also set, either

the channel indicated by CSR
< 11:8> has failed to
~ transfer DMA data within 10 microseconds of the
bus request being acknowledged, OR thereis a host

memory panty error.

' The TBUFFADI and TBUFFAD?2 registers _wxll

contain the address of the memory location at which |
the error occurred. TBUFFCT w1ll be cleared

<l’l:8>

TX.LINE

(Transmit Line Number) (R)

If TX.ACTION is set. these bits hold the line

| nurnber to whrch TX ACTION refers

~ Bit

7.
|

Name

Descnpnon

RX.DATA.AVAIL
(Received Data Available) (R)

When set, this bit indicates that a recetved character
is available. It is clear when the receive FIFO is

~empty. It is used to request a receive interrupt.

Itis set after MASTER. RESET because the receive
FIFO contaxns ‘diagnostic information.

'« RXIE

" (Receiver Interrupt Enable)
(R, W)

? When set. thxsvbtt allowsthe DHQH to interrupt the

host when RX.DATA.AVAIL is set. An interrupt 1s
|
Ureneratted under the tollowmg condmons

RXIE is set and a character is placed nto an

empty receive FIFO

The receive FIFO contains one or more

characters, and RXIE is changed trom 0 to [.

It is*cleared by BINiT but not by MASTER.RESET.

‘MASTER. RESET

(Master Reset) (R/W)

I'v

- <3:.0>
-

- IND. ADDR' REG

(Indirect Address Regxster)

_RW)

" This bitis set by the host to reset the module. [tstays

set while the DHQl | runs the self-test and performs

an initialization sequence. The bitis then cleared to
tell the host that the process is cornplete |

~ This bit can be set directly by the host, or 1ndtrect1y
by BINIT (bus 1n1t1ahzat10n sxgnal)

For mdexed regxsters these blts select one of exght

.channels

3.2.2.2 Receive Buffer (RBUF) A read from ‘base + 2’is interpreted by the DHQI 1 hardware asa
read from the receive FIFO. Therefore RBUFis a 256-character register wrth a l-word address. The
least-significant bit (LSB) of the character is in bit 0.
RBUF (READ BASE +2)

»1,"3_

R ] R|R|RIR|[R]R/|R

R| R

([
N

DATA

~ VALID
|

FRAMING

"OVERRUN

ERROR

PARITY

11T

CHARACTER

LINE NUMBER
e
|

R | R

RECEIVED

RECEIVE

| ERROR
|

QR
DATA SET

|
(FROM HIGH BYTE

STATUS FLAGS OF STAT)

ERROR

R
DIAGNOSTIC INFO

‘Bit

,Name’

| Description

DATA.VALID

This
bit is set if there is data in the receive FIFO.

When this b1tis clear, the contents of RBUF <14:0>

(Data Valid) (R)

is not valid.

Afterself-teSt, diagnostic infOrmation is loaded into

_‘

the receive FIFO. Therefore, this bit is always set
after a successful master reset sequence.

OVERRUN.ERR

~ This bit is set if one or more previous characters of

(Overrun Error) (R)
|

the channel indicated by bits

<11:83> were lost

because of a full receive FIFO.

VOTE

The ‘all 15’ code for bits <14:12> is reserved. This
code indicates that RBUF <7:0> holds modem
status or diagnostic mformanon

13
12

' FRAME.ERR

(Framing Error) (R)_

PARITY.ERR

- (Panity Error) ( R)

This bit is set if the first stop bit of the received
character was not detected (also see RX.CHAR).

This bit is set if this character has a parity error, and if
parity is enabled for the channel indicated by bits

<I11:8> (also see RX. CHAR)

3-6

Bit

Name

‘< 11:8>

RX LINE

- (Recexve Lme Number) (R)
»

RX.CHAR

' <70>

(Received Character) ( R)

Descnpnon |

- These bits hold the brnary number of the channel on

which the character of RBUF< 7:0> was received,
|

or on which a data-set change was reported.

= 000. these eight bits contain
If RBUF< 14:12>
the oldest character

the

receive

FIFO.

The

- characteris good.

If RBUF<14:12> = 001. 010, or Ol1. these eight

bits contain the oldest characterin the recerve FIFO.

The character 1S bad.

If RBUF< 14:12> = 111, these eight bits contain

- diagnostic or modem status information. [n this case.

RBUF <0> has the following meanings.

Modem status in RBUF<7:1>

0
1

Diagnostic information in RBUF <7:1>

- If there is an overrun condition, the four-character
- UART receive buffer tor that channel will be cleared.
This data will be lost. A null character is placed in the
receive_FIFO, and R'BUF<_ 14> is set.

The DHQI11 does not have a break-detect»bi't‘. A line

break is indicated to the program as a null character

with F,RAME.E‘RR: set. and, overrun is_ clear.

3.2.2.3

Transmit Character Reglster (TXCHAR) - Smgle-character programmed transfers are made

“through the transrmt character register.

TXCHAR (WRITE BASE + 2)
15

1110

wilwlwlwlwliw]l|wl|w

TRANSMIT

' CHARACTER

DATA VALID

2£1238

3.7

Bit

Name

| TX.DATA.VALID

e Description

(Transmit Data Valid) (W)
-

When ;s’et,fl this bit ihstr.u_cts the DHQI1 to transmit

the character held in bits <7:0>. The bit is sensed by
the DHQI1, which then transfers the character, clears
the bit, and sets TX.ACTION..

TX.DATA.VALID
and TX.CHAR can be written
together. or by separate MOVB instructions.

<»7':O>

TX.CHAR

_(Transmxt Character) (W)

3.2.2.4

"This contams the character to be transmttted The

LSB is bit O.

Lme-Parameter Reglster (LPR) - This register is used to configure its associated channei

LPR (BASE + 4)

14 13

10
9

rRwrRW|RW[RWI[RW[RW|RW[rRW

TRANSMIT
SPEED

N O

STOP | PARITY

CODE

'RECEIVE

ENABLE

EVEN

SPEED

. DIAGNOSTIC
CODE *

CHARACTER

PARITY

LENGTH

DISABLE
-~

REPORTS

* OO NORMAL OPERATION
.
01 = SCREEN RECEIVED XON/XOFF CHARACTERS
FROM ENTRY INTO RECE!VER BUFFER IF

.0 AUTO IS SET

RE2719

Bit

Name

<15:12>

TX.SPEED

RXSPEED

This bit is set to 110] by MASTER.RESET (9600

, (Recexved Data Rate) (R/W)

STOP.CODE

(Stop Code) (R/W)

bxts/s) It defines the recexve data rate (Table 3-2).

This bit defines the length of the transmitted stop bit.
|

This bit is set to 1101 by MASTER.RESET (9600

(Transmitted Data Rate) (R/W) bits/s). It defines the transmit data rate (Table 3-2).

pumas

<118>

Descnpuon

l stop bit for 5-, 6-. 7-. or 8-bit characters B
2 stop bits for 6-, 7-. or 8-bit characters, or l 5
- stop bits for 5-bit characters

3-8

Bit

Name

Descnpnon

.~ EVEN.PARITY

)

The but is cleared by MASTER.RESET.

If LPR<5> is set, this bit defines the type of parity.

(Even Parity) (R/W)
|
|

,
= Even parity

O- = Odd panty

~ The bit is cleared by MASTER RESET.

PA RITY.ENAB

This bit causes a parity bit to be cIenerated on transmit.

(Parity Enable) (R-W)

»and checked and strlpped on receive.
1= Parrty enabled
0= Parxty dlSdbled

) 'The blt is cleared by MASTER RESET

—

‘<4:3‘_">
*

’CHAR.LGTH

.These two brts define the length of characters. The

Character Length) (R, W)

length does not include start, stop, and parity bits.

00 = S bits

0l = 6 bits

10 = 7 bits
[1 =8 brts

They are set to 11 by MASTER. RESET
<2:1>

DIAG

(Diagnost_’ic Code) (R/W)

Dlagnostlc control codes are are used by the host as

follows.

00 = "

Normal operation

01 = Causes the background momt:er program

(BMP) to report the DHQII status through
‘the receive FIFO.

<0>

Other codes are reserved

DISAB.XRPT

(Disable XON/XOFF

‘Reporting) (R/W)

XON and XOFF characters are reported on
all channels

1 = - If LNCTRL <_4>» is also set for a particular
channel. these characters are filtered from the

received data stream, to. relieve the host of the
need to do so

3-9

SRR AN

Bit

St R cars

... AR

Description

Name

On initialization, this bit is cleared. In order to read or
write to this bit, CSR
< 3:0> must equal zero.

VoTE’
An XONcode = 218

DC
=CTRL/Q. An XOFF
code =23;= DC3=CTRL/S. No other codes are
specified for the interface.

Table 3—2 Data Rates
Code

Data Rate
(Blts/s) 50

0.01

0010

110

- 0.08

0011

Error (%)

0000

0001
-

Maximum

0.01

134.5

0100

0.07

150

- 0.01

0101
0110
Ol11

300
600
1200

1000
1001

1010
1011

1800
2000

0.01
0:19

2400
4800

0.0l
0.01

1100
1101

7200
9600
19200

0.01

1110
1111

3 2.25

0.01
0.01
0.01

0.01
- 0.01

38400

0.01

Line-Status Register (STAT)
- The hxgh byte of this register holds rnodern status mforrnatxon

~ The low byte is undefined.
STAT (READ BASE+6)

13
‘R

DSR

8
R

R
" INDICATOR)

CTS

MDL
o

pCo
(RING

0 = MODEM SUPPORT PROVIDED FOR THIS LINE

1 = MODEM SUPPORT NOT PROVIDED FOR THIS LINE
~

3-10

......

Bit

Vame

15 |

,’ DSR S

(Data Set Ready) (R)

o DeSeription

ThlS bxt g1ves the present status of the Data Set_ |

Ready (DSR) signal from the modem.

| = ON

0 = OFF

NOTE

)

ln order to report a change of modem status, the

- DHQI11 writes the high byte of STAT into the low
~

12 -

byte of RBUF. RBUF
< 14:12>
= 111 indicates to
the host that RBUF<7:0> holds modem status
: mformanon instead of a recelved character -

(Ring Indicator) (R)

DCD

(Data Camer Detected) (R)

This bit gives the present status ofthe ng [ndicator
(RI) signal from the modem.

ThlS bit gives the preSent status of ’the Data Carrier »
Detected (DCD)- snznal from the modem.

| = ON
0 = OFF

)

CTS

(Clear to Send) (R)

This bit gives the present status of the Clear To Send

o (CTS) signal from the rnodem

1 = ON_

0 = OFF

3-11

Descnptmn

Bit

‘Name

MDL

Always reads as 0 for DHQll to indicate that the

‘

module has modem support capability.

(MDL Modem Support Low) (R)

NOTE

[tis only necessary to read the modem Support status

for one line, smce all the other hnes will have the same
semng

This bit’ is set to zero on t'acto_ry-issued‘ boards.

Reserved

3.2.2.6 Line-Control Reglster (LVCTRL) - The main functxon of thlS rezlster 1s to control the line
|

mterface

LNCTRL(BASE-+10)

15 14

11
12

R/W
_

RTS

08 07

RW
lrw | rRW [RW |RW ] AW | RW|R/W|RW||RW
A
A
A
A
A
i
A
A
A

'DTR

MAINTENANCE

MODE

LINK

TYPE

OAUTO

FORCE.

XOFF =

ENABLE

BREAK

ABORT

|AUTO
22442

~ Bit

Name

RIS

. Doscnptmn
-

(Request To Send) (R/W)

|
DIR

(Data Terminal Ready) (R/W)

This bit controls the Request To Send (RTS) sxgnal

| = ON

O = OFF

This bit controls the Data Terminal Ready (DTR) signal.
| = ON
== OFF

3-12

Bit

~ Description

‘Name

LINK. TYPE

‘This bit must be set if the channel is to be connected toa
‘modem. When the bit is set, any change in modem status

(Link Type) (R/W)

~ will be reported through the receive FIFO as well as the
|
| ,STAT register.

- If this bit is cleared. this channel becomes a

‘data-leads-only’ channel. Modem status information is
loaded in the high byte of STAT. but is not placed in the
receive FI FO

' <7:6>

MAINT

- (Maintenance Mode) (R, W)

| These bits can be written by the dnver or test proqrdms In
- order to test the channel.
‘.The_ coding 1s as follows:
Normal operation

- 00

Automatic echo mode — Received data is
looped back to the terminal (regardless of the

state of TX.ENA) at the data rate selected for
the receiver The received characters are

processed normally and placed in the receive
FIFO. Any data that the host attempts to
~transmit on this channel will be discarded by

~
-

the OCTART. The RX.ENA bit must be set
when operating in this mode.

10=

Local loopback — Data transmitted by the

~
|

host is looped back to the receive buffer. Data
~received from the terminal is ignored, and the
transmit data line to the terminal is held in the
mark condition. The data rate selected for the

transmitter is used for both transmission and
reception. The TX.ENA bit still controls
transmission in this mode. The RX. ENA bitis
ignored.

Remote loopback — In this mode. data

received from the terminalis looped back to the
terminal at a clock rate equal to the received
~

3-13

clock rate. The datais not placedin the receive
FIFO. The state of TX.ENA is ignored. The

- RX.ENA bit must be set on this channel.

-_-Name

~ Bit

R Descnptlon

5 c FORCE.XOFF

o This bit can be set by the program to mdxcate that this

- (Force XOFF) (R/W)

channelis congested at the host system (for example, if the

typeahead buffer is full). When it sees this bit set, the
DHQI1 will send an XOFF code. Until the bitis cleared.
XOFFs will be sent after every alternate character received
on this channel. When the bit is cleared. an XON will be
sent unless IAUTO is set and the receive FIFO is critical.

This bit is the auto-flow control bit for outgoing
|
o
OAUTO
(Outgomg Auto Flow) (R W) ~ characters. When set, if RX.ENA is also set. the DHQI!!

will automatically respond to XON and XOFF codes

received from a channel.. The DHQI!! uses the TX.ENA

bit in TBUFFAD2 to stop and start the flow. If
DISAB.XRPT is also set, XON/XOFF codes are not
entered in the receive FIFO.

BREAK“’ |

(Break Control) (R/W)

~If set, this bit forces the transmitter of this channel to the
spacing state.

If this bit is set whilea character is being transmutted,

transxmssxon 1S completed before breakis asserted on the
~ line.

Transmission is re-enabled when the bit is cleared.

NOTE

If the lineis idle, there may be a delay of up to 170

microseconds between writing the bit and the channel
changing state. If a character is already being
- transmitted by the OCTART, the BREAK signalwnll

be transmitted lmmedlately afterwards.

RX.ENA

* (Recexver Enable) (R/W)

channel is | enabled.
If this bit is set, this receiver
|
|

If this bit is cleared when thxs channel IS assembhng a
- character, that character s lost.

The bit is cleared by MASTER.RESET.

I - TAUTO
|

(Incoming Auto Flow) (R/W)

This is the auto-flow control bit for incoming characters

If it is set, the DHQ!1 will control incoming characters by

transmitting XON and XOFF codes

Bit

Name

Description

If the receive F IFO becomes more than three--quarters Full,

the DHQI!1 will sendan XOFF code to that channel, and
to any other channel which receives a character and has
the IAUTO bit set. When FIFO becomes less than half
full, an XON will be sent to all channels which had

'prev1ously been sent an XOFF

0
|

TX.ABORT

(Transmit;Abort) (R, W)

This bit is set by the dnver program to halt data
transmission. If a DMA transfer wus in progress, the
DMA
address and
count
registers
(TBUFFADI,
"TBUFFAD?. und TBUFFCT) will be upduted to retlect
the number of chamcters which have been trunsmitted.
The transter can be continued by clearmz TX.ABORT.
and then setting TX.DMA. START In TBL FFAD2. \o

characters wxll be lost.

[f DMA is not in proeress no acuon is taken.
When an abort sequence has been completed the DHQI [
will set the TX.ACTION bit :n the CSR. If the transmitter

interrupt is enabled. the provram will be interrupted at the

transmxt vector.

The program must make sure that TX ABORT is clear

before setting TX.DMA.START. otherwise the transfer
will be aborted before any characters are transmitted.

The bn is cleared by MASTER. RESET
3.2.2.7 Transmit Bufl‘er Address Reglster Vumber 1 (TBUFFADI) TBUFFAD1 (BASE + 12)

| '15 14 13 12

11 A1o

rw [Rw [rw | Rw [Rw | Rw

[Rw | Row

768 5 4
3
Rw

[Rw

[Rw [Rw
| Rw

[Rw | Row | Row

T 1T

TXMIT DMA ADDRESS

(BITSOTO?S)

‘B,i.t
<15:0>

Name |

Descnptloh

TBUFFAD<150>

Bits <150> ofthe DMA address

(Transmit Buffer Address [Low])

(R/W)

3-15

3.2.2.8

Transmit Buffer Address Reglster Number 2 (TBUFFADZ) -

TBUFFADZ (BASE + 14)

_1'5’14

|
R’W

OMA

START

ENABLE

- Bit

Name

TXMIT DMA ADDRESS
(BITS 16 TO 21)

Description '

TXENA

(Transmxtter Enable) (R/ W) |

»When this bit is set, the DHQH will transmit all
characters.
|

When this bit is cleared, the DHQI! will only
transmit internally generated flow-control characters.

The bit is set by MASTER. RESET
In the OAUTO mode, thxs bxtIS used by the DHQl |
to control outgomg characters.
|
7

TXDMASTART

}»‘;(Transrmt DMA Start) (R/W)

| "Thxs bit is set by the host to start a DMA transfer
The DHQI1 will clear the bit before returmng
'TX.ACTION.

The bit is cleared by MASTER.RESET.

| NOTE
After settmg tlus bit, the host must not wnte to

TBUFFCT, TBUFFADI, or TBUFFAD2 <7:0>

~until the TX. ACTION report has been returned.
<5:0>
|

TBUFFAD<21:16>
(Transmlt Bufi'er Address [ngh])

(R/W)

Bits <21:16> of the DMA address. Before a DMA
transfer, TBUFFADI
and the low byte of
TBUFFAD? are loaded with the start address of the
- DMA buffer. This address will be continuously
changmg during a DMA transfer and has no
meaning. Once TX.ACTION has been returned the
register contains the final DMA transfer address.

3229 Transmit DMA Buffer Counter (TBUFFCT) TBUFFCT (BASE + 16)

15 14

12 11

{rw [rRw [rRw |rw [Rw

DMA CHARACTER COUNT

(WHEN VALIID,HQLD_S NO. OF CHARS STILL
TO BE SENT)

Bit
<15:0>

\Jame

Descriptibn |

TX.CHAR.CT

This wordIS loaded wrth the number ofcharacters to

(Transmit Character Count) (R;W)

be transferred by DMA

| The nurnber of characters IS specxfied as a 16- b1t
“unsigned 1nteger

After a DMA transfer hus been aborted this locanon

will hold the
transferred

number

of characters

See also the previous NOTE.

stlll to

33 PROGRAMMING FEATURES
3.3.1 Imtlahzatlon
|
The DHQI11 is initialized by its on-board sequencers

Imtlahzatlon takes place after a bus reset sequence or when 'the 'ho»st' sets CSR<5>

_(MASTER RESET).

i Before starting 1mt1allzatlon the on-board sequencers perform a self-test The results of thxs test are
reported by eight diagnostic bytes in the receive FIFO.
~ The DHQll state, after a successful self-test 1s as follows

h L. Erght dxagnostrc codes are placed in the receive F IFO}
2.

The dlagnostlc fail bit (CSR< l,3>) ls clear

3. All channels are set for:

Send and receive 9600 bits/s

'b. Eight data bits

| ¢c.. One stopbit
d. 'No parity |

~e.

Parity Odd ._

‘f. | Auto-fliow'ofi'
g. ~ Receive disabled

Transmit enabled

No break on line |

No loopback

Link type set ’to data'-lead‘s-only

DTR and RTS off

m. DMA character counter zero

n. | DMA start address registers zero

o. TX.DMA.START cleared
p. TX.ABOR'f cleared
q.

Auto-flow -reports enabled

318

—

o
e

- The DHQl I clears the MASTER RESET bit (CSR<5>) when 1n1t1ahzatlon and self-test are complete

>'332 Configuranon

After DHQI11 self-initialization, the dnver program can configure the DHQll as needed ThlSi1s done
through the LPR and LNCTRL reglsters
|

'The line characteristics for a channel can be set up by wntmg to the LPR and LNCTRL reglsters
| -assocxated with this channel These are:
o
o

Transmit spfieed -

| 0 »Receive speede Number
of stop bits

@ | Parity type or parity disabled
®

Character le‘ngth |

Flow-control c‘haracteristlcs o

o
o

Normal Oor maintenance mode'
R_eceiver enable/disable |

yModem or data‘-leads-only -

NOTE
If RX. EN A is reset whxle a recexved characteris bemg
| assembled that character mll be lost

3 3 3 Transnuttmg
|
|
|
Each DHQll channel can be setup to transfer the characters by DMA or under program control

1 33.3.1

DMA Transfers - Before setting up the transfer of a DMA buffer, the program should make

sure that TX.DMA.START is not set. TBUFFCT TBUFFADI and TBUFFAD2 should not be
written unless TX DMA. START1S clear
S
|

Transmlssron will start when the program sets TX DMA START The size of the DMA buffer and its
~start address, can be written to TBUFFCT, TBUFFADI, and TBUFFAD?in any order, provided that
~ the TX.DMA start bit (TBUFFAD2< 7>)is not set. However, TBUFFAD?2 contains TX.ENA and
TX.DMA.START, so it is probably simpler to write TBUFFAD?2 last By usmg byte operations on thlS |
regxster TX.ENA and TX DMA START can be separated
|

The DHQ!! will perform the transfer, and set TX.ACTION when it is compl'ete If TXIE is set, the
~program will be interrupted at the transmit vector. Otherwise, TX.ACTION must be polled.
- TX.ACTIONis not returned until the UART has completely transmitted the last character of the DMA
bufi'er |
.

3-19

| To abort a DMA transfer, the program must set TX ABORT. The DHQll will stop transmission, and |
update TBUFFCT, TBUFFADI, and TBUFFAD2<7:0> to reflect the number of characters which
have been transmitted. TX.DMA.START will be cleared. If TXIEis set, TX.ACTION will interrupt the
program at the transmit vector. If the program clears TX. ABORT and sets TX.DMA. START, thetransfer can be contxnued W1thout loss of characters

If a DMA transfer fails because of a host memory error, the transmission wfll be terminated.

TBUFFADI and TBUFFAD?2 will point to the failing locatlon TBUFFCT will be cleared.

3.3.3.2

Programmed I/O - Single characters are transferred through the channel TX.CHAR register.

The character and the DATA. VALID bit must be written as definedin Section 3.2.2.3. Note that the
character and the DATA.VALID bit can be written by separate MOVB Instructions.
When the DHQI11 removes the character from TX.CHAR, it returns TX.ACTION. This will generate
an mterrupt if TXIE IS set.
|
NOTE |
In single-character mode, TX.ACTION is returned
when the DHQ11 accepts the character, not when it

has been transmitted. Each channel can buffer up to
three characters. Therefore, if line parameters are
changed immediately after the last TX.ACTION of a
‘message, the end of the message could be lost unless

three null characters are added to the end of each

single—character programmed transfer message.
- 3.34

Recemng

Received characters, tagged with the channel number error information and DATA.VALID, are placed

in the receive FIFO. RX.DATA.AVAILis clear when the receive FIFOis empty. When a characteris put
into the empty receive FIFO, the DHQI11 sets RX.DATA.AVAIL. A receive interrupt is generated if

RXIEis set. RX. DATA.AVAIL stays set while thereis valid datain the receive FIFO. Itis recommended
that the receive character routine continues to read characters from the recexve FIFO unnl
DATA VALIDis clear.
|
|
|
|

NOTE

The mterrupt is

dynamlc

ransed as

RX.DATA.AVAIL is set after RXIE, or as RXIE is
set after RX.DATA.AVAIL. If the interrupt routine
does not empty the receive FIFO, RXIE must be
- toggled to ralse another mterrupt

If RXIE is not set the program must poll RBUF often enough to prevent data loss
3.3.5 Interrupt Control
The DHQll provides one of two vector addresses dunng a bus mterrupt sequence The receive vector
addressis the address set up on the vector address sw1tches The transmit vector addressis the receive

- vector address + 4.

3-20

The recexve 1nterrupt vector 1s generated when

RXIE is set and acharacteris placed 1nto an empty recexve FIFO

RXIE is changed from 0 to 1, and the_ receive FIFO contains one or more characters.

The transmit interrupt vector is generated when:

‘ e TXIE is set and TX.ACTION becomes set

) o | TXIE is changed‘from 0to | ‘While V‘TX.ACTION' is set

NOTE

Up to- 16 TX. ACT ION reports are bufi'ered It is

~ therefore recommended that your program reads the
~
CSR until the TX.ACTION bit becomes clear,
otherwnse TX.ACTION wrll ‘be lost.

At the two vectors, the host must provxde the addresses of suitable routmes to deal thh the above
| condmons

336 Auto XON And xon-‘ |
XON and XOFF characters are commonly used to control data flow on commumcat1ons channels To

“use this facthty, interfaces must have suitable decodmg hardware or software

A channel using flow control that recetves an XOFF stops sendmg characters untll it receives an XON
If the receive F IF O becomes more than three-quarters full the DHQl 1 will send an XOF F code to that

- channel, and to any other channel which receives a character and has the IAUTO bit set. When FIFO
becomes less than half full, an XON w1ll be sent to all channels which had prevrously been sent an
- XOFF
The DHQI11 automatxcally controls character flow when programmed accordmgly (auto- fiow) Four'
bits control th.lS function:

e 1AUTO

LNc'rR_Lf<1_>«-“z

FORCEXOFF — LNCTRL<5>

OAUTO

— LNCTRL<4>

* DISAB XRPT — LPR<0>
,IAUTO and FORCE.XOFF both controlmcomxng characters IAUTO1S an enable bit Wthh allows
the level of the receive FIFO to control the generation of XOFF and XON characters. The

_ F ORCE XOFF

3.3, 6. l

bitis a direct command from the program to control the mcomxmg data stream

IAUTO
- The DHQll hardware recogmzes when the receive- F IFOis three-quarters full and

“half full. The logic uses these states for auto-flow control.

321

Each channel hasa separate IAUTO bit. If there are 191 or more characters in the receive FIFO, and a
characteris received on a channel with IAUTO set, an XOFF characteris sent. If the channel does not
respond to the XOFF, the DHQI11 will send another XOFF in response to every alternate character
received. An XON will be sent when the receive FIFO contains less than 128 characters, unless the
FORCE.XOFF bit for that channel is set. XONs are only sent to channels to whrch an XOFF has
previously been sent.

By msertrng XON and XOFF characters Into the data stream, the program can perform flow control

-dlrectly However, if the DHQll 1S 1n IAUTO mode the results W1ll be unpredrctable

In IA UTO mode, if RX.ENAis set, XON and XOF F characters wrll be transmrtted even if TX E\IA1S

cleared

3 3. 6 2 FORCE XOFF When FORCE.XOFF is set the DHQI!1 sends an XOFF and then acts as if
[IAUTOis set and the receive F IFO is critical (was three-quarters full, andis not yet less than half full).
When FORCE.XOFFis reset, an XON will be sent unless the receive FIFOis critical and IAUTOis set.

33.63 OAUTO - If the program sets OAUTO, the DHQI1 will automatically respond to XON and.
XOFF characters from the channel. It does this by clearing or setting the TX.ENA bit

The program rnay also control the TX.ENA bit, so in thrs case it is 1mportant to keep track of recexved XON and XOFF characters

| Recerved XON and XOFF characters wrll always be reported through the receive FIF O, unless the

DISAB.XRPT bitis set. It is possible, during read-modify-write operatrons by the prograrn for the

DHQ!1 to change the TX.ENA bit between the read and the write actions. For this reason, if DMA

| transfers are started while OAUTO 1S set, it is advisable to write to the low byte of TBUFFAD2 only.

3.3.6. 4 DISAB XRPT - If DISAB. XRPTis clear, XON and XOFF characters will be processed as
normal characters and are entered into the receive FIFO. DISAB.XRPT allows the individual line
OAUTO bits to control whether XON or XOFF characters received on that channel are drscarded
When DISAB.XRPTis set and OAUTO is set, this filterrngis enabled
|

NOTES |
1.

When checking for flow-control characters, the
DHQI11 only checks characters which do not
contain transmission errors. The parity bit
is
stripped, and the remaining bits are checked for
XON (214) and XOFF (23,) codes.

Auto flow-control does not absolutely guarantee
that overrun errors will not occur. These errors
may still occur if the transmitting devices do not
respond to the XOFF 1mmed|ately

3. 3 7

Error Indication

Four bltS 1nforrn the program of transnnssron and receptron errors.

TXDMA.ERR

—

CSR<I2>.

3.22

PARITY.ERR

—

‘e FRAMEERR
e

RBUF<I2>

— RBUF<I3>.

OVERRUN.ERR — RBUF<14>.

RBUF< '14:12»> also identify a diagnosticor modem status code.
3.3.8

Modem Control

Each channel of the module provides modem control bits for RTS and DTR. Also on each channel are

modem status inputs CTS, DSR RI and DCD These bits are used for modem control (see Sectlon»
|

3.2.2.5).

CTS, DSR, and DCD are sampled every 10 ms. Therefore, for a change to be detected, these bits must
stay steady for at least 10 ms. Rl is also sampled every 10 ms, but a change is not reported unless the newstate is held for three consecutive samples. Modem signals must be coordinated under program control;
thereis no hardware modem control logic. Modem status change reports are placedin the receive FIF 0
only if LINK.TYPE is set, but any changes are updated in STAT irrespective of the state of
LINK.TYPE.

’Appendlx A gives more details of modem control

By clearing LINK. TYPE a channelis selected as a ‘data-lmes only channel Modem control and status

bits can still be managed by the program, but status bits must be polled at the line-status register.
Changes of modem status will not be reported to the program.

Status change reporting is done through the receive FIFO as follows.

When OVERRUN ERR, FRAME. ERR and PARITY ERR are all set, the eight low-order

If RBUF<O> =0, RB_UF<7:1> holds STAT < 15:9> (see_ Section 3.2.2.5)

bits contain either status change or dlagnostlc mformatton In this case:

o If RBUF <0>

’1, RBUF<7:1> holds diagnostic information (seeSec_tion 3.3.10).

-3.39 Mamtenance Pr
The host can set bits 7 and 6 of LNCTRL to allow each channel to be configuredin normal automatic

" echo, local loopback, and remote loopback modes. These modes allow an individual data channel to be
" looped back to the host, or to be looped back to the terminal to assist in 1solat1ng communication
problems
|

The host muSt provide suitable software to use these modes.,

33.10 Diagnostic Codes

3.3.10.1 Self-Test Diagnostic Codes— After bus reset or master reset, theDHQll executes a self—test
and initialization sequence. Durmg the sequence elght dxagnostlc codes are put in the receive FIF O, and
RX.DATA.AVAIL is set.

After an error-free test, DIAG.FAIL will be reset and the ‘dxagnostxc passed’ LED will be on. If an error

is detected, DIAG. FAIL will be set and the LED will be ofi'

13-23

)

3.3.10.2

Interpretation Of Self-Test Codes- The high byte of diagnostic codes in RBUF can be

interpreted as in Section 3.2.2.2, except that bits < 11:8> are not the line number. They indicate the

N sequence of the diagnostic byte, thatis to say, 0 = first byte I = second byte, and so on. Table 3-3 shows
the meanlng of each of the error codes.
Table 3-3

Code

(Octal)

DHQll Self-Test Error Codes

Test

bits <7:0>

201

»-

211

Self-test null code (used as a :_filler)

| »;

22'5" '.

—

| :OCTART error

RAM error

)

231

RTS-CTS-DCD error

235

DTR-RI-DSR error

All other error codes should be treated as an vundefined error.
~If bit 7 0 and bit 0

=1, then brts <35: 2> contain circuit revision mforrnatron

Bit 6 always reads 1 for the DHQll and 1nd1cates that the cxrcuxt contalns control and OCTART
chxps
|
|
|

Bit 1 mdicates to Which chip the information _refers: 0 = Control,*l .=,OCTART.'
After self-test the eight FIFO codes consist of SiX dxagnostlc codes and two cxrcurt revision codes If
there are less than six errors to report, null codes (201,) fill the unused places.

After an error-free test six null codes and two circuit rev1sron codes will be retumed

Self-test may be skxpped to shorten the tmtxahzatlon cycle (see Sectron 3.3 10. 3)The moduleis stxll tested, even if self-testis skipped. The reset delayis much shorter but test coverage IS
not affected; therefore skipping self-test is advantageous.
|

After sk1p self-test’ self-test, the erght FIFO codes consist of six diagnostic codes and two circuit
revision codes. If there are less than SIX errors to report 203, codes fill the unused places.

After an error-free test, six 203, codes and two circuit revision codes will be returned.

33.10.3 Skipping Self-Test — The following method
is used:

L
2.

The ‘program resets the DHQlI
The program waits 10 ms (t 1 ms) after 1i ssu1ng reset, and then attempts to write 0525253 to
any of the control reglsters except the CSR, within the next 4 ms.

3.
~

Following self-test, the DHQI1 hardware checks whether an attempt was made to write the
skip code to the registers during the 4 ms window after reset (see step
2 above). If an attempt

~ was made, the MASTER.RESET bitis cleared at 30 ms afterissuing a reset mstead of 1.2s.

The 1.2 s reset time was retained for companbxhty W1ththe DHVIIL.
NOTE

The program must not write to the CSR, or to the
control registers, during the period starting 15 ms
after reset, and ending when the MASTER.RESET
bitis cleared. Writing during this period could cause a
dxagnostlc fail condltlon

" 3.3. 104 Background Monitor Program (BMP) - The DHQI1 BMP loglc performs ‘background
self-tests by checking for OCTART Interrupts. One of two codes is returned to the receive FIFO

1. 305, — DHQII running
:

3078 — DHQI1 defective (also LED ofi)

A single dlagnostlc wordis returned to the receive FIFO. The low byte contains the diagnostic code. In
the high byte, OVERRUN.ERR, FRAME.ERR, and PARITY.ERR are all set to indicate that
bits<7:0> do not hold a normal character The line number (RBUF<11: 8>)

BMP normally only reports when it finds an error. However, the program can get a BMP report at any
time to check the DHQII Thisis done by setting DIAG (LPR <2:1>) of any channel to 01 The line
-number returned is that of the LPR used to request the ‘report.
‘
B

On completing the check BMP clears thrs 01 code The host should not write to the LPR of that channel

~until LPR <21> becomes OO

3.25

o
34 PROGRAMMING EXAMPLES
These programsare not presented as the only way ofdnvmg the opuon and are neither guaranteed nor
supported
|
|

- 34.1 Resettmg The DHQll ~
In the followmg example:

-. @

DIAGCis a routine to check the dlagnostlc codes It returns with CARRY set 1fit detects an

error code

| ®

The loop at l$ takes 1.2 seconds SO the programmer could poll through a timer or poll at
interrupt levei zero.

; A ROUTINE T0 RESET THE DHOii AND CHECK THAT IT IS FUNCTIONINC
; CORRECTLY.

DHGRES: :
L
L
‘
- MOV . %40,@#DHQCSR

1$:

BIT
BNE
CBIT
BNE

o
BT
SET MASTER.RESET AND

CLEAR INTERRUPT ENABLES.

1§
#20000,@%DHACSR
DIAGER

; WAIT FOR MASTER. RESET T0
; CLEAR.
.
' CHECK THE DIAGNOSTICS
; FAIL BIT.

#40,@sDHACSR
|

MOV

28:

MOV

JSR
BCS

. NOTE: TEST INSTRUCTION IS
; OK BECAUSE THERE ARE
:

; NO

#8.,RS

TRANSMIT.ACTS

; SET UP A COUNT.

@®RBUFF,RO

; GET NEXT DIAGNOSTIC CODE.

; PROCESS IT.
; CARRY SET - MUST HAVE

SOB

RS,2$

; GO BACK FOR NEXT CODE.

RTS

; RETURN
- CARD IS RESET.

BEEN AN ERROR.

wNe

;

DHGLY HAS FAILED TD RESET PROPERLY, SO HALT AND WAIT FOR

THE FIELD SERVICE ENGINEER

Wwa

PENDING.

PC,DIAG
DIAGER

DIAGER: HALT
BR

DIAGER

3-26

3.4.2 Configuration
- This routine sets the characteristics of channel | as follows:

1 | | Tra‘hsrrfit and téceive .é,t 306 bit‘s/s_
2.

Seven data bits with even pafity andvcne’ stol‘p bit

, Transrhitters and receivers enabled‘- i

| No ffiodem Aco.ri»tvlt'ol

- |-

\\\

{,"

No automatic flQw contro.l_.
MOV
|

=1 ,@sDHQCSR
|

MOV

)

; LOAD INDEX REG

;

%052560,@sLPR

MOV
MOVB

#4,@sLNCTRL
#200,@#TBFAD2+1

RTS

; RETURN
- CHANNEL 1 DONE.

WITH CHANNEL NO.

~; DATA RATE, STOP BITS,
; PARITY AND LENGTH.
; ENABLE
THE RECEIVER.
; ENABLE THE TRANSMITTER.

3-27

3.4.3 Transmitting
3.4.3.1

Smgle-Character Programmed Transfer - Thls1sa programto send a message on channel L.

The message (MESG) 1s an ASCII stnng w1th a null character as termmator
Pollingis used, but a TX. ACTION mterrupt could also be used.

This program would function on a DHQI!! with only this channel active. Otherwise it would lose

TX.ACTION reports of other channels. However, a program to control all channels would be too big to
use as an example
|

A ROUTINE TO URITE A MESSAGE TO CHANNEL { USING SINGLE-CHARACTER
MODE.
.,

“we

SINGOT::
MOV
|
i$:

»1,@8DHOCSR

LOAD INDEX REC WITH

MOV

*MESG,
RO

POINT
TO MESSAGE.

MOVB

(RO)+,@8TXCHAR

MOVE CHARACTER TO TRANSMIT

BEQ

MOVE
MOV
BPL
,BIC

TXI

CMP
BNE

CHANNEL NO.

BUFFER.
GO RETURN IF ALL CHARACTERS
GONE.
SET DATA VALID BIT TO START.

38
8200, @8TXCHAR+1{

WAIT FOR TX.ACT

~ @%DHACSR,
Ry
2

174377
R4

ISOLATE CHANNEL NUMBER.

#000400
R4
24

RTS

IGNORE THE TX.ACT IF IT IS

NOT OURS (SHOULD NOT HAPPEN).
GO BACK FOR NEXT CHARACTER.

3%:

HESC_

‘.

HESSAGE SENT

ASCIZ /A SINGLE-CHARACTER HESSAGE FDR CHANNEL 1/

- 3-28

3432 DMA Transfer —

; THIS PROGRAM SENDS A HESSAGE OUT ON EACH LINE OF THE DHOii Aflbiv:

; HALTS THE MACHINE HHEN ALL TRANSHISSIUNS HAVE COHPLETED

; THE MESSAGES ARE TRANSHITTED USING DMA HODE AND INTERRUPTS ARE

; USED TO SIGNAL TRANSMISSION COMPLETION.

i$:

28. RO

CLR

MOVB

Ri @ODHOCSR

MOV

*DMASIZ,@#TBFCNT

sDMANES, @8 TBFAD{
'#100200,
@8 TBFAD2

SET LENGTH OF MESSAGE.

SET LOWER 16 ADDRESS BITS.

CLR
MOVB

| RS
#100,@8DHQCSR+1L

CHP
BNE

HALT

~ BR

RO,1$

‘START DMA WITH TRANSMITTER

ENABLED (ASSUME UPPER ADDRESS

BITS ARE ZERO).
'POINT TO NEXT CHANNEL.
REPEAT FOR ALL LINES.

; RS IS USED BY INTERRUPT ROUTINE
; ENABLE TRANSMITTER INTERRUPTS.

'WAIT FOR ALL LINES IO FINISH.

*8.,RS

ALL DONE, SO STOP.

TRANSMITTER INTERRUPT ROUTINE.

RS IS INCREMENTED AS EACH LINE COMPLETES.

INC
SOB

SET UP THE INTERRUPT VECTORS.
INTERRUPT PRIORITY FOUR.
EIGHT LINES TO START.
START
AT LINE ZERO.

', SEL
THEECT
REGISTER BANK.

MOV

%200,@8TXPSH

‘s

WTXINT,@#TXVECT |

we W

MOV
MOV

wWE

MOV

wWs

DMAINT::

TXINT::
MOV
- BIT
BEQ

- INC
|

#100000,R0
4%
|

TXINT

DMAMES:
DMASIZ

; FLAG THAT ANOTHER LINE HAS FINISHED
|

RTI
HALT

; CHECK FOR (ANOTHER) TX,ACTION.
; IF NOT, GO RETURN AND WAIT.

|
5%

@eDHACSR,RO ; GET LINE NUHBER.OF FINISHED LINE.

5¢

; MEMORY PROBLEM

.ASCII (15)(12)(7)(7)(7)/SYSTEH CLOSING DOWN NQOuW/

.~DMAMES

.EVEN

3433 Aborting A Transmission —

; THIS ROUTINE IS CALLED
TO ABORTA TRANSMISSION (EITHER DMA OR
.

’

FIFO)

PROGRESS

ON A SPECIFIED LINE.

THIS ROUTINE MAKES THE

(RATHER RASH) ASSUMPTION THAT THERE ARE NO OTHER
; PROGRESS.
.

’

TRANSFERS

’

; ON ENTRY,
BNE

RO,RY
RO CONTAINS THECMP
IGNORE IT IF IT IS NOT (OUR
13
’
ASSUHPTIDN WAS URONG')
’
.

e
ws

; CLEAR DOUN THE ABORT FLAG
FOR NEXT TIHE

’

RTS

1,QOLNCT§L-'

BUFFER COHPLETELY ABORTED.
IF A DMA WAS IN PROGRESS, THE
DMA REGISTERS REFLECT UHERE
THE DHQii HAD GOT TO.

BIC

3-30

344 Receiving
; THIS ROUTINE PROCESSES RECEIVED CHARACTERS UNDER INTERRUPT

IF AN
; CONTROL.
XOFF
IS RECEIVED, THE TRANSMITTER FOR THAT
; CHANNEL IS TURNED OFF IF AN XON IS RECEIVED,
THE TRANSHITTER
; IS TURNED BACK ON. ALL OTHER CHARACTERSARE IGNORED

. THIS IS JUST AN EXAMPLE.

‘A BETTER UAY T0 PERFORH FLDH CONTROL 1S
5 TO USE THE AUTOMATIC CAPABILITIES OF THE DHLL.
.

CLR

SRXINT, @®RXVECT
#200,@8RXPSH
*8.,R0
R&

s
MOVB
BIS
INC
SOB

RO,1$

MOVB

#100, @#DHACSR

RTS

R4 ,@8DHACSR
#4,@8LNCTRL

MOV
MOV

RXAUTO:
:

ws W

'SET UP THE INTERRUPT vzcrons |
INTERRUPT PRIORITY FOUR.
ENABLE ALL THE RECEIVERS,
STARTING
AT CHANNEL ZERO,

. SELECT THE LINE.

; ENABLE THIS RECEIVER.
|
|
SET POINTER
TO NEXT CHANNEL.

’

; ENABLE
THE RECEIVER INTERRUPTS.

RETURN
- INTERRUPTS DO THE RESET.

3-31

. INTERRUPT ROUTINE TO DO THE MAIN TASK.
»

’

RXINT::

MOV
RXNXTC:
MOV
BPL
MOV

RO,-(SP)
@eRBUFF ,RO
RXIEND
RO,-(SP)

; SAVE CALLER’S REGISTERS.
e
|
; GET THE CHARACTER.
; IF NO DATA VALID, WE HAVE FINISHED.
3 CHECK FOR ERRGORS, nonzn AND

BIC

#107777,(SP)+ ; DIAGNOSTICS CODES .
RXNXTC

;

BIC

-o17ozoo RO

; REMOVE UNNECESSARY BITS.

BNE
SWAB
BIS
MOVB

= JUST IGNORE THEH (BAD PRACTICE)

RO
~
3 POINT TO THIS CHARACTER’S LINE.
£100,R0
~; (ADD THE INTERRUPT ENABLE BIT )
RO, e:nuacsa o

SWAB

- CMPB
BNE

#2{ R0
14

BISB
BR

PUT CHARACTER BACK IN LOUER BYTE

; WAS IT AN "XON°?
; NO - GO CHECK FOR AN "XOFF"

8200 ,@8TBFAD2+1
; ENABLE THE TRANSMITTER.
- RXNXTC
; GO CHECK FOR MORE CHARACTERS.

CMPB
BNE

823
RXNXTC

BICB
|

RXIEND:
|
MOV

RTI

; WAS IT AN °“XOFF"?
; NO - G0 CHECK FOR MORE CHARACTERS.

ceoo,earnrnnz+1 DISABLE THE TRANSHITTER
.

RXNXTC
5

; G0 CHECK FOR MORE CHARACTERS.

(SP)+,R0

o
; RESTORE THE DESTROYED REGISTER.

3-32

345 Auto XON And XOFF
I

THIS PROGRAM SENDS A MESSAGE OUT ON EACH LINE OF THE DH011 AND
; HALTS THE HACHINE WHEN ALL TRANSMISSIONS HAVE COHPLETED

’.l

’

; THE HESSAGES ARE TRANSHITTED USING DMA MODE, AND INTERRUPTS ARE

; USED TO SIGNAL TRANSMISSION COHPLETION

: AUTOMATIC FLOW CONTROL IS ENABLED ON THE OUTGOING
DATA.

’.
e

MOVE

BIS

R1,@#DHACSR
#24,@LNCTRL

SAUTOSZ,@8TBFCNT

®AUTOM
@8 TBFAD1
S,

MOV

#100200
@8 TBFAD2
,

CLR

R§

MOVE

cMP

BNE.
3¢

. HALT
BR

RO,1$

%100 ,@4DHACSR+1

8. R5
2%

wa
we
ws
Ws

INC
S0B

MOV
MOV

"~ CLR

#8.,R0
R

%Na

1$:

MOV

%200, @#TXPSH

~ sATOINT,@eTXVECT

NEe

MOV

WNEe

TXAUTO::

’

SET UP THE INTERRUPT VECTORS.

INTERRUPT PRIORITY FOUR.
EIGHT LINES TO START.

'START
AT LINE ZERO.

'SELECT THE REGISTER BANK.

'ENABLE AUTOMATIC FLOW CONTROL

ON THE TRANSMITTED DATA.
SET LENGTH OF MESSAGE.
SET LOWER 16 ADDRESS BITS.
START DMA WITH TRANSMITTER
ENABLED (ASSUME UPPER ADDRESS
BITS ARE ZERO).
POINT TO NEXT CHANNEL.
REPEAT FOR ALL LINES.

; RS IS USED
BY INTERRUPT ROUTINE.
; ENABLE TRANSMITTER INTERRUPTS.

’

3 WAIT FOR ALL LINES TO FINISH.
’

ALL DONE, SO STOP.

3-33

N
-e
W
“-s

IS INCREMENTED AS EACH LINE COMPLETES.
RS

-s

“was

TRANSMITTER INTERRUPT ROUTINE.

ATOINT::
)

MoV

BIT
BNE
INC

@eDHOCSR,RO
#10000,R0
43

; GET LINE NUMBER
OF FINISHED LINE.
; CHECK
FOR DMA FAILURE.

. ; GD HALT
- MEMORY PROBLEM.

5 FLAG THAT ANOTHER LINE HAS’FINISHED;

RTI

4%:

HALT
BR

. MEMORY PROBLEM

AUTOMS: .ASCII (18)¢12)(7)(7)(7)/SYSTEM CLOSING DOWN NOW/

AUTOSZ

=
.EVEN

.-AUTOMS

)

3-34

3.4.6 Checking Diagnostic Codes
; THIS ROUTINE CHECKS

THE

; DHG1L.

RO CONTAINS THE CHARACTER RECEIVED FROM THE

ENTRY,

; DHRL1.
ON EXIT,
; FOR FAILURE.

DIAGNOSTICS

CODES RETURNED

FROM

THE

THE CARRY BIT WILL BE CLEAR FOR SUCCESS,
.
|

SET
|

’

MOV

o
)

BIC

RO,-(SP)

; SAVE THE CODE FOR LATER.

CMP.

#070001,RO

#107776,R0

; CHECK THAT IT IS A DIAG. CODE.

BNE

DIAGEX

;

IF NOT, JUST EXIT NORMALLY.

MOV

(SP),RO

; GET THE CODE BACK.

.~ BITB

%200,R0

; CHECK FOR CHIP VERSION NUMBER.

BE@

DIAGEX

BEQ
CMPB

DIAGEX
#201,R0

CMPB

#203,R0

BEQG

DIAGEX

CMPB

BEQ

o
; SELF-TEST NULL CODE.

|
;

#305,R0

;

DIAGEX

|
cLC
DIAGXX:
MOV

RTS

DH@ RUNNING CODE.
|

)

'; AN ERROR CODE WAS RECEIVED, SO

~; SET THE CARRY FLAG.

(5P)+,RO

; ALL THE REST ARE ERROR CODES.

DIAGXX

DIAGEX:

R
SELF-TEST SKIPPED CODE.

SEC

’

; EVERYTHING 0K, SO CLEAR CARRY.
o
|
|
; RESTORE THE CHARACTER/INFO.

“

.
4.1

CHAPTER 4

TROUBLESHOOTING

SCOPE

‘This chapter explains how to isolate the cause of a communlcattons problem between the DHQll and

-the equipment to which it is connected.

42 PREVENTIVE MAINTENANCE

- No preventive maintenance is needed for this option. However, you should always ensure that all cables
are clear of danger, and that all the connectors are secure.

| ~ Make sure that all cables are clearly labelled 50 that you can easily 1dent1fy whrch channel number and
Wthh DHQll module are assocxated with each terminal.

4.3 TROUBLESHOOTING PRO’CEDURES
Troubleshooting procedures are to identify whether the problem is caused by:
®

The module

' A terminal

"0' The cabling and distribution panels

' First decrde whether the problemis assocxated with one channel, a group of four channels or all eight
channels

If all channels are faulty, run the user dlagnostlcs to test the module Also check whether your software |
has a driver for the DHQll

If a group of four channels are faulty,» check the BCOSL-xx cable connected to the module.

For single-channel problems (EIAf232'D):
\Mh—“//

Check for loose cables and connectors.

2. | Verlfy that the termmal is workmg correctly If necessary, swap it w1th another one.
3.
'

When a modemline is suspect check that the modemis correctly configured for modem
“signals supported by the DHQI1. Also check that the software dniver has the correct
| baud-rate settmg and that modem support is enabled for that line.
-

4 | If the problem cannot be solved, call DIGITAL erld Servrce
For s1ngle-channel problems (DEC423)

Check for loose cables and connectors.

N
2.

Venfy that the terminal is working correctly. If necessary, swap it with another one.

Disconnect the BC16C-XX cable from the drstnbutron panel, and connect it to the H3101
loopback connector
|
|

Type characters at the terminal connected to the suspect line. If characters are echoed back

when the H3101 is connected, the cables and terminal are working. If characters are not
echoed back, the fault lies with the cable connectlon to the termmal or w1th the terminal
itself.
=
|

5..

Rectify the cable or termmal fault if thereIs one. If not, make sure that the user dlagnostlcs
for the module run correctly

If the prOblem cannot be solved, call DIGITAL Fie{ld Service.

H3101 LOOPBACK
CONNECTOR

’

H3104

TQ TERMINALS

BC16C-XX

Flgure 4-1
4. 4

Troubleshooting DEC423 Installations

INTERNAL DIAGNOSTICS

‘Internal diagnostics run without intervention frorn the Operator There are two tests the self-test and the
background momtor program (BMP)

4.4.1
SeIf-Test
- The self-test starts immediately after the Q bus or module has been reset. [t performs a comprehenswe |
internal logic test but does not test the Q-bus interface. The DIAG.FAIL bit and the ‘diagnostics passed’
LED on the module give an indication of a successful self-test. The self-test also reports error or status
information to the host via the receive F IFO
|
-

The self-test has completed successfully if the LED is ON 1. 2 seconds after the self-test has been
initiated. The module is initiated by powering up the module, by resetting the module through the

program interface, or by a Q-bus initialization sequence. The LED is turned off while the self-test

‘sequencer 1s executing; it will flicker durmg this time. The duration of the OFF period depends on

whether or not the self-test was invoked usmg the self-test sklp feature of the program mterface but it

will not exceed 1.2 seconds

4-2

Self-test provides a high level of confidence that the majority of the rnedule Iogic 1sworking The user

diagnostics must also be used to test the Q-bus interface and verify that the switch settlngs on the module
|

sw1tchpacks are correct.

4.4.2 Background Monitor Program (BMP)
»
‘When the DHQ!1 is not doing other tasks, the BMP carries out tests on the module If an error 1s
detected, the BMP reports to the host via the FIFO, and also sw1tches OFF the dlagnosttcs passed’
|

LED.

By writing codes to the line-parameter register, the host can cause the BMP to report the status of the

device, even if an error has not been detected. This facilityis used if the host Suspects that the optlon s
faulty

NOTE

More information on the self-test 'and. BMP
dtagnostlcs is glven in Chapter 3 of this manual.

45 MlcroPDP-ll DIAGNOSTICS
4. 5 1

User-Mode Dlagnostlcs

These tests can be used by an untrained operator to venfy the basic operatlon of the Optlon User-mode
tests do not cause any disruption to data networks or devices to which the DHQI11 may be connected.
Such networks and devices do not have to be disconnected from the DHQII1 during the tests. The
chroPDP 11 system manuals describe how to load and run these diagnostics..
4.5.1.1 Runmng User-Mode Tests- All user-rnode tests are run by selection from the test menu
displayed when the user diagnostics are booted. See Chapter 2 for more details.

A MicroPDP-11 Maintenance Kit is avallable Wthh allows trained personnel to run individual

diagnostic programs under the XXDP + diagnostic monitor, and to configure and run DECX11 system
test programs. The XXDP+ functlonal dxagnostxc is VHQATM**. BIN and the DECXll module is
-

XDHV**0OBJ.

4.6

MlcroVAX I DIAGNOSTICS o

Diagnostics for MicroVAX II systems all run under the MtcroVAX Mamtenance System (MMS). The
MicroVAX II system manuals describe how to load the MMS into the MicroVAX II, and how to run
‘MMS diagnostics. All the tests can be run by selection from the test menus dxsplayed when MMS IS
booted.

- 4.6.1

User-Mode Tests

These tests can be used by an untramed operator to verify the basic operatlon of the option. User mode
“tests do not cause any disruption to data networks or devices to which the DHQ!1 may be connected. Such networks and devices do not have to be dlsconnected from the DHQll durmg the tests. See

Chapter 2 for more detafls

4-3

a7 FIELD-REPLACEABLE UNTTS (FRUs)
The FRUs are:

Reference No.
M3107

Item
-

Dual-height DHQl‘I module

BCOSLxx

Distribution panel
,

H3173-A
H3100

Active distribution panel

BCl6C-25

70.22775XX

For DEC423 Installations

H3104

‘F.llat cable, 40 conductor

For EIA-232-D Installations
'

'
-

Multiway cable
Cable concentrator

Power cable

APPENDIX A |

MODEM CONTROL

Al SCOPE

This appendix contains information useful to both the programmer _'and the engineer. It defines control

~ signals, describes typical modem control methods, and warns against likely network faults. A detailed
-example of auto-answer operation is included.
|
|
»
|

A2 MODEM CONTROL

‘The DHQ!1 supports sufficient modem control to permit full-duplex operation over the public switched

- telephone network (PSTN) and over private telephone lines. Table A-1 lists the control leads supported

by the DHQI11, together with an explanation of their use and purpose. In this appendix, the terms
modem and dataset have the same meaning. They refer to the device which is used to modulate and
demodulate the signals transmitted over the communications circuits.

Tinblé A-1 Modem Control Leads
Name

GND

EIA-22-D

~AB

V.24

102

TXD

~ 25-Pin

| |

,Signal:'Gr_o'imd. This is a reference level

for the data and control signals used at the

103

Definition

line interface.

From DHQII to modem.. This signal

contains

the serial

bit

stream

transmitted
to the remote station. -

RXD

104

From modem to DHQIL. This signal is
the serial bit

RTS

CTs

105

106

~ From modem to DHQI1. Indicates that
~

cCc

17 6

the

~modem’s carrier to be placed on the line.

‘DSR -

From DHQI! to modem. Causes the

stream received

modem from the remote station.

the modem has successfully placed its
carrier
on the line, and that data presented
- on circuit BA will be transmitted to the
‘communication channel.
-

From modem to DHQII. Indicates that

the modem has completed all call
establishment
functions
and
is
-successfully
~ connected
to
a
~ communications channel.
|

—
—————s
i

‘Table A-1

Name

EIA-232D V24

DTR

- CD

e
s

Modem Control Leads (Cont.)

Definition

25-Pin

| 1108/2 20

From DHQlI to‘raodem'. Indicates to themodem that the DHQI1 is powered up

~and ready to answer an incoming call.

DCD
RIL,
»

CF
CE

109
125

8 |

—

,-Frornrnodem to DHQll Indicates to the

DHQI!!1 that the remote station's carrier
- signal has been detected and is within
appropnate hmlts
|

Frommodem to DHQII. Indicates that2

_new incoming callis being received by the
modem.

The DHQ!1 modem control interface can be used in many applications. These include control of serial

line printers, terminal cluster controllers, and industrial I/O equipment, in addition to the more usual
- applications in telephone networks.
The use of the control leads described in Table A-1 is therefore
completely dependent on the application, although there are international standards which telephone
network applications should obey. There are no hardware interlocks between the modem control logic
and the transmitter and receiver logic. Program control manages these actions,
as necessary.

A subset of the leads liSted in Table A-1 could be used to establish a communications link using modems

~ connected to the switched telephone network. Ring Indicator (RI), Data Terminal Ready (DTR), and
Data Carrier Detected (DCD) are the absolute minimum requirements. In some countries Dataset

Ready (DSR)is also needed. Itis usually desirable, however, to implement modem control protocols
- which will operate over most telephone systerns in the world. Also, some protection should be included

to guard against network faults particulariyin apphcatxons such as dlal-up tlrneshanng systems Such

faults mclude

Makmg a channel permanently busy (hung) because of a misdialed connection frorn a
non—data statlon

) " Connectmg a new mcommg call on an m-use channel. Thls fault mlght occur, for example,

~after a temporary carrier loss, if the host systern assumed that the carrier was reasserted by the

ongmal caller

Modem control w1th some protection against common faults, and which is compatible with the

| telephone networksin most geographic areas, can be implemented by using all the signals listedin Table

~ A-1, in the way described by the CCITT V.24 recommendations. Section A.2.1 describes a method of _' _unplementmg a full-duplex auto-answer communications link through modems over the PSTN. It is

provided here only to show the operation and interaction of DHQI!1 modem control leadsin a typical
appllcatlon
|
|
|
:
|
A.2.1

Example Of Auto—Answer Modem Control For The PSTN

The system operator determines which DHQ1 1 channels should be configured for either local or remote
operation. Local operation implies control of data-leads-only, while remote operation implies that
- modem control will be supported. The host software will assert DTR and RTS together with the
- LINK.TYPE bit in the LNCTRL register for all DHQI11 channels configured for remote operation.
DTR informs the modem that the DHQ11 is powered up and ready to acknowledge control signals from

A-2

the modem. RTS1s asserted for the full-duplex mode of operatlon and causes the modem to place its
carrier on the telephone line when the modem answers a call. Link Type (LNCTRL <8>) enables
modem status information to be placedin the receive character FIFO, where it will be handled by an
interrupt service routine. Modem status changes are always reportedin the STAT regxster regardless of
- the state of LNCTRL <8>. The modem 1s now prepared to auto-answer an mcommg call

Dialing the modem S number causes RI to be asserted at the line interface. This informs the DHQl 1 that
a new callis being received. RI has to bein a stable state for at least 30 ms, or the change will not be
- reported by the DHQI11. Since DTRis already asserted, the modem will auto-answer theincoming call and start its handshaking sequence with the calling station. The time needed to complete the
handshaking sequence.can be in the order of tens of seconds if fallback-mode speed selection and
satellite links are involved. The modem will assert DSR to indicate to the DHQ11 that the call has been
successfully answered and a connection established.

NOTE
On some older types of modem used on the PSTN,
the opposite effect
is also true. The RI signal may be
~

very short, or it may not even occur if DTR was

previously asserted. When this type of modem
answers an incoming call, it asserts DSR almost
- immediately and deasserts RI at the line interface.
~

Programs must therefore expect RI or DSR or DCD
as the first dataset status change received from the
Amodem when estabhslung a connection.

As RTS was previously asserted, the modem’s carrier will be placed on the line when DSRis asserted.

‘When the modem has successfully placed its carrier on the line it will assert CTS. This indicates to the
| DHQII that it can start to transmit data. If the
i1ncom1ng callis the result of a misdialed number, a
carrier sxgnal may never be received. To guard against this, the host starts a timer when it detects RI or
DSR. Thisis usuallyin the range 15 to 40 seconds, within which time the carrier must be detected. When

- the modem detects the remote modem’s carrier signal on the line, it will assert DCD This 1nd1cates to.
| the DHQI1 that data1s valid on the RXD line.

The modem can now exchange data between the DHQI1 and the calling station for as long as DCD,
DSR, and CTS stay asserted. If any of these three signals disappears, or if RIis detected during normal
transmission, a fault conditionis indicated. A change of state of any of these signals causes an interrupt
through the receive FIFO.
»

The handling of the fault conditions now becomes country-specific, since some telephone systems

tolerate a transient carrier loss, while others do not. In the USA it is usual to proceed with a call if carner
-

resumes within two seconds. In non-USA areas it is possible for telephone supervisory signals, such as

dial-tone, to be misinterpreted by the modem as a resumption of carrier. In this case the host program
‘would assume that the connection had been re-established to the original caller and would cause a
‘hung’ channel. To prevent this, DTR should be deasserted immediately after the loss of DCD, CTS, or
DSR, to abort the connection. DTR should stay deasserted for at least two seconds, after Wthh timea
new call could be answered

A-3

\--”//

APPENDIX B
F LOATING ADDRESSES
B.1 FLOATING DEVICE ADDRESSES
|
On Q-bus systems a block of addressesin the top 4K words of address space is reserved for options w1th

floating dev1ce addresses. This range is from 177600105 to 177637768

| Opthl‘lS Wthh can be asmgned floatmg device addresses are hsted in Table B-l Thxs table gives the |
sequence of addresses for both UNIBUS and Q- bus optlons F or example the address sequences could
be:
|
A

DHIl
DQIll

DU11/DUV1I

and so on.

Having one list allows us to use one set of configuration rules and dné configuration program.

Table B-1 Flo_ating Device Addrsss Assignm‘ents
Rank

Device

DQII gap

4
4

10
10

17760040
17760050

17760060

17760070

DUI1, DUVI1I gap
DUPIlgap

~N O3

LKIIA gap
DMCI11/DMRI11 gap

9
10

Address

Modulus
Octa)

D11 gap

DHI1 gap

Size
_(Decimal)

DZ11/DZV11/DZS11/DZ32

gap
KMCIl1 gap

N
4

LPPI1 gap

VMV2I gap

10
20

10 ***

10
10

410

17760010

17760020

17760030

17760100

ST
17760110
17760120

17760130

VMV3I gap

DWR70gap

RL11, RLV11 gap
LPA11-K gap

4
8

10*
20*

17760160
17760200

KWIl-Cgap

17760210

VSV2lgap

4
RXII/RX211/RXVII/RXV2]
4
gap

10
10*

17760140

17760150

17760220
17760230

‘Table B-1

Rank

Device

DRII-Wgap

DRI11-Bgap

Floating Device Address Assignments (Cont.)

- Size

(De‘cimal)

Modulus

(Octal)

’

40
4

10 *

Address

17760240

17760250

DPVII gap

DMPII gap

>3
24

ISBIl gap
DMVII gap

17760300

3
4

DEUNA gap

17760320

10 *

17760330

KDASO/UDASO/RQDX3gap 2

17760334

KMSII gap

17760360

20
4

17760400
17760404

17760420

26
27

DMF32 gap

VS100 gap

TUSl gap

3
2

KMVII gap

DHVll/DHUll/DHQll gap

17760260

17760270

17760340

17760440

The first device of this type has a fixed address. Any extra devrces have a floatxng address.

The first two devices of this type have a fixed address. Any extra devrces have a floatmg address

*** The Dle E and DZ11- F are treated as two Dles

The address a551gnment rules are as follows.

l. yAddresses, starting at 177600103 for Q bus systems are assxgned accordmg to the sequence of
-

Table B-I.

Option and gap 'addresses are assigned according to the octal modulus as follows.
®
-

Devices with an octal modulus of 4 are assrgned an address on a 4, boundary (the two
lowest-order address brts = 0)
|

@®
|

Devices w1th an octal modulus of 10 are assrgned an address on a 103 boundary (the
three lowest-order address bits = 0)
|
N

o ) Devxces with an octal modulus of 20 are assxgned an address on a 203) boundary (the
four lowest-order address bits = 0)

3.
~

Devnces with an octal modulus of 40 are ass:gned an address on a 40, boundary (the five
lowest-order address bits = 0)
,

Address space equal to the device's modulus must be allowed for each dev1ce which 1s

connected to the bus.

A l-word gap, assigned according to rule 2, must be allowed after the last device of each
type
This gap could be bigger when rule 2 is applled to the following rank

5. A l-word gap, assigned according to rule 2, must be allowed for each unused rank
on the list if
“a device with a higher addressis used. Thxs gap could be brgger when rule 2 is apphed to the

follawing rank

If extra devices are added to a system the fioatmg addresses may have to be reassrgnedIn agreement

with these rules.
- B.2

FLOATING VECTORS

Each device needs two 16-bit locations for each vector. For example a devrce w1th one receive and one

transmit vector needs four words of vector space.
The vector asslgnment rules are as follows:
1.

Each device occupies vector address space equal to ‘Size’ words. For example, the DLV11-J

- occupies 16 words of vector space. If1ts vector were 3008, the next available vector would be at
340,.

There are
no gaps, except those needed_ toalign an octal"modulus.
- Table B-2

Rank :

Device
B

Floatmg Vector Address Assrgnments

S Size

~ (Decimal)

Modulus
(Octal)

DCIl11

TUSS8
KLI11

4
4

10
10 **

DLI11-A

10 **

"DLI11-B-

10 **

2
2
3
4

DLV11-]
DLV11, DLVII-F
DP11
DMI11-A

16
4
4
4

10
10
10
10

~DNI11

DMI11-BB/BA

1
2

DHI11 modem control

DRI11-A, DRVI1I-B
‘DRI11-C, DRVI1
PA611 (reader + punch)

-4
4
8

10
10
10

4
4

10
10

-8
2

10
10

8
9
10
11

14
15

DXI11

DL11-C to DLVI1- E
DJl11

4
|

DHI11

VT40
VSVIi1

LPS11

iy v——y

|
|

LPDI1
DTO07

Table B-2 Floating Vector Addres_s ASSignmentS- (Cont.)
Device

~ Size

o
19

(Octal)

DV1l + modem control
LK11-A
:

4
4
4

6
4

10
10
10

DWUN
.
DMCI!1/DMRI1I
o
DZ11/DZS11/DZV11, DZ32
KMCl11
|
|

4
-4
4
4

10
10
10
10

DQIll

20
21
22

KWI11-W, KWV1]
- DUIL, DUVII
puprtt

23
24

25
26
27

Modulus

(Decimal)

LPPIl

10
10

VMV21

|
32

YMV3]
VTVOl

4
4

10
10

33
34

DWR70

RLI11/RLVI11

4 *

35
36

TS11, TU80
LPA1l-K

2
4

4
10

4
2

10
4 *

2
2

4
4

IP11/IP300

38
39

KWI11-C
<
RX11/RX211 RXVI11/RXV2l

40
41

42
43

DRI11-W
DRII1-B

DMPI11
DPVI11

ML“

ISB11
DMVI1l

DEUNA

-4

DME32

KMSI11
PCLI11-B
VS100

6
4

10
10

50
51
- 52
33

54
55
56
57

KDAS50/RQDX3

TU81

KMVIi1l

- KCT32
[EX

DHVI11/DHU11/DHQI!

4 e

4 ¢

4 *

4
4
4
4

10
10
10

Table B-2

Rank
|

Device
-

QNA
QVSS

64
65
66

DMZ32/CPI32(async)
CPI32(sync)

Floating Vector Address Assignments (Cont.)

.
|

|
|

V8§31

Size
(Decimal)

Modulus
-

12
12

12
4

4
4

4
10

LNVII

QPSS
QTA
DSvIl

2
2
2

4
4
4

. The firstvd_ev-ice of this 'ty.pe hés a fixed vector. Any extra devices have ‘a' ilioating-vector.
**

(Octal)

Ifa KLII or DLI11 is used as the console,»ijt‘ has a fixed vector.

*** MLI1 is a MASSBUS device which can connect to UNIBUS via a bus adapter.

APPENDIX C

AUTOMATIC FLOW CONTROL
C.1 OVERVIEW
|
|
Flow controlis the control of the flow of data along a communications line, to prevent an oversptll of
queues or bufl'ers or to prevent the loss of data Wthh the receiver is unable to accept.
The method of flow control adopted for the DHQI | is datastream-embedded ASCII control characters.

The control characters used are XOFF (octal 023) and XON (octal 021). XOFF stops transmission and
- XON starts transmission. The codes are transrmttedin the opposxte dtrectton to that of the data they
control.
|

~The DHQl 1 has one mode of operatton for transmitted data (received fiow-control characters) and two
modes of operation for received data (transmitted flow-control characters). Each mode can be enabled
on a ‘per channel’ ba51s Each direction of flow is discussed separately within this appendix.
C.2 CONTROL OF TRANSMI'ITED DATA
The transmitted-data mode of flow control is the snmplest of the three fiow-control modes of the
DHQll

When the DHQII receives an XOFF character fora particular channel the TX.ENA bit for that
channel is cleared. When this bit is clear, the DHQI! will not transmit any data on that channel;

however, internally generated flow-control characters will still be transmitted. When an XON character _
is received, the TX.ENA bit for that channel is set. Fxgure C-1 illustrates the operatton of the
transmltted data fiow control
-

c-t

XON

L
OQAUTO=0

RECEIVED
.

XON RECEIVED

OAUTO=1
XOFF
|

‘0AUTO=0

|RcvD

XOFF RECEIVED
‘0AUTO=0

XOFF

\\\5559veo
ap22s!

Figure C-1

Transmltted Data Flow Control

Only characters wrthout transrnxssron errors are checked for XON and XOFF codes The characters
have their parity blt str1pped before companson

| NOTE
For the automatic flow control to operate correctly,

‘the terminal must also recognize and respond to
flow-control characters.
,
|

~ The transmxtted data mode of flow control 1S enabled by setting OAUTO (blt 4 of the lrne control
reglster) and is drsabled by cleanng it. The default for this modeis disabled.

Received flow-control characters are processedin the same way as normal characters, and are placed

into the receive FIFO. This is not affected by OAUTO, but these characters can be filtered out by setting
'DISAB.XRPT. If DISAB.XRPT is set, you do not need a routine in your software driver to filter
flow-control characters frorn the data stream.

C.3 CONTROL OF RECEIVED DATA |
Received-data flow controlis slightly more complicated than transmitted-data fiow control. Therefore
the two modes of received-data flow control are described separdtely
|

C.3.1 Flow Control By The Level Of The Recelve FIFO
Occasionally, the program may not be able to empty the receive FIFO as fast as the received data is
filling it. Because the program ‘does not know how full the receive FIFO is, it cannot take action to
prevent data loss. To overcome this problem, the DHQI1 can be progrdmmed on a ‘per channel’ basis.
When the recewe FIF O becomes three-quarters full, an XOFFis sent to the channels from Wthh datais

recelved An XOFF character 1S then sent in response to every second recewed character until the
receive FIFO level drops below half full. An XON character is then transmitted. The operation of

~ receive FIFO-level flow control1s shownin Frgure C-2.

FIFO.CRIT=F

- FIFO.CRIT=F

FIFOGRIT=T

IAUTO=1

|
CHAR

AcvoD

SEND

XON

JAUTO=1

IAUTO=0

|AUTO=1

1AUTO=0 \

\JAUTO=0

‘

FIFOCRIT=F
R

FIFOCRIT=T

STATE

“

CHAR

RCVD

[ SEND

FIFO.CRIT=T

CHAR
RCVD

XON

FIFO.CRIT=F

CHAR

RCVD

IAUTO=0

FIFO.CRIT=F

RD2252

Figure
C-2 Receive FIFO-Level Flow Control

The receive F IFO-level flow-control mode is enabled by settmg JAUTO (bit 1 of the line control

after an XOF F is sent, but before the receive FIFO Ievel drops below half full, an XON 1s
i still sent.
NOTE

'FIFO.CRITis set (T) when the receive FIFOis being
filled, and contains 192 characters. It is cleared (F)
when receive FIFO reaches 127 characters as it is

being empned

C.3.2

Flow Control By Program Initiation

Occasionally, the program itself may need to invoke flow control, for example, when host buffers'

become full. To allow this, the DHQ1! hasa FORCE.XOFF bit (bit 5 of the line control register). When
the FORCE.XOFF bit is set, the DHQI transmits an XOFF character for that channel. A further
- XOFF bitis transmitted for every second character received on the channel afterwards. An XONis sent
when the FORCE.XOFF bit is cleared. Figure C-3 shows the operation of program--initiated flow

control The FORCE.XOFF bit 1s cleared by a DHQll reset sequence

FORCE.XOFF=1

CHAR RCVD

RCVD

FORCE.XOFF=1

FORCE.XOFF=0

~ CHAR RCVD

FORCE.XOFF=0

RD229%3

Figure C-3 'Program-Initiated Flow Control
NOTE

If the program sets the FORCE. XOFF bit and then

immediately clears it, the XOFF code may not be
transmitted. Thisis because thereis a delay of up to
350 microseconds before the DHQ11 detects the need
to send an XOFF. If the conditions for sending an
XOFTF clear before within this time delay, no XOFF
code. wnll be sent.

C-4

C.3.3 Mxxmg The Two Types Of Received-Data Flow Control
~ To calculate the effect of using the two modes, they should be logically ORed together an XON will not
be sent until both sources are inactive. An XOFF will be sent when FORCE.XOFF is set, even if
FIFO-critical modeis active and an XOFF has already been sent on that channel. If the receive FIFO
critical mode becomes active whilst FORCE.XOFF is set, then another XOFFIs sent in response to the

- next received character.

APPENDIX Df |

- GLOSSARY OF TERMS
- D.1 SCOPE
This appendix contains a glossary of terms used in this manual and in other DIGITAL
techmcal
manuals in this series.

D.2

The terms are in alphabetical order for easy reference

GLOSSARY

Asynchronous. A method of senal transmissmn in which data is preceded by a start bit and
followed

by a stop b1t

The receiver provrdes the mtermediate timmg to 1dent1fy the data bits.

| Auto-answer A facxlity of a modem or termmal to answer a call automaticallly
Auto-flow. Automatic flow control A method by which
means of special characters within the data stream.

Backward channel A channel Wthh transrmts m
Normally used for supervrsory or control srgnals

Base address
. BMP

The Q bus

address

of the first

the DHQI! controls the flow of data by
|

the opposrte dxrection to the usual data flow.

(lowest)

device reglster (CSR)

Background Monitor Program

CCI'IT Comité Consultatif International de Telephome et de Telegraphie

‘standards committee for telephone telegraph

An international

and data communications networks

| Dataset See modem

DMA Direct Memory Access. A method which allows a bus master to transfer data to or from systern
memory without using the host CPU.

- Duplex. A method of transrmttmg and receiving on the same channel at the same time
EIA. Electrical Industries Association.
CCITT.

American
|

orgamzation w1th the same function as the
=

FCC. F ederal Commumcations Commisswn ‘An Amencan organization Wthh regulates and hcenses

communications equipment

FIFO. First In First Out The term describes a register or rnernory from, which the oldest data is
removed first

. , Floatmg address. An address assrgned toan option which does not have a fixed address allocated The
~address is dependent on other floating address devrces connected to the bus

- Floating vector An mterrupt vector assigned to an option wh1ch does not have a fixed vector
allocated
The vector is dependent on other floating vector devices connected to the bus.

D-1

FRU. Field-Replaceable Unit.

IC. Integrated Circuit.
- I/O. Input/Output.

'LSB. Least-Significant
Bit.
o MMJ Modlfied Modular Jack.
Modem. The wordIs a contractron of MOdulator DEModulator Amodem 1nterfaces a terminal to
a transmrssron line. A modem is sometimes called a dataset

MSB

Most Significant Bit.

Mulnplexer A dev1ce which allows a number of mputs to share one common output

| ”Null modem. Acable which allows two termmals which use modem control 51gnals to be connected
| together directly.

only possible over short dlstances

| OCTART._ A smgle IC conta«mmg eight UARTs.

PCB. Printed Circuit Board.

| Protocol A set of rules Wh.lCh define the control and flow of datain a commumcatlons system

- PSTN. Pubhc Switched Telephone Network
Q-bus. A global termfora specific DIGITAL bus on which the address and data are multiplexed.
RAM. Random Access Memory.

RFI. Radio Frequency Interference.

ROM. Read OnlyMemory |
Spht-speed. A fac1hty of a data commumcattons channel which can transtt data at a dtfferent speed
from the received data.
- UART. Universal Asynchronous RCCCIVCI' Transmitter. A device which converts between senal and

parallel data used for transmrssron and receptron of senal asynchronous data on a channel.

- XOFF. A control code (233) used to disable a transmltter Specral hardware or softwareis needed forg
this functlon

XON A control code (21) used to enable a transnntter Wthh has been dlsabled by an XOFF code.

D-2

APPENDIX E
DHQll 0- BUs CONNECTIONS
Table E-1

Data/Addres’s
|

Data Control |
|

| VBDALO;L — 1.L

BDOUT.L* |

~ BRPLY.L
~
BDIN.L

Interrupt Control

BDMGI.L
- BDMGO.L
BSACK.L

BREF.L

System Control

BINITL -

Power Supplies

+5V

Grounds

- GND

GND
GND

‘GND

AE2

AF2
AH2

Iat. 'Req. Level 4
Int. Ack. Input
Int. Ack. Output

AJ2

Write Byte Control
I/O Page Select

" BDMR.L

+12vV.

BE2 — BV2
ACl — ADI
‘BCl — BFI

Synchronize Strobe

BIRQ.L

AU2 — AV2

Reply Handshake
Data Input Strobe

- BIAKI.L
- BIAKO.L

Pin Number

Data Output Strobe

BSYNC.L

BWTBT.L
BBS7.L

Fflnctioh |

Data/Address Lines

BDAL2.L — I5.L
BDALI16.L — 17.L
BDALI8.L — 21.L

DMA Control

Signal