AlphaStation 600 Series Technical Reference Information

This document, "AlphaStation 600 Series Technical Reference Information" (Part Number: EK-AS800-RM. A01, July 1995), serves as a comprehensive guide for system programmers developing operating system support code for the AlphaStation 600 Series workstations.

The manual details the system's design from a block diagram level down to individual registers, software/firmware design, and physical component layouts, with a strong emphasis on programming information.

Key aspects covered include:

• System Overview: The AlphaStation 600 is a high-performance deskside workstation based on the EV5 Alpha architecture. It supports Windows NT, OSF/1, and OpenVMS.

• ASIC Functionality:

  • CIA (Control, I/O, and Addressing) ASIC: Acts as the host bridge, managing address and command flow from the EV5 CPU, controlling memory (RAS/CAS signals, refresh), and interfacing with the PCI bus. It includes ECC generation/checking and scatter/gather TLB for DMA.
  • DSW (Data Switch) ASICs (4 chips): Handles the high-bandwidth 256-bit data paths between the EV5, memory, and CIA (for PCI data). It incorporates various buffers for victim data, I/O, and DMA.
  • GRU (General Register Unit) ASIC: Manages PCI interrupt logic, memory/cache presence detection, Flash ROM interface, and system reset signals.
  • PCI-EISA Bridge Chipset (Intel 82374EB ESC & 82375EB PCEB): Connects the PCI bus to the EISA/ISA bus, providing interrupt logic, timers, and DMA control.

• Memory Subsystem: Features two Memory Motherboards (MMBs) supporting 32MB to 1GB (expandable to 4GB) of 256-bit wide, ECC-protected memory. It includes a direct-mapped, write-back, ECC-protected Bcache (2MB to 16MB) partitioned across three SIMMs.

• I/O Subsystem: Utilizes a 64-bit PCI bus (32-bit addressing at 33MHz) and an EISA/ISA bus. It provides 8 PCI and (E)ISA slots (four PCI, three EISA, and one shared PCI/EISA slot). Dedicated I/O components include a PCI graphics card, an I/O Subsystem Module (with PCI-based SCSI/Ethernet and a PCI-PCI bridge), and an ISA-based Audio card.
• Addressing: Details the 40-bit physical address space mapping for CPU memory and I/O. It describes dense and sparse address spaces, scatter/gather address translation for DMA, and PC compatibility addressing including "holes" for memory-mapped I/O.
• Error Handling and Interrupts: Explains the system's robust error detection strategy across CPU, memory, and I/O buses (ECC, parity), how errors are latched, and how they trigger interrupts to the EV5 CPU. It includes detailed machine check logout data structures to aid software in handling and diagnosing errors.
• System Initialization: Outlines the power-up sequence and the two-stage firmware initialization process: the Serial ROM performs basic CPU, EISA bridge, and cache/memory sizing, while the Flash ROM (System ROM) handles more detailed device configuration and address map setup.
• System Coherency: Addresses crucial architectural considerations for maintaining data consistency across the EISA, PCI, and Alpha architectures, outlining software rules and hardware behaviors to prevent data inconsistencies and deadlocks.

The document is a foundational resource for anyone needing to understand the low-level workings of the AlphaStation 600 Series for system-level programming and debugging.