DECsystem 5800 System Technical User's Guide

This document is a Technical User's Guide for the DECsystem 5800 System, published in July 1990. It is intended for Digital customer service engineers for installation and repair, and for OEMs writing specialized applications or operating systems.

The manual provides a comprehensive reference on the DECsystem 5800, covering its architecture, components, and how to write software for it.

Key areas summarized in the document include:

• DECsystem 5800 System Overview: Introduces the system as a general-purpose computer based on a RISC (Reduced Instruction Set Computer) CPU, designed for multiprocessing (up to four processors). It highlights the use of a high-bandwidth internal system bus called the XMI bus for interconnecting processors, memory, and I/O adapters, and the VAXBI bus as the I/O interconnect.
• The XMI Bus: Details the XMI's electrical environment, protocol, and logic. It describes XMI addressing (1 Gigabyte, split into Physical Memory and I/O Space), data transactions (reads, writes, interlocked operations), interrupt mechanisms (INTR, IDENT, IVINTR), and bus integrity features like parity protection, ECC, and error recovery.
• KN58A/A Interface Module: Explains the module that interfaces the KN58A/B CPU to the XMI bus. It covers the CVAX maintenance processor, the second-level cache (256 KB), the XMI interface (XCPGA gate array), and support logic, including EEPROM for system parameters and SSC (System Support Chip) for various functions like timers and console communication. It also details initialization, self-test, and interprocessor communication via a Console Communications Area (CCA).
• KN58A/B CPU Module: Describes the computational core of the system, based on the MIPS R3000 RISC microprocessor and its R3010 Floating-Point Accelerator (FPA). It outlines the R3000's architecture (pipeline, memory management with TLB, on-chip caches) and the FPA's capabilities. It also explains R3020 Write Buffers and the first-level cache (128 KB), including their coherency and error detection.
• MS62A Memory Module: Focuses on the system's memory, a 32 Mbyte (up to 256 MB total) dynamic random access memory (DRAM) module. It describes its features, including ECC logic for error detection and correction, configurable interleaving, and control/status registers.
• DWMBA XMI-to-VAXBI Adapter: Explains this two-module adapter (DWMBA/A on XMI, DWMBA/B on VAXBI) that translates transactions between the XMI and VAXBI buses, facilitating CPU-initiated I/O and DMA transfers. It covers its registers, interrupt handling, and error reporting specific to the adapter.
• Power and Cooling Systems: Details the various components responsible for powering and cooling the DECsystem 5800, including power controllers, regulators, sequencers, blowers, and environmental sensors.

In essence, this document serves as a deep dive into the hardware and low-level software aspects of the DECsystem 5800, providing the necessary information for technical personnel to understand, repair, and program the system at a detailed level.