PDP-11/45, 11/70 Hardware Introduction Course Drawings

This document is a comprehensive collection of hardware introduction course drawings for the PDP-11/45 and 11/70 computer systems. It is organized into several sections covering different aspects of the hardware.

Key sections and their contents include:

• Asynchronous Line Interface (DL11-W): Detailed parts lists, logic schematics, ROM pattern specifications, cable assembly drawings (KL8-E, BC05C, BC03L), and an installation procedure outlining switch settings for address assignments, data format (data bits, parity, stop bits), and baud rates.
• Power System Engineering Drawings: Schematics for power control (861), wiring diagrams (H7420), power line monitor and 15V/5V regulators, and power fail circuits.
• KB11-C/D Block Diagrams: High-level architectural block diagrams for the KB11-D and KB11-C processors, illustrating ALU, registers, bus interfaces, and control paths.
• KB11-C Flow Diagrams: Detailed flowcharts (referred to as "Flows 1-14") that outline the microcode execution sequences for various CPU operations, including instruction fetch, control, floating-point and indexed source/destination modes, multiply, divide, execute-memory reference, break conditions, service sequences, and console operations (examine, deposit, load address, register examine/deposit).
• KB11-D and KB11-C Timing Logic: Schematics and parts lists for the timing generators, detailing crystal clocks, phase splitters, buffers, and timing state drivers.

The document provides a deep dive into the hardware components, their interconnections, operational logic, and control sequences, making it suitable for training or detailed technical reference for the PDP-11/45 and 11/70 systems.