DMA20 Memory Bus Adapter

The DMA20 Memory Bus Adapter is a critical interface control element designed for the Digital Equipment Corporation (DEC) KL10 system. Its primary function is to manage the transfer of 36-bit data words between the central processor's MBox and external destructive readout core memory.

Key Features and Capabilities:

• Data Transfer: It controls bidirectional data flow, using the SBus for communication with the MBox and four K Buses for connecting to storage modules.
• Memory Capacity: Equipped with four bus ports, the DMA20 can connect 1 to 16 storage modules per port, supporting a maximum capacity exceeding four million 36-bit words.

• Operational Modes: It supports three main modes, determining K Bus usage and storage module interleaving:

  • Four Bus Mode: The standard, highest-performance mode, utilizing all four K Buses for 4-way interleaved memory access, ideal for concurrent quadword (four-word) requests.
  • Two Bus Mode: A degraded mode that uses two K Buses for 2-way or 4-way interleaved access, offering a balance of performance and fault tolerance.
  • One Bus Mode: A non-interleaved, single K Bus mode for maximum memory availability during system degradation, albeit at reduced speed.

• Memory Cycle Types: The DMA20 handles three types of memory cycles:

  • Read/Restore: Reads data from memory to the MBox, then restores it to its original location.
  • Clear/Write: Writes data from the MBox to memory.
  • Read/Modify/Write: Reads data to the MBox for modification, then writes the modified data back to the same memory location (limited to single-word requests).

• Error Detection and Reporting: It continuously checks for address and data parity errors, as well as Nonexistent Memory (NXM) references. Detected errors are flagged in an internal error register and reported to the MBox, with diagnostic cycles available to retrieve error status and system information.

• Diagnostic Capabilities: The DMA20 offers diagnostic cycles for setting operational modes, testing data paths (including a loop-around mode to check MBox-DMA transfer without accessing core memory), and single-step operation at reduced clock rates for fault isolation.

The DMA20 system consists of 10 modules, including those for K Bus data buffers, address lines, SBus receivers/drivers, error logic, and request/response control. Its operation is synchronous with the MBox via an external clock and asynchronous with the core memory, using a request/response dialogue to manage memory access and prioritize requests.