MG10

This document is a maintenance manual for the MG10 Core Memory, providing a comprehensive description of its functional, physical, and operational aspects, along with detailed principles of operation.

The MG10 is a coincident current, ferrite core, 3-D, 3-wire memory system designed for DECsystem-10, capable of storing up to 131,072 37-bit words with a 1 microsecond cycle time. It operates asynchronously, using a "request/response" system, and supports up to eight access ports for various processors and data channels. Key features include priority logic for handling simultaneous requests, 2-way and 4-way interleaving to enhance performance, and data parity checking for error detection. The memory also incorporates features for smooth degradation, such as select switches for 32K memory banks, allowing for continued operation even with some core stack malfunctions.

Physically, the MG10 is housed in a standard PDP-10 cabinet, utilizing Quick Latch bus connectors for easy cable attachment. Its internal logic is divided into two main sections: the Core Memory and Control (CMC) and the Port Control and Core Interface (PCCI). The manual details installation procedures, including cabling for memory bus, AC power, and ground, and explains how to configure memory address, interleave, and port selection settings using switches on the maintenance panel.

The operation section describes the control and indicator panels, which manage input power, port addressing, memory sizing, and troubleshooting. The principles of operation delve into memory cycle timing (Read/Restore, Clear/Write, Read/Modify/Write), explaining how data is read, written, and modified. It outlines the core memory technology, including the 3-D 3-wire configuration, core array organization, X and Y line decoding, and current generation and sensing mechanisms (inhibit drivers, sense amplifiers, memory data latches, and stack charge circuits). The power system, comprising power control units and various voltage regulators, is also described, along with its power-on/off sequences, overcurrent, overvoltage, air-flow, and door interlock protection circuits.