KC10 BlockDiagrams Aug0

This confidential DEC document from August 1980, titled "Project Jupiter: KC10/2080 CPU," provides a detailed technical overview of the KC10/2080 Central Processing Unit's architecture, functional blocks, and various subsystems.

Key aspects covered include:

1. CPU Block Flow: A high-level diagram outlining the main components: MBOX (Memory Box), IBOX (Instruction Box), EBOX (Execution Box), and FPA (Floating Point Accelerator), and their interconnections via MD, L, and A buses.
2. CPU Pipeline: A multi-stage instruction pipeline operating in 22ns cycles, detailing stages like instruction fetch, effective address calculation, memory operand access, execution, and result storage, with different instruction timings (22ns, 44ns, 66ns).
3. Partitioning and Interfaces: The document shows the functional partitioning of units across FPA, EBOX, IBOX, and MBOX, and details the signal interfaces between the EBOX/IBOX and MBOX, as well as with the IOBOX and FPA, including control, diagnostic, and interrupt lines.
4. Clocking System: Descriptions of the CPU's clock phases (PH0-PH3) at 11ns intervals and the mechanism for stopping and starting the clocks.
5. Subsystem Details:
   • EBOX (Execution Unit): Detailed data paths, including registers, ALUs (main, shift, scalar), and control storage with early, intermediate, and late control levels.
   • IBOX (Instruction Unit): Covers instruction fetch (IPUT) stages, next address generation logic (for skips, jumps), the tag system (including tag buffer and page table cache), the Line Read File (LRF) for multi-stream instruction prefetching (streams A, B, C), and the vcode system for instruction validation.
   • FPA (Floating Point Accelerator): Shows the multiply array, Wallace Tree Adders, and a Modulo 3 checking algorithm for verifying multiplication results.
   • System Controls: Includes a FRU (Field Replaceable Unit) priority encoder for error handling, a comprehensive interrupt system with priority encoding, and logic for interval timers and account meters.
   • Flags: Detailed diagrams of various flag registers such as overflow, carry, trap conditions, and user/processor control unit flags.

The document primarily uses block diagrams, logic schematics, and timing charts to illustrate the design and operation of these components.