38

This PDP-X Technical Memorandum #38, dated January 19, 1968, outlines the parity control mechanisms developed for the Magtape IO Processor to ensure compatibility with IBM's 9-track magnetic tape equipment.

The document identifies two crucial types of parity operations:

1. Output Parity Generation: Required for creating 9-bit data output and Cyclic Redundancy Character (CRC) computation. The parity bit is generated as the most significant bit (bit 7) in a 16-bit register, alongside the 8 data bits (8-15).
2. Input Parity Checking: Involves making the full 9 bits read from tape available for CRC computation and verifying the tape's parity bit against the processor's internally computed parity for the 8 data bits.

Both input and output operations must be capable of using either even or odd parity, as specified by the Command Word.

The implementation relies on:

• Generating an 8-bit exclusive-OR (XOR) result from the Arithmetic Register's left half.
• Three dedicated signals provided by the Control Memory:
  • Input Parity Insert (IPI): Sends the parity track from the tape directly to the Carry Insert input.
  • True Parity Insert (TPI): Supplies the direct output of the 8-bit XOR to the Carry Insert.
  • Complemented Parity Insert (CPI): Supplies the logical complement of the 8-bit XOR output to the Carry Insert, enabling odd parity generation.

These TPI/CPI operations, combined with appropriate masking, can be performed within a single micro-instruction to manage even or odd parity for both data input checking and output generation. The document includes microcode examples and a truth table illustrating these parity input, testing, and generation processes.