M115

This document is a proprietary schematic diagram, copyrighted by Digital Equipment Corporation in 1967, for a circuit titled "8-3 INPUT NAND GATES M115" (Part Number M115-0-1, Revision C).

The schematic illustrates a circuit built around eight 3-input NAND gates. These gates are implemented using three "INTEGRATED CKT. DEC74ION" (part number 1905576), which likely contain multiple 3-input NAND gates each (e.g., a triple 3-input NAND gate IC, such as a 7410 equivalent). The circuit also includes three .01 MFD, 100V, 20% DISC capacitors (C1-C3) for power decoupling.

Power supply connections are indicated for +5V and Ground (GND), with -15V noted as "NOT USED." Important notes specify that Pin 7 on each integrated circuit (IC) is connected to Ground and Pin 14 on each IC is connected to +5V.

The document includes a revision history and a parts list for the integrated circuits and capacitors. It was drawn by m. Haller on April 20, 1967, and checked/engineered by April 21, 1967.