6206 MA, PC, IR Flip-Flops

The 6206 module is a component of the PDP-6 computer's control section, designed to handle one bit each for the Program Counter (PC), Instruction Register (IR), and Memory Address (MA) registers. It features three buffered 10 MHz flip-flops along with their associated gating circuitry. Two of these flip-flops are capable of generating a carry pulse. Each flip-flop is equipped with direct clear inputs, as well as either a gated set input or a normal set input (or both).

Key specifications include a 10 MHz frequency limit, a maximum output fall delay of 70 nanoseconds, and a maximum output rise delay of 50 nanoseconds. The module is built on a double-length board with 22 pins on the front and 18 on the back. Inputs vary by register and include direct clear, gated set, normal set, increment, and level inputs. Outputs provide register states (e.g., PC(1), IR(1), MA(1)), carry pulses for PC and MA, bus driver outputs for IR, and an indicator driver. Power requirements are -15V at 300mA, +10V(A) at 3.0mA, and +10V(B) at 140mA.