Principles of Operation

This document serves as Chapter 3 of a technical manual for the PDP-8/E system, providing an in-depth explanation of the processor's principles of operation. It is structured into eight primary functional sections: System Introduction, System Flow Diagrams, Timing Generator, Memory System, Central Processor, I/O Transfer Logic, Teletype Control, and Power Supply.

Key areas covered include:

• System Architecture: An overview of the PDP-8/E processor, which utilizes the OMNIBUS to interconnect eight functional modules.
• Data Paths: Detailed descriptions of how information moves through the system between memory, registers, and the CPU via the OMNIBUS, including the roles of the Memory Data (MD) bus, Data bus, Memory Address (MA) bus, and the Major Registers bus.
• Major States and Timing: An explanation of the four processor states (FETCH, DEFER, EXECUTE, and DMA) and the timing generator (M8330), which provides the necessary synchronizing signals and time states (TS1-TS4) for system operations.
• Instruction Flow: Comprehensive flow diagrams and logic descriptions for various operations, including the fetch state, operate microinstructions (Groups 1, 2, and 3), I/O transfers, and the interrupt system.
• Memory System: Technical specifications and operational theory for the MM8-E core memory, including the roles of sense amplifiers, inhibit drivers, current sources, and core selection decoders (using coincident-current 3-wire/3-D configuration).
• Control and Manual Operation: Descriptions of the Programmer’s Console and front-panel operations, including how manual functions like loading addresses, depositing, and examining data are performed through specific control logic.