KL8-J Terminal Control/Asynchronous Data Interface

Summary

This document provides the engineering specifications, installation/acceptance procedures, and technical logic diagrams for the KL8-J Terminal Control/Asynchronous Data Interface (specifically the M8655 module).

Key information includes:

• Purpose: The KL8-J serves as an interface between the PDP-8 computer (via the Omnibus) and various asynchronous external devices, such as serial terminals, teletypes (LT33/LT33D), and VT05 terminals.
• Operational Details: It facilitates serial data communication using both 20mA current loop and EIA (RS232-C) signaling. The interface includes double-buffering for efficient data transmission.
• Specifications: It covers baud rate selections (up to 9600), parity options, and data bit configurations. It also details power requirements, physical cabling, and specific signal pin assignments.
• Programming: The document outlines the instruction set for managing the interface, including clearing flags, reading buffer data, and status word monitoring (error detection for parity, framing, or overrun).
• Diagnostics: Includes procedures for testing the interface and ensuring correct installation using specific Maindec diagnostic software.