Pdp-8e Extended Memory Address Test (Eabe)

This document serves as the technical documentation and operating guide for the PDP-8e Extended Memory Address Test (EABE). The program is designed to verify that memory locations in systems equipped with 8K to 32K words of core memory can be uniquely addressed and tested.

Key aspects of the document include:

• Requirements: The program requires a PDP-8e or PDP-8a computer with at least 8K of memory.
• Test Methodology: It employs a series of four test routines that use core locations 5000 to 5177 as a buffer area, utilizing automatic program relocation to test all memory fields.
• Operating Procedure: It provides instructions for loading the program via the Binary Loader and configuring the system using the Switch Register (SR).
• Configuration: The Switch Register allows operators to control test execution, including selecting specific test routines, setting test behavior (such as halting on error or inhibiting printouts), and defining stack limits for memory testing.
• Diagnostics: The document explains how to interpret switch settings and error conditions, noting that failure to correctly address a memory location or a failure in the relocation check will trigger an error.