This document provides technical information for VARs, ISVs, and service providers configuring or adding features to Digital AlphaStation 200 and 400 Series systems. Both series are state-of-the-art workstations featuring DECchip 21064 or 21064A Alpha CPUs and the 21071-AA core logic chipset (cache/memory controller, PCI interface, data path).
Key shared features include:
Distinctions between the series include:
The document details system configuration (memory, mass storage, PCI/ISA expansion, jumpers), addressing schemes (cacheable, noncacheable, PCI sparse/dense memory spaces), I/O programming (flashbus, keyboard/mouse, TOY clock, Super I/O chip, interrupts), DMA channels, hardware interrupts (CPU, device, NMI, timer, HALTREQ, PCI), system power-up and initialization sequences, AlphaStation firmware (SROM, DROM, ARC, SRM features, LED/beep codes, console commands like ISACFG), fault management (error registers, machine check codes, error formats), and comprehensive connector and cable information, along with a list of system registers.
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