MM11-D/DP Core Memory User's Manual

This document is a user's manual (1st Edition, October 1976) for the Digital Equipment Corporation (DEC) MM11-D/DP Magnetic Core Memory, designed for use with the PDP-11 family Unibus.

The MM11-D/DP is described as a low-cost, low-power, and high-reliability core memory. Key features include:

• Capacity: 16,384 (16K) words, supporting 16-bit data (MM11-D) or 18-bit data with two parity bits (MM11-DP).
• Functionality: Operates as a slave device on the Unibus with a 1 µs cycle time (access times of 425 ns for D, 560 ns for DP with parity).
• Addressability: Its starting address can be set on any 8K boundary within the 124K Unibus address space, and it can even be configured to use a portion of the I/O page (124K-128K) in specialized applications.
• Interleaving: A notable feature is the ability to interleave two MM11-D/DP modules, assigning one to odd and the other to even addresses within a 32K block to effectively decrease memory cycle time through partially overlapping operations.
• Physical Components: It consists of a G652 hex multilayer motherboard (housing Unibus interface, timing, control, and driver/sense circuits) and an H222 hex stack (containing the core plane and temperature-sensing circuitry). The MM11-DP variant requires a separate M7850 Parity Control module.

The manual provides step-by-step instructions for installation, covering:

1. Unpacking the modules.
2. Address Selection using jumpers on the G652 module to define the memory's starting address and configure interleaving if desired.
3. Backplane Voltage Check to ensure correct DC power supply.
4. Module Insertion of the G652 motherboard and H222 stack into a Unibus backplane.
5. Cable Connection for the Unibus.
6. Parity Controller setup (for MM11-DP).
7. Diagnostic Acceptance Tests using specific DEC diagnostics (MM11-D/DP Diagnostics, Memory Exerciser, and DZQMB) to verify proper operation, including margin testing.