VAX 11/780 DW780 Unibus Adaptor Technical Description

This document is a comprehensive Technical Description of the VAX-11/780 DW780 Unibus Adaptor (UBA), published by Digital Equipment Corporation in May 1978. It provides a detailed overview at general, functional, and logical levels, serving as a resource for field service, manufacturing training, and reference.

The primary function of the DW780 UBA is to connect Unibus peripheral devices to the VAX-11/780 system's Synchronous Backplane Interconnect (SBI). It facilitates communication and data transfer between these two distinct bus architectures.

Key aspects covered include:

1. System Integration: The UBA acts as a bridge, translating addresses, data, and control signals between the 16-bit, 18-address-bit, asynchronous Unibus and the 32-bit, 28-address-bit, synchronous SBI. A VAX-11/780 system can support up to four UBAs.

2. Data Transfer Capabilities:

   • Address Mapping: It uses 496 map registers to translate Unibus memory page addresses to SBI page addresses, allowing Unibus devices to access discontiguous SBI memory pages.
   • Data Paths: The UBA employs a Direct Data Path (DDP) for random access transfers (translating each Unibus word/byte transfer to an SBI transfer) and fifteen Buffered Data Paths (BDPs) for high-speed block transfers (DMA), which buffer data to optimize SBI utilization (e.g., performing quadword transfers).
   • Special Modes: A "longword aligned 32-bit random access mode" is described, enabling more efficient 32-bit transfers for specific applications by eliminating traditional purge and prefetch operations.

3. Interrupt Handling: The UBA manages interrupt requests from Unibus peripheral devices, translating them into SBI interrupt requests for the VAX-11/780 CPU. It also handles interrupts generated by internal UBA events.

4. Hardware Architecture: The UBA consists of a six-slot backplane housing four main modules:

   • USI (UBA SBI Interface): Manages SBI arbitration, transceivers, parity logic, and diagnostic/configuration registers.
   • UCB (UBA Control Board): Contains the microsequencer, which controls UBA operations including initialization, attention handling, and DMA processes.
   • UMD (UBA Map and Data Path): Houses the map registers, data paths, and associated buffering and shifting logic.
   • UAI (Unibus Address and Interrupt): Interfaces directly with the Unibus, handling address and interrupt logic, and containing control/status registers.

5. Reliability and Diagnostics: The UBA incorporates extensive features for reliability (e.g., parity protection for map and data path RAMs, detection of SBI faults and Unibus timeouts) and diagnostics (e.g., data wraparound testing, read/write access to internal registers for integrity checks, a diagnostic control register to test failure modes).

6. Operational Details: The document delves into the specific command codes, timing relationships, arbitration protocols, power fail/initialization sequences, and the functions of various internal registers (e.g., Configuration, Control, Status, Failed Map Entry, Data Path Registers) that enable the UBA's sophisticated bridging capabilities.