Extended Memory Address Test

This document describes the PDP-9 Extended Memory Address Test, a diagnostic program (Product Code: MAINDEC 9A-D1FA-D) designed to rigorously verify the functionality and integrity of all core memory locations not occupied by the program itself. Created on December 29, 1967, by J. W. Richardson and maintained by the Diagnostics Group, the test ensures that each memory location is uniquely addressable.

The program performs five distinct tests: writing and checking addresses and their complements, writing a word of zeros, and detecting patterns related to shorted adjacent bit positions. The latter three tests can be selectively enabled using Address Control Switches (ACS 3, 4, 5, 6, and 7). It automatically relocates itself to test all core memory from bank to bank, requiring a PDP-9 with a minimum of 8K of core memory, utilizing locations 100 through 6007 (octal).

Loading involves punching the tape in HRI mode, setting address switches to 100, pressing I/O RESET, and then READ-IN. After loading, the program halts, indicating readiness and the amount of memory to be tested. Operational control is managed via various ACS settings: ACS 0 stops/resumes the program, ACS 1 inhibits error print-outs, ACS 2 rings the TTY BELL on error, ACS 9 inhibits program relocation, and ACS 10 allows for interactive selection of tests and suppression of specific memory addresses or blocks through keyboard input. ACS 14-17 specify the highest and lowest 8K memory banks to be tested.

Errors are reported with details including the test number, octal address, expected ("GOOD") value, actual ("BAD") value, and bank/pattern information. The document also provides guidance on handling errors and program halts, noting that using the STOP key (rather than ACS 0) during relocation can lead to unpredictable results. Each 8K memory bank takes approximately 2.5 minutes to test completely with all five tests.