DH11 Asynchronous 16-line Multiplexer Maintenance Manual

This document is the DH11 Asynchronous 16-Line Multiplexer Maintenance Manual (EK-DH11-MM-002), published by Digital Equipment Corporation in December 1973 (2nd Printing: April 1975).

The manual provides comprehensive information on the installation, operation, and maintenance of the DH11 Asynchronous 16-Line Programmable Multiplexer. The DH11 connects a PDP-11 processor to up to 16 asynchronous serial communication lines, with individually programmable parameters for each line. It supports up to 16 DH11 units per PDP-11, enabling a total capacity of 256 lines.

Key functionalities and features include:

• Programmable Line Parameters: Each line can be configured for character length (5-8 bits), number of stop bits (1, 1.5, or 2), parity generation/detection (odd, even, none), and operating mode (half or full duplex).
• Variable Baud Rates: Supports a wide range of speeds from 0 to 9600 Baud, plus external inputs.
• Double-Buffered I/O: Utilizes MOS/LSI Universal Asynchronous Receiver/Transmitters (UARTs) with double buffering for efficient character assembly (reception) and parallel-to-serial conversion (transmission).
• Silo (FIFO Buffer) for Reception: Received characters and their associated line numbers are automatically stored in a 16-bit wide, 64-word deep First-In, First-Out (FIFO) buffer. The bottom of the silo is the Next Received Character Register (NRC), which is a read-once register that extracts characters and causes others to "bubble down."
• Direct Memory Access (NPR) for Transmission: Transmitters load characters directly from PDP-11 memory using single-cycle Direct Memory Transfers (NPRs), significantly reducing Unibus overhead. Current addresses and byte counts for each line's message table are stored in the DH11's semiconductor memories.
• Auto-Echo Feature: Hardware provision to echo received characters back to the sending terminal without software intervention, provided no errors (framing, overrun) are detected, and the transmitter buffer is available.
• Interrupt System: Generates various interrupts, including Receiver Interrupts (silo fill level exceeds alarm), Storage Overflow Interrupts (silo full), Transmitter Interrupts (completion of a character string transmission), and Non-Existent Memory Interrupts (attempting to access invalid memory addresses during NPRs).

Physical Configurations: The DH11 is available in several models (-AA, -AB, -AC, -AD, -AE) to support different line interfaces, such as 20 mA current loops (Teletype), EIA/CCITT devices (with or without modem control), and telegraph lines. A caution notes that the DH11 uses hex modules and requires specific PDP-11 box types.

Programming Interface: The DH11 exposes eight program-addressable registers for control and status, allowing software to manage line parameters, initiate transmissions, handle received data, and respond to various conditions via interrupts. Key registers include the System Control Register (SCR), Line Parameter Register (LPR), Current Address Register (CAR), Byte Count Register (BC), and Silo Status Register (SSR).

Maintenance and Troubleshooting: The manual details diagnostic programs (MAINDECs: DZDHA through DZDHK) for fault isolation, covering internal logic verification (in maintenance mode) and output interface testing (on-line). It includes procedures for hardware setup, proper jumper settings, and step-by-step failure analysis for diagnostic error messages.

Appendices provide detailed supporting information on floating device/vector addresses, PDP-11 memory organization, integrated circuit descriptions, Universal Asynchronous Receiver Transmitters (UARTs), modem control interface specifics, and modem timing diagrams.