Firefox Workstation M-Bus Specification

This document, "Firefox Workstation M-Bus Specification Revision 2.1," details the design of the M-Bus, a synchronous memory interconnect specifically for Firefox workstation modules, published by Digital Equipment Corporation in December 1987.

The M-Bus's primary purpose is to enable processor snoopy caches to maintain data consistency across all caches on a cycle-by-cycle basis. Key features and specifications include:

• Module Support: Accommodates a maximum of eight modules that arbitrate for the bus using a least-recently-used priority scheme.
• Data Transfer: Transfers up to 32 bits of address or data per M-Bus cycle. Memory-space transactions involve 4 longwords (an octaword) of data, while I/O-space transactions transfer one masked longword.
• Performance: Has a target cycle time of 70 ns, with transactions typically completing within 4 to 10 cycles.
• Design Principles: Utilizes time-multiplexed and encoded control signals to minimize signal count and power consumption.
• Error Detection: Supports single-bit error detection on command and data signals via parity, but lacks hardware error correction.
• Transaction Types: Defines detailed protocols for memory-space operations (read-miss fills, write-miss fills, dirty-victim writes, shared-cache-line write-throughs, interlocked reads, unlock writes), I/O-space operations, and interrupt-acknowledge transactions.

The specification also covers detailed bus terminology, addressing schemes (2-Gbyte memory and I/O spaces), a comprehensive list and description of M-Bus signals (arbitration, data transfer, workstation control, clock distribution), interface registers, initialization procedures (power-up, power-down, reset), and electrical and mechanical characteristics for module and backplane components.