Firefox Workstation Dual-CVAX Processor Module Functional Specification

This document, the "Firefox Workstation Dual-CVAX Processor Module Functional Specification, Revision 3.0," details the KA60 module, a foundational component for the Firefox multiprocessor workstation.

The KA60 is a single, quad-height module designed to enable Symmetric Multiprocessing (SMP) by integrating two independent CVAX CPU/Floating-Point Accelerator (FPA) chipsets. Key features and functionalities provided by the module include:

• Two-Level Caching System: Each CVAX CPU utilizes an on-chip 1KB Level-1 write-through cache and an external 64KB Level-2 snoopy cache. The Level-2 cache's snoopy protocol ensures system-wide memory and I/O consistency across the M-bus, employing a write-back policy for unshared data and a write-through policy for shared data. The Level-1 cache is maintained as a consistent subset of Level-2.
• M-Bus Interface: It implements an interface to the Firefox M-bus, ensuring a consistent view of memory and I/O space for all processors and supporting VAX interlocked instructions and vectored interrupts.
• SMP Requirements Support: The KA60 provides global memory and I/O space consistency, interprocessor interrupt capability, console support for halting and controlling processors, and mechanisms for processor identification and census (determining the number and status of CPUs in the system).
• Diagnostic/Boot ROM: Each CPU is equipped with its own diagnostic/boot ROM.
• Test-Mode Features: Includes inputs for manufacturing tests and status indicators (LEDs).

The core of the module's implementation relies heavily on the Firefox Bus Interface Chip (FBIC), which acts as the M-bus interface, external cache controller, and manages various SMP-specific registers and functionalities. The document also outlines the module's physical address mapping and initial programming requirements.