Firestarter 8 Megabyte Memory Module Functional Specification

This document is the Functional Specification for the Firestarter 8 Megabyte Memory Module (Version 1.0, November 9, 1987), developed by Digital Equipment Corporation.

Core Purpose & Capacity: The module serves as a main memory for the Firefox system, providing 8 megabytes of Dynamic Random Access Memory (DRAM). It interfaces directly with the M-bus protocol.

Key Functionality & Bus Interface:

• The module operates as an M-bus slave, responding to transactions initiated by bus masters (it is never a bus master itself).
• It supports various M-bus transactions, including memory space reads (unshared, shared, interlocked), memory space writes (unshared, shared, write-through, write-unlock), and I/O reads/writes.
• Data is transferred via a 32-bit bidirectional MDAL bus, with command/status signals (MCMD, MSTATUS) and parity for error detection. Data is transferred to/from the DRAM in octawords (four 32-bit longwords).
• The Firestarter Memory Controller Module (FMCM) manages the DRAM array, including automatic refresh operations, prioritizing refresh requests over memory access.

Error Handling:

• The module detects M-bus parity errors (on MDAL, MCMD, MSTATUS) and invalid MCMD encodings. Upon detection, it asserts the MABORT signal (unless the ISOLATE bit is set in the FMDCSR register).
• It does not perform internal memory error detection; internal DRAM failures are expected to manifest as M-bus data parity errors or slave timeouts.
• It does not utilize other M-bus signals such as MSHARED, MDATINV, MDCOK, or MIRQ (interrupt).

Configuration & Control:

• Module configuration and status are managed via four FMCM registers:
  • MODTYPE: Identifies the module type.
  • BUSCSR: Stores M-bus error status and controls error logging (includes a FROZEN bit to capture the first error).
  • FMDCSR: Provides module control (e.g., disabling refresh, selecting refresh period, diagnostic refresh, and an ISOLATE bit to inhibit MABORT on error).
  • BASEADDR: Defines the module's starting memory address on 1MB boundaries and enables memory space transactions.

Limitations:

• The module lacks battery backup, meaning all data is lost upon power failure.
• It cannot initialize its DRAM array under processor command.

Power Requirements:

• The module requires a single +5V power source. Typical active power consumption is 8.6A/45W, with a maximum of 11.4A/60W during read cycles.