Firefox 16 Megabyte Memory Module Functional Specification

This document is the functional specification (Revision 3.0, dated December 31, 1987) for the Firefox 16 Megabyte Memory Module, developed by Digital Equipment Corporation.

The module serves as a primary memory within an M-bus system, designed to interface with Firefox processors and I/O subsystems. It provides 16 megabytes of ECC-protected DRAM memory (using 1M x 1 DRAMs in a 72-bit wide configuration, including 8 ECC bits). A central component is the FMDC (Firefox Memory Data path and Control) gate array, which manages the interface between the M-bus and the DRAMs, handling address decoding, data transfer, and error correction.

Key features and functionalities include:

• M-Bus Interface: The module functions strictly as a bus slave, responding to various M-bus transactions (read, write, I/O) via the 32-bit bidirectional MDAL bus. It utilizes MCMD for commands, MSTATUS for status, and MPARITY for error detection, along with control signals like MBRQ, MDATINV, and MABORT. It operates under master (MCLKA) and slave (MCLKB) clocks.
• Error Correction Code (ECC): Implements a modified Hamming code to correct all single-bit errors (SBE) and detect all multiple-bit errors (MBE) and address parity errors. MBEs are detected but not corrected, and a MDATINV signal indicates corrupted data.
• Error Strategy: Detects bus parity errors and protocol errors, asserting MABORT for 8 cycles. Internal memory errors are classified (SBE, MBE) and reported, with SBEs being corrected automatically.
• Diagnostics and Self-Test: Features a comprehensive self-test strategy for the DRAM array and internal control circuitry. This involves writing pseudorandom data, reading and checking it using the ECC, and utilizing Linear Feedback Shift Registers (LFSRs) for signature analysis to verify state machine integrity. An array of I/O registers provides detailed logging, status, and control for diagnostic purposes.
• Power and Reliability: The module requires a single +5V power source. The document includes detailed power requirements and Mean Time Between Failures (MTBF) calculations, demonstrating a significant reliability improvement due to the ECC.

The document also provides details on the module's addressing scheme, signal definitions, transaction protocols, and the design goals for its robust error handling and self-testing capabilities. A notable limitation is that the module does not have battery backup capability, meaning all data is lost upon power failure.