VAX 6000 Series Vector Programmer's Guide

This document, the "VAX 6000 Series Vector Processor Programmer’s Guide" (Order Number: EK–60VAA–PG–001, June 1990), is intended for system and application programmers developing software for the VAX 6000 system equipped with a vector processor.

The manual provides a comprehensive overview of vector processing, covering:

• Fundamental Concepts: It introduces core ideas like scalar vs. vector processing, different types of vector processors (attached vs. integrated, memory vs. register), the role and limitations of vectorizing compilers, vector registers, pipelining, stripmining, stride, and performance metrics such as MFLOPS, Amdahl's Law, and the crossover point.
• VAX 6000 Architecture: It details the specific hardware architecture of the VAX 6000 series vector processor, including its Vector Control Unit, Arithmetic Unit (with register file and FPU chips), Load/Store Unit, vector processor registers, memory management, cache memory, and vector pipelining.
• Optimization Techniques: The guide offers practical strategies for optimizing code, particularly using MACRO-32 and FORTRAN. Topics include effective vectorization, scalar/vector synchronization (SYNC, MSYNC, VSYNC), instruction flow, maximizing instruction overlap, out-of-order execution, chaining, efficient cache utilization, and register reuse.
• Algorithm Examples: It illustrates optimization methods with real-world application examples, specifically for equation solvers (e.g., Linpack, BLAS routines) and signal processing (e.g., Fast Fourier Transforms).