BLUEFISH Functional Specification

This document serves as a preliminary software reference guide for the BLUEFISH (PDP 11/68) processor, outlining its functional specifications. BLUEFISH represents a new high-end PDP-11 architecture, aiming for 1.5 times the performance of the 11/74 at a reduced cost, with integrated multiprocessor capabilities. It offers full 11/74 functionality with a few specified exceptions.

Key architectural features include communication via a high-bandwidth synchronous backplane interconnect (PPBI), mass bus peripherals handled by RH68 controllers, and Unibus mapping by a Unibus Controller (UBC). The system supports both the Commercial Instruction set (DEC STD 168) and integral/accelerated floating-point operations with the full FP11 instruction set, and includes a cache buffer.

The document details the PDP 11/68 processor's base instructions, addressing modes, control registers, and mechanisms for handling aborts, traps, and interrupts (including a priority list). A significant portion is dedicated to the Memory Management Unit (MMU), explaining its role in memory protection and relocation through virtual addressing, physical address construction, and a set of management registers (PARs, PDRs, MMRs). Cache/Memory operations are also described, covering CPU references, DMA, and cache memory format.

The Floating Point Processor (FPP) is an integral component, designed for parallel operation with the main CPU, offering high-speed single and double precision calculations with six 64-bit accumulators. Its data formats, status register (FPS), exception handling, and instruction addressing are explained. The "Software Issues" section highlights programming differences and specific hardware implementations compared to other PDP-11 family members, such as write buffering on CPU writes and changes in trap-related functions. Appendix A provides a detailed functional specification for the Midrange Systems Console, defining its command syntax, interaction, and communication protocols.