PDP-11 UNIBUS Processor Handbook

This document, the "PDP-11 UNIBUS Processor Handbook," serves as a comprehensive reference guide for Digital's PDP-11 UNIBUS processor family, specifically detailing the PDP-11/84, PDP-11/44, and PDP-11/24 models. It provides an in-depth look at the UNIBUS, a high-speed, bidirectional, asynchronous communication bus that forms the backbone of these systems, ensuring extensive hardware and software compatibility across the family.

The handbook offers a functional overview of each processor: - PDP-11/84: Positioned as the most powerful and cost-effective, featuring the J-11 chipset, private memory interconnect (PMI) for accelerated CPU-memory-UNIBUS adapter communication, 8Kbyte CPU cache, DMA cache, memory management unit (MMU) with 22-bit addressing, an integral floating-point processor, and support for up to 4 Mbytes of ECC MOS memory. - PDP-11/44: A medium-scale general-purpose computer characterized by its high-performance central processor, 8Kbyte parity cache memory, and standard memory management and UNIBUS map. - PDP-11/24: A compact, low-cost processor offering 22-bit memory addressing up to 4 Mbytes, with optional floating-point and commercial instruction sets.

For each processor, the document covers its system architecture, central processor details (including registers, status words, traps, pipeline processing, and error handling), memory systems (management, Error Correcting Code, and battery backup), UNIBUS adapter, boot ROM facilities, console functions, and technical specifications.

Chapter 5 is dedicated to a detailed technical description of the UNIBUS, outlining its characteristics (e.g., nonmultiplexed, master/slave relationship, partially distributed arbitration, asynchronous operation, 18-bit addressing), its structure as cooperating buses (initialization, arbitration, data transfer), various data transfer types, signal descriptions, and electrical characteristics. Appendices further enhance the guide with tables comparing PDP-11 family differences in instructions, memory management, and error handling, alongside console ODT commands and detailed instruction execution timings for the various processors. This handbook is intended for both evaluators and users to aid in selecting and effectively utilizing PDP-11 systems.