11/60 MICROPROGRAMMING SPECIFICATION

This document details the microprogramming specification for the Digital Equipment Corporation (DEC) PDP-11/60 processor, aimed at experienced assembly language programmers and hardware engineers. Its primary goal is to describe the hardware environment accessible to the microprogrammer, enabling customization of the CPU via the Writable Control Store (WCS) option.

The manual introduces microprogramming as a method to control computer functions through elemental "micro-operations," highlighting its evolution into a user-accessible tool. It differentiates between architecture (programmer-visible features) and organization (implementation details), presenting the 11/60 as a microprogrammed PDP-11, complete with floating-point unit, cache, stack limit, and memory management.

The 11/60 processor is segmented into five logical sections: Datapath, Bus Control, KT/Cache, Processor Control, and WCS. The Datapath, the core operational unit, comprises an Arithmetic/Logic Unit (ALU), A and B scratchpads (ASP/BSP) for registers, a C scratchpad (CSP) for constants and memory data, a D register for ALU output, a Shift Register (SR), and a Shift Tree for data manipulation. Control is orchestrated via a 48-bit "horizontal" microword, which often allows parallel control of multiple signals and employs bit steering. Microinstructions execute in 170-nanosecond microcycles, further timed by clock pulses.

Microinstruction sequencing on the 11/60 follows a chained approach, where each microinstruction explicitly specifies its successor's address, facilitating conditional branches (BUTs) and subroutine calls. Careful attention to timing is crucial, particularly with overlapped instruction fetches and multi-cycle memory operations.

The Processor Control section manages inter-processor communication through BUS DIN and DOUT, governed by the User Control (UCON) register. Memory operations involve the Bus Address (BA) register, KT unit, and cache. The WCS, a 1K-by-48 bit RAM, can function as both control store and local store, with auxiliary routines from the Transfer Micro Store (TMS) ROM supporting block data transfers.

The document further outlines the base machine's code flow, including overlapped instruction fetches and micro-level interrupt handling (Service and JAMUPP routines). It concludes with WCS usage guidelines, detailing Unibus registers for WCS loading, various entry points into WCS microcode, available TMS ROM routines for managing processor state, and critical cautions concerning interrupt latency, Unibus usage, scratchpad integrity, PDP-11 state requirements, and complete opcode decoding to prevent errors. Practical examples, such as microcode for a block move, are provided to illustrate these concepts.