FP11-B floating-point processor maintenance manual

This manual provides comprehensive maintenance information for the FP11-B floating-point processor, an optional arithmetic unit designed for the PDP-11/45 Central Processor to enhance arithmetic and logic operation speed. It covers the processor's system architecture, including its single and double-precision floating-point capabilities, and its direct interface with the PDP-11/45 CPU. The document details data and instruction formats, the microprogrammed control ROM, and the arithmetic algorithms for addition, subtraction, multiplication (using "shifting over 1s and 0s"), and division (using non-restoring normalizing division). A significant portion is dedicated to the detailed logic diagrams of the FP11-B's four multilayer hex modules and their internal components, such as accumulators, ALUs, registers, and control logic. Furthermore, it provides extensive maintenance information, including descriptions of the Maintenance Module, console display features, special maintenance instructions (e.g., LDUB, LDSC, STAO, STQO, MRS), and diagnostic programming examples to assist personnel in troubleshooting and verifying proper operation. The manual also includes appendices for integrated circuit descriptions and a signal glossary.