A Comparison of Two Microprogrammable Processors

This document compares the capabilities and performance of two microprogrammable processors: the vertically-encoded 36-bit MLP-900 and the horizontally-encoded 16-bit PDP-11/40E. The study aimed to evaluate their suitability for a multi-level simulator project.

The MLP-900, a synchronous machine with a 250 nsec clock cycle, features a split architecture with an "Operating Engine" (OE) for arithmetic and a "Control Engine" (CE) for control flow, allowing for parallel microinstruction execution. It boasts a 36-bit data path, 4K of 32-bit microstore, and various registers. Memory references take approximately 1300 nsec. Programming is superficially straightforward but complex for maximum performance due to OE/CE pairing and data distribution.

The PDP-11/40E is a modified PDP-11/40 with cycle times between 140-300 nsec and a 16-bit data path. It uses an 80-bit microword, 1K of 80-bit read/write microstore, and a hardware stack. Memory references require two microinstructions and average 780-1180 nsec due to asynchronous Unibus operations. Programming for optimal performance is considered difficult due to the need for parallel thinking and specific hardware quirks.

Four benchmark programs were used for comparison:

1. MMPY (64-bit integer multiply): The MLP-900 was over four times faster, leveraging its 36-bit data path against the PDP-11/40E's 16-bit path, which required quadruple-word operations.
2. TRANS (character translation): The PDP-11/40E was about 25% faster, benefiting from its byte-handling features, which the MLP-900 lacked.
3. ALLOC (memory allocation): The PDP-11/40E was slightly faster for full-word 16-bit operations. The MLP-900's wider data path was less effective when data had to be packed into fewer words, increasing execution costs.
4. NOVA (minicomputer emulator): The PDP-11/40E performed about 30% faster, attributed to its 16-bit architecture being well-suited for emulating a 16-bit machine, and the MLP-900's higher overhead for field extraction and longer memory reference times.

A "neutral" benchmark comparison, focusing on 16-bit full-word operations, showed the PDP-11/40E to be 10-15% faster for tasks like memory allocation and list reversal, although requiring slightly more instructions. Branch costs were found to be approximately equal on both machines (around 70-75 nsec expected wasted time per branch).

In conclusion, the PDP-11/40E is preferred for emulating 16-bit or smaller machines and byte-handling tasks, while the MLP-900 is superior for applications requiring wide data paths or emulating larger, wide-word length machines. The PDP-11/40E might be easier for automatic microcode compilation due to more regular data handling, while the MLP-900 is a usable prototype system available via the ARPA Network.