FP11-A floating-point processor technical manual

This technical manual details the FP11-A Floating-Point Processor, a hardware option designed to enhance the PDP-11/34A central processor with floating-point arithmetic capabilities. The FP11-A supports both single- (32-bit) and double-precision (64-bit) data modes, performing arithmetic operations and data conversions between integer and floating-point formats. It features multiple accumulators, PDP-11 compatible addressing modes, and error recovery mechanisms.

The document provides a foundational review of floating-point numbers and their normalization, followed by a detailed description of the FP11-A's data formats for integers and floating-point values, including its Program Status Register and exception handling. A significant portion covers the comprehensive floating-point instruction set, encompassing arithmetic, load, store, and conversion instructions, illustrated with examples.

Subsequent chapters explain the processor's organization, focusing on the AM2901 microprocessor, its internal RAM, ALU, Q-register, and various control components like shift control, branch logic, and tri-state transceivers. The control store and signal interface are also described in detail. The manual meticulously outlines the arithmetic algorithms for floating-point addition, subtraction, multiplication, and non-restoring division, highlighting their hardware implementations. The document concludes with essential information on maintenance, diagnostics, programmer's console features, installation procedures, and power specifications for the FP11-A and associated PDP-11 components.