Tru64 UNIX

This document, "Tru64 UNIX Asynchronous Transfer Mode," dated September 2002 (Part Number: AA-RH9KC-TE), is a manual for experienced UNIX kernel programmers and system administrators working with Tru64 UNIX Version 5.1B or higher.

The manual describes the architecture and kernel interfaces of the Tru64 UNIX Asynchronous Transfer Mode (ATM) subsystem. It is intended for those responsible for writing ATM device drivers and kernel modules, detailing how to configure the subsystem and utilize its kernel interfaces. It is not an ATM networking tutorial or a guide to user-level application programming interfaces (APIs).

Key components and features of the ATM subsystem covered include:

• Connection Management Module (CMM): The central module that manages all ATM subsystem activities, virtual circuits (VCs), and communication among modules.
• Interfaces: The CMM provides well-defined interfaces for ATM device drivers, signaling modules, and convergence modules (which connect kernel networking protocol stacks to ATM).
• Data Handling: Supports raw ATM cells and cooked packet Protocol Data Units (PDUs), with mechanisms for time-stamping and handling cell loss.
• Physical Point of Attachment (PPA): Represents network service endpoints, categorized as Permanent Virtual Circuit (PVC) PPAs and Switched Virtual Circuit (SVC) PPAs.
• Memory Management: Provides specific macros for allocating and freeing memory within the ATM subsystem.
• Locking Mechanisms: Details ATM locking macros to ensure SMP (Symmetric Multiprocessing) and RT (Real-Time) safety for kernel modules.
• Circuit Types: Supports Unspecified Bit Rate (UBR), Constant Bit Rate (CBR), and Pacing circuits.
• Global Data Structures: Describes various structures used for managing VCs, addresses, services, and error information.
• Module Management Interface (MMI): Allows applications to exchange configuration and management information with specific ATM modules through the CMM.
• Queuing and Flow Control: Offers guidelines for implementing queuing policies in device drivers and convergence modules, and explains hardware and software flow control mechanisms within the ATM subsystem.