M7218 PDP11 15 Bus Requests

This two-page document details the "Bus Requests" logic for a Digital Equipment Corporation (DEC) M7218 module, specifically identified as KBR-1 (on the general information page) and KBR-2 (on the schematic page).

Page 1: Reference Information and Notes (KBR-1)

• Parts Reference: Lists the capacitors and integrated circuits (ICs) used, including specific DEC part numbers and quantities.
• Component Placement: Provides a visual layout of the major components (capacitors C1-C13 and ICs E1-E12) on the module.
• Pin Nomenclature: Defines the mapping between module pins (e.g., C, D, A, B) and processor pin functions.
• Notes (Critical for Interpretation):
  • Explains pin notation, module references, and how they relate to the processor.
  • Details how signals are noted, including input/output conventions.
  • Defines the "Processor Signal Source Notation" (e.g., KBR-X) for identifying signal origin (print set, sheet, on/off module) and the "BUS" prefix for wired-OR signals.
  • Provides standard pin assignments for GND and +5V for various IC types, along with default resistance and capacitance values.

Page 2: Bus Request Schematic (KBR-2)

• This page presents the detailed logic diagram for handling bus requests.
• Inputs: The circuit receives multiple active-low "Bus Request" lines (BUS BR7 L, BUS BR6 L, BUS BR5 L, BUS BR4 L), various control/status signals (K9-4-ST05, ST06, ST07), a clock signal (K15-2 CLK BR H), a clear signal (K15-2 CLR BR L), a "disallow" signal (K15-2 DISALLOW BR H), and a "grant" signal (K2-3 GRANT BR H).
• Outputs: It generates processor-specific "Bus Grant" signals (KBR-2 PROC BG7 H, BG6 H, BG5 H, BG4 H), enable signals (KBR-2 BG6 ENABLE H, KBR-2 BG4 ENABLE H), a general "Bus Request Output" (KBR-2 BRQ L), and several "Test Point" signals (KBR-2 TP1, TP2, TP3, TP4).
• Logic: The design utilizes various standard TTL logic gates (NAND, NOR, Inverters, D-type flip-flops like 74H74) to implement the control logic, suggesting a sequential and potentially prioritized mechanism for processing and granting bus requests within the M7218 system.