M7217 PDP11 15 PWRFAIL RESTART

This document details the "PWR FAIL & RESTART" module, designated "KP-2", which is designed to manage power failure and restart sequences within a processor system.

It comprises three main sections:

1. Parts Reference: A comprehensive list of components, including various capacitors, diodes, resistors, and numerous integrated circuits (primarily 74xx series TTL logic and 8881 ICs), along with their part numbers and quantities.
2. Component Placement: A diagram illustrating the physical layout of all listed components on the module.
3. Schematic Diagram: A circuit diagram detailing the logic for power failure detection and restart. Key functions include:
   • Detection of AC and DC power loss (AC LO, DC LO).
   • Generation of PWR DOWN and POWER UP signals.
   • Incorporation of multiple delay circuits to ensure proper sequencing during power transitions.
   • Integration of various input signals such as GATED PRESTART, HALT, R/WI (Read/Write Inhibit), ISR (Interrupt Service Request), and SVC CLR OVFLF (Service Clear Overflow).

General Notes: The document also specifies conventions for pin notation, processor signal source identification (e.g., KP-X prefixes), and component value defaults (resistance in ohms, capacitance in picofarads, un-noted capacitors as 0.01 MFD). An important revision note indicates a specific ECO affecting the KY-3 HALT L signal name (BØ4S2). Pin 7 and Pin 14 are generally used for GND and +5V, respectively, with exceptions for certain IC types.