KT11-B EngrDrws Feb7

This document is a comprehensive technical manual for the Digital Equipment Corporation (DEC) KT11-B Paging Option, designed for use with the PDP-11 processor. Dating from February/March 1972, it provides detailed engineering and maintenance information for this specific computer hardware component.

Key sections include:

• Master Drawing List: An index of all included drawings.
• Parts Lists: Detailed breakdowns of components, covering both mechanical assemblies (e.g., wired assemblies, panels, rivets, wires, power harnesses) and electronic modules (e.g., inverters, gates, NAND gates, memory, shift registers, associative memory, pulse generators, power inverters, bus interfaces, Unibus drivers/receivers, bus terminators).
• Wiring Diagrams: Specifically, a wire table showing power connections for the Paging Option.
• Module Utilization Charts: Indicating the usage of various electronic modules within the system.

• Extensive Circuit Schematics: Covering the major functional blocks and logical operations of the paging option. These include:

  • Address Bus & Control Logic
  • State Control Logic
  • SP Input Multiplexer (MX)
  • AM Control & Random Signals
  • Scratch Pad & State Control Logic
  • Data Bus & Control Logic
  • Keys & Associative Memory (AM)
  • XP Option for KT11 AM Control
  • PGM Register (Program Register)
  • FCC Register (Field Control Register)
  • Timing Logic
  • Buffered Signals & Main Logic
  • Extended Associative Memory
  • KA-11/KT-11 Interface

• System Configuration Diagram: Illustrating how the KT11-B Paging Box integrates with the PDP-11 processor, various power control units (H720 H, 83A, 841B), and different bus interfaces (CPU Bus, CP Interface Bus, DV Bus).

• Bus Connectors: Showing pinouts for inter-component connections.

The document serves as a detailed technical reference for the design, assembly, and logical operation of the KT11-B Paging Option within a DEC PDP-11 system.