M8018 LSI-11 WCS Schematic

This document consists of six sheets of engineering schematics (pages 2-6 provided) detailing the design of a "WRITEABLE CONTROL STORE (WCS-LSI-11)" module for a Digital Equipment Corporation (DEC) LSI-11 system, copyrighted 1976.

The schematics outline the various functional blocks of this memory module, primarily using 74LS series integrated circuits and SRAM (e.g., 2115-type) chips:

• DAL Bus Timing and Selection (Sheet 2): This section defines the interface with the main "DAL Bus," handling signal timing, data selection, and the generation of internal control and data signals for the WCS.
• RAM Address MUX and Latch (Sheet 3 & 4): These sheets illustrate how memory addresses are generated, multiplexed, and latched from various internal "TSB" signals to access the data RAMs that store the writable control store's contents.
• DAL Output Muxes and Trace Mode Logic (Sheet 5): This part describes the logic responsible for outputting data from the WCS, potentially back onto the DAL bus. It notably includes a "Trace Mode Logic" section, suggesting built-in capabilities for debugging or monitoring the control store's operation.
• Control/Status Register (Sheet 6): This section details the primary control and status interface for the WCS, encompassing logic for write enable, clock generation (for counting up/down), data bus arbitration, a "stop" function, and the management of various internal status signals.

The recurring "CAUTION CHANGE IN-PROCESS" stamp on the sheets indicates that the design was actively undergoing revisions at the time these drawings were produced.