PHYKLP Memo

This document describes the KLIPA driver (PHYKLP), a low-level TOPS-20 device driver specifically for the CI-20. It is integrated into the PHYSIO system as the first non-RH20 device.

The KLIPA driver's core responsibilities include:

• Hardware Control: Coordinating all access to the CI-20 device, implementing a queued interface with the operating system, and providing services for diagnostics and "DMA" (Direct Memory Access) functions.
• Virtual Circuit Management: Maintaining reliable port-to-port virtual circuits (VCs) with other CI nodes. This involves continuous polling to discover new nodes or detect configuration changes, and establishing VCs through a "three-way handshake" initialization protocol.
• System Integration: It interfaces with PHYSIO for interrupt handling and polling, despite the KLIPA not supporting vectored interrupts directly. It also interacts extensively with the System Communication Architecture (SCA) for higher-level data transfers.

Key aspects of its operation and structure include:

• Data Structures: It manages a Port Control Block (PCB) for communication with the KLIPA hardware (using physical memory addresses and "spin locks"), and System Blocks which describe each node on the CI, including its virtual circuit state and associated PCB information.
• Active vs. Passive Roles: While generally a passive service responding to requests, its active components are the polling operation and virtual circuit initialization. Other data transfers (messages, datagrams, DMA) are explicitly requested by SCA.
• Message Handling: It supports various packet types, including SCA messages and datagrams, and CI housekeeping/maintenance datagrams. SCA message delivery is guaranteed, while datagram delivery is not. SCA is responsible for providing most message and datagram buffers; PHYKLP merely enqueues and dequeues them.
• Error Handling: Errors are detected at the interrupt level and categorized into transmission errors (affecting VCs, CI defects, no ACK), device errors (e.g., free queue errors due to insufficient SCA buffers, CRAM parity errors indicating a KLIPA halt), and bus errors. Severity varies, from logging events to shutting down VCs or requiring microcode reloads.

In essence, PHYKLP acts as a state machine, managing the complex interactions and states required to maintain robust communication over the CI, providing fundamental services for higher-level system components like SCA. This document serves as a "road map" for its implementation and maintenance.