LCG CI Port ArchSpec Jan85

This document, the "LCG CI Port Architecture Specification" from January 1985, details the architecture and operating system interface for the LCG Computer Interconnect (CI) port.

The CI is a 70 Megabits/second, packet-oriented, multi-drop bus designed to link computer systems and intelligent mass storage controllers, featuring low error rates and immediate acknowledgements. The LCG CI port enables LCG computers to interface with this bus, complying with the CI wire architecture.

Key aspects of the architecture include:

• Queued Protocol: Host-port communication is managed through a queued protocol utilizing a Port Control Block (PCB) in host memory. This PCB contains link words for seven doubly-linked queues: four priority-ordered Command Queues, a Response Queue, and two Free Queues (Datagram and Message) for managing queue entries.
• Port States: The port operates in three defined states: Uninitialized, Disabled, and Enabled, controlling its functionality and packet acceptance.

• Packet Transmission Characteristics: The document specifies formats for various packet types and services, including:

  • Datagram Service: Provides best-effort delivery for messages.
  • Virtual Circuit Service: Offers higher-quality, reliable, sequential, and non-duplicated delivery for messages and large data transfers, managed by circuit state variables (CST, NS, NR) and path selection.

• Data Transmission: Data transfers leverage "named buffers" in host memory, described by a Buffer Descriptor Table (BDT) composed of Buffer Header Descriptors (BHDs) and Buffer Segment Descriptors (BSDs). It supports three data formatting modes: Industry Compatible, Core Dump, and High Density.

• Port Management: Includes functionality for port performance monitoring (via counters), configuration information (ID commands), and maintenance commands (e.g., Reset, Start, Read/Write Remote Memory).
• Diagnostic Operations: Supports commands for diagnostic purposes like Loopback and reading/writing port registers.
• Port Registers: Communication between the host and port is primarily through the Control and Status Register (CSR), which indicates port status and allows command invocation.
• Error Conditions: The port microcode handles error retries, and non-recoverable errors (e.g., queue interlock failure, internal port errors, EBUS/CBUS errors) lead to the port entering a Disabled state, with error details logged in the PCB.

The specification provides detailed formats for commands, responses, and data structures, serving as a comprehensive guide for software interaction with the LCG CI Port hardware.