ICCSPORT Memo Jul9

This document describes the design of the KL10 ICCS port, intended to provide a VAX-compatible interface to the ICCS bus and facilitate migration to the 2080 interface.

The port's architecture revolves around three key interfaces:

1. Software to Port: Managed via standard PDP-10 I/O instructions for data transmission requests, completion, and status.
2. Port to Link: Defined by the corporate interconnect specification.
3. Port to Memory: Utilizes the C-BUS for DMA data transfers and the E-BUS for queue manipulations and packet handling.

Key components and functions include:

• Port Control Block (PCB): A central structure identified by its physical address, containing pointers for free queues, four prioritized command queues (0-3), and response queues.
• Buffer Descriptors (BDs): Linked lists defining physical memory regions for data, used in conjunction with a Buffer Descriptor Table (BDT).
• Interlock Function: Requires atomic read-modify-write capabilities for memory locations and the ability to detect interlock unavailability.
• Command Queues: Four distinct queues with implicit priority (0 highest, 3 lowest) for local host requests, and local/remote host initiated data transfers.
• Messages: Fixed-sized packets transmitted atomically, with control information using 36-bit words and the message body using the left-most 32 bits of each word for byte data.
• I/O Instructions (CONO PRT): Bits for controlling PSI level, GO, Stall, error flags, queue status, and cache clearing.
• Control/Status Registers (CSRs): Used for port configuration (e.g., base address, bus selection mode, error reporting).
• Data Modes: Supports byte, word, and tape modes, with specific packing and zero-filling rules. BDs also include modifiers for read/write directions (e.g., read-only, write-backwards).
• Caching: BD and BDT data caching is considered beneficial, while caching queue entries is noted as risky.

Programming considerations emphasize the port's reliance on physical memory addresses for critical data structures, the complexity of managing BDs, and the need for efficient command/response queue processing, proposing solutions like memory-mapped PCBs and virtual address mapping for packets.