CI20 HwPortSpec May83

This document is a hardware port specification for the CI20 (KL10 CI Port Adapter), dated May 19, 1983.

Purpose and Function: The CI20 is a unique hardware/firmware option designed to enable KL10-based operating systems to interface with the Corporate high-speed serial line CI Bus. Its primary functions are to facilitate:

1. Loosely coupled communication between multiple KL10 systems via the CI Bus.
2. Connections between KL10s and HSC50s via the CI Bus.

Key Components and Architecture (focusing on the "PORT" as per the document): The CI20 system consists of three main logical sub-groups: the LINK/FRONT END INTERFACE (L0100), PACKET BUFFER (L0109), and the PORT. This document primarily describes the PORT hardware.

The PORT itself is composed of three standard hex modules:

• EBUS INTERFACE/PORT ALU MODULE (M3001): Acts as a low-speed asynchronous control interface between the KL10 EBOX and the PORT Microprocessor. It contains a 36-bit Control and Status Register (CSR) for EBUS operations and houses the PORT Microprocessor's Arithmetic Logic Unit (ALU).
• PORT MICROPROCESSOR CONTROL MODULE (M3002): A horizontally programmed bit-slice microprocessor controller. It's responsible for managing the CBUS/Mover and EBUS/PORT ALU interfaces, including data mapping, CI packet interpretation, and packet buffer manipulations. It contains an AM2910 microsequencer, a 4Kx60-bit Control RAM (CRAM) for microcode, and a 1Kx36-bit Scratch Pad RAM.
• CBUS-PLI INTERFACE MODULE (M3003 - CMVR): Serves as a high-speed synchronous DMA data transfer path and data formatter between the PACKET BUFFER and the KL10 CBUS CHANNEL. It handles 8-bit PLI bytes to 36-bit KL10 words conversion and vice versa, and supports data transfers between the PORT microprocessor and the formatter/PLI.

These PORT modules are interconnected by a 36-bit tri-state data path called the MBUS.

Firmware (Microcode): The PORT hardware is inseparable from its PORT MICROCODE. The KL10 loads this microcode into the CRAM before the PORT starts. The microcode controls all data transfers, processes CI PROTOCOL PACKETS according to the CI Architecture Specification, and provides error monitoring/reporting.

Functionality and Features:

• Data Formats: Supports High Density, Core Dump, and Industry Compatible data format modes.
• Reliability & Diagnostics (RAMP Features): Includes parity generation/checking on all external busses (not internal data paths), CRAM parity checking with recovery, microcode self-test routines, diagnostic loop-back capabilities, single-cycle mode for debug, and DMA parity prediction.
• Performance: Offers a realizable data transfer bandwidth of approximately 300 pages/sec (0.7 megabytes/sec), accounting for both hardware DMA and microcode processing overhead.
• Interfacing: Uses the EBUS for control and status with the KL10, and the CBUS for high-speed DMA data transfers.

Installation and Compatibility:

• Designed as a field-installable upgrade kit for KL10 model B systems (not supported on model A).
• Installed in a dedicated slot (RH20 position #7) in the KL10's RH20-DTE20 backplane, which restricts the number of other RH20s.
• Can be installed on SMP systems, but requires external memory in "FOUR BUS MODE."
• Does not support multiple CI20s on a single KL10 or 7-bit ASCII data.
• Powering is integrated with the KL10 system.

The CI20 adheres to DEC-102 temperature/humidity standards and has a minimal impact on the KL10's EMI-RFI profile.