TX01 STC Tape Controller Handout Aug73

This document, titled "TX01 TAPE CONTROLLER HANDOUT," is a comprehensive technical manual detailing the hardware and micro-programming aspects of the TX01 Tape Control Unit.

It is structured into several key sections:

1. Basic Logic Components (Pages 2-9): Provides a reference guide for various SN74xx series integrated circuits (ICs), including logic gates (NAND, NOR, AND, XOR), inverters, buffers, flip-flops (JK, D-type), expanders, comparators, decoders, data selectors, shift registers, memory components, line drivers, and receivers. Each entry includes pin configurations, functional descriptions, and power requirements.

2. Control Unit Architecture and Micro-programming (Pages 10-20): This section outlines the structural and operational logic of the control unit. It includes:

   • High-level logic diagrams showing interconnections of ICs and system components (e.g., Control Memory, Mother Board Pins).
   • A block diagram of the control memory architecture, detailing components like ROMAR (ROM Address Register), ROM, SPAR RAM, ROMSL (ROM Sense Latches), and ROM DR (ROM Data Register).
   • Detailed explanations of machine cycle timing (e.g., 390ns cycle, R1/R2 cycles) and control unit clock generation.
   • The structure of ROM words, detailing micro-order encoding, and the logic for both unconditional and conditional branching to determine the next ROM address.

3. Operational Microcode/Logic Flow (Pages 21-87): This extensive part presents flowcharts and logic diagrams illustrating the precise sequence of steps and conditional logic for various tape controller commands and routines. This covers:

   • Write Operations: Sequences for initial selection, bus parity checks, command decode, write prefetch, motion control, turnaround delays, BCR value setting, data loop processing, read back checks, and reset sequences.
   • Read Operations: Sequences for initial selection, command decode, motion control, read data control, and generating resets.
   • Specific routines for functions such as "MAINT TO IDLE LOOP," "SPAR TO COMMAND," "BUFFER COMMAND ACCESS," "SENSE DECODING," "TURNAROUND," "ID BURST DETECTION," "NRZI READ," and "NRZI WRITE," often including notes on logic conditions and timing.

4. Tape Data Handling and Timing (Pages 88-101): This section delves into the specifics of data storage and retrieval:

   • Details on Phase Encoded (PE) write timing, data rates (e.g., 1600 bpi for a 3470 tape unit), and bit cell timing.
   • Explanation of data encoding and error checking mechanisms like Cyclic Redundancy Check (CRC) and Longitudinal Redundancy Check (LRC), including how these are written to and read from tape, and the logic for error pattern detection and comparison (e.g., CRC=DTR for Tie Found).
   • High-level and detailed block diagrams illustrating the data path through various registers, detection units, and control points (e.g., I/O Reg, R/W Regs, ECC Bus, CRC Reg, DTR, LSSB, PE Detection, NRZI/Lo/Hi Clip Detection).
   • Comprehensive timing diagrams for read detection (including specific patterns like 40 zeroes), normal data transfer, read overrun conditions, and phase error.

The document is highly technical and appears intended for engineers or technicians involved in the design, maintenance, or in-depth study of the TX01 Tape Controller.