MH10

This manual provides a comprehensive description, installation, operation, and maintenance guide for the MH10 Core Memory. The MH10 is a coincident-current, ferrite-core, 3-D, 3-wire memory system, capable of storing up to 262,144 37-bit words (36 data bits plus 1 parity bit) with a cycle time of 1.2 µs. It is offered in basic (MH10-G, 64K words) and expandable configurations (MH10-H at 128K, MH10-L at 256K) and can be connected to up to 16 memory units on a memory bus.

The MH10 operates asynchronously within the DECsystem-10 via a "request/response" system, supporting up to eight access ports with priority logic for simultaneous requests. It features 2-way interleaving within a single cabinet and 4-way interleaving between two cabinets, effectively reducing cycle time for sequential addressing. Key features include bank selection switches for graceful degradation in case of stack malfunction and data parity checking.

Physically, the MH10 is housed in a standard PDP-10 cabinet, divided into two major logic sections: the Core Memory and Control (CMC) and the Port Control and Core Interface (PCCI). The PCCI handles request-acknowledge and priority control, while the CMC manages the core memory stacks and data handling.

Installation procedures cover site preparation, cabling (memory bus, AC power, remote power control, ground mesh), and setting various switches for memory address (lower boundary), interleaving modes (normal, 2-way, 4-way), port selection (with a defined priority scheme), and memory bank sizing.

For operation, controls and indicators are grouped on Maintenance, Indicator, and 857 Power Control panels. The 857 Power Control panel manages main power, implements safety shutdowns, and allows maintenance overrides. The Maintenance panel configures port addressing, interleaving, memory banks, and provides troubleshooting switches like MARGIN, DISPLAY, ERROR STOP, and SINGLE STEP. The Indicator panel displays memory operation status and register contents for diagnostics.

The principles of operation detail the MH10's logical functions, including three primary memory cycles: Read/Restore, Clear/Write, and Read/Modify/Write. It explains how data is stored in ferrite cores by magnetization, selected via X-Y-Z windings, and how currents are generated and sensed. The power system, comprising an 857 power control and H7420 power supplies, is also described, including power-up sequences, protection circuits (airflow, interlocks, overcurrent, overvoltage), and voltage regulation.

Maintenance procedures include preventive tasks like visual inspections, running diagnostic programs (MAINDEC testing), and checking margins, voltages, and timing delays. Corrective maintenance involves voltage adjustments, troubleshooting parity errors (potentially linked to CPU, memory bus, PCCI, or CMC logic), and module replacement for factory-adjusted components. Troubleshooting aids, such as charts and waveforms, are provided to assist in isolating malfunctions.