alpha assembly lang

This document, "Alpha Assembly Language Guide" by Randal E. Bryant (September 22, 1998), provides an overview of the Alpha instruction set and its assembly language programming conventions.

1. Overview of Alpha Architecture:

• The Alpha is a second-generation Reduced Instruction Set Computer (RISC) architecture, originally by Digital Equipment Corporation (later Compaq).
• It is a true 64-bit machine with all integer registers 64 bits wide, fully supporting 64-bit addresses and integers, while also providing support for 32-bit integers (termed "long words" compared to 64-bit "quad words").
• Porting C Code: A significant section addresses challenges when porting C code from 32-bit systems to Alpha, particularly concerning the differing sizes of pointers and ints, the need for an 'L' suffix for 64-bit integer constants, and appropriate printf format specifiers.

2. Instruction Set: The Alpha instruction set is characterized by its simplicity:

• Arithmetic operations are strictly register-to-register, requiring explicit load/store instructions for memory access.
• Conditional branches can only test the relation between a register and zero.

Key instruction categories include:

• Arithmetic Operations: Available in both 4-byte (long word, suffix 'l') and 8-byte (quad word, suffix 'q') versions, often with three operands (two sources, one destination) and support for small literal constants. Scaled operations (e.g., s4addq) are useful for array indexing.
• Comparison Operations: Work on 8-byte quad words, setting a destination register to 1 (true) or 0 (false), with both signed and unsigned variants.
• Bit-Level and Logical Operations: Operate on quad words.
• Loads and Stores: Transfer data between registers and memory for 4-byte (ldl, stl) and 8-byte (ldq, stq) quantities. Special instructions like lda and ldah manipulate addresses without memory access. Alpha imposes strict alignment requirements (4-byte for long words, 8-byte for quad words), but provides unaligned load/store (ldq_u, stq_u) and dedicated Byte Manipulation Operations (extbl, mskbl, insbl, extqh, zap, zapnot) to handle byte-level data efficiently, which is critical given the hardware's non-direct support for single-byte operations.
• Conditional Moves: Allow registers to be updated conditionally without branching, improving performance.
• Special Case Operations: Common instruction patterns are given readable "special names" (e.g., nop, mov, sextl) which are translated into fundamental Alpha instructions.
• Transfers of Control: Includes conditional branches (e.g., beq, blt) and unconditional jumps (br, bsr for subroutines, jmp, jsr, ret).
• Floating Point: Utilizes a separate set of 32 floating-point registers (e.g., $f0-$f31) supporting single (S_floating) and double (T_floating) precision. These operations largely mirror their integer counterparts, covering arithmetic, comparisons, loads/stores, conditional moves, branches, and type conversions.

3. Programming Conventions:

• A set of standardized conventions is vital for compiler writers and assembly programmers to ensure interoperability between different code sources and to support debugging and performance tools.
• Register Usage: Both integer and floating-point registers are assigned specific roles by convention (e.g., return values, temporaries, callee-saved registers, arguments, stack pointer $sp, global pointer $gp). Register $31 (integer) and $f31 (floating-point) are hardwired to zero.
• Stack Frames: Procedures allocate stack frames for local data, linkage information, and arguments. The stack grows towards lower addresses, and frame sizes must be a multiple of 16 bytes.