Dolphin Shared Pages Data Integrity Box Aug78

This document comprises several interoffice memoranda from Digital Equipment Corporation concerning data integrity in multiprocessor Dolphin systems, specifically focusing on "Shared Pages" and the "Shared Pages Data Integrity (SPDI) Box."

The primary document is the "Dolphin SPDI Box Functional Specification Revision 1" (dated August 16, 1978). It describes the SPDI Box as an optional hardware unit that plugs into the Dolphin Bus. Its main function is to ensure data integrity between processor caches in a multi-processor system, preventing stale data.

Key functions of the SPDI Box:

• Intercepts writes to "shared writable" memory pages: These pages are identified by address bit 9 being set. The SPDI Box re-issues the write to memory (with bit 9 suppressed) and then sends "cache zapper" bus requests to all other active processors.
• Cache Invalidation: These "cache zapper" requests force other processors to invalidate any copies of that specific data in their caches, ensuring all processors access the most current version.
• Handles "interlock read" requests: For these specific read operations, the SPDI Box also re-issues the read (with bit 9 suppressed) and can enter a "selective busy" state. In this state, it only responds to the initiating processor until a "write release" request is received, managing concurrent access to shared resources.
• Hardware Footprint: It's a small unit, estimated to be a fraction of a board (17-18 Macro Cell Arrays), and it's suggested its functionality could be integrated into a Dolphin Bus Repeater for efficiency and reliability.

The accompanying memoranda ("Shared Pages in Multiprocessor Dolphin Systems," dated August 7, 1978, July 20, 1978, and July 18, 1978) provide the broader context for the SPDI Box. They detail the system-level scheme for handling "shared writable pages," which are memory pages that have been written to by one processor and are referenced by others.

• Problem: Maintaining consistency for cached data across multiple processors.
• Solution Components:
  • Core Status Table (CST): Uses multiple bits (one per processor, plus a "modified" bit) to track which processors have referenced or modified a page.
  • Address Bit 9: Used to designate a page as "writethrough" cache status, which then involves the SPDI Box.
  • Transition to Shared Writable: A complex process involving page faults, CST updates, cache sweeps (to invalidate data), and inter-processor messages to flush page table caches.
  • Interlock Instructions: Explicit instructions (like AOSE) are handled by the MBOX in conjunction with the SPDI Box to manage critical sections and prevent deadlocks.

In essence, the SPDI Box is a critical hardware component within a larger software and hardware architecture designed to ensure data consistency and prevent cache coherence issues in Digital Equipment Corporation's multiprocessor Dolphin systems by actively invalidating stale data and mediating access to shared memory pages.