Dolphin Mbox Functional Specification Aug78

This document is a functional specification for the Dolphin Mbox, a key subsystem of the Dolphin central processor. The Mbox's core components include a microcontroller, a data cache, a page table cache, and a bus interface.

Its primary functions are:

• Data and Instruction Caching: Manages a 2048-word cache for Pbox (Ebox, Ibox, and FPA) instructions and data.
• Virtual Address Translation: Performs virtual-to-physical address translation using a 512-entry page table cache.
• Dolphin Bus Interface: Controls and interfaces with the Dolphin Bus for interrupts and memory requests.
• Microcoded Control: Utilizes a fast, pipelined microcoded controller to manage bus operations, cache refills, sweeps, writebacks, and invalidations, enhancing speed and minimizing complex hardwired logic.
• Error Recovery: Implements robust error recovery through Error Correction Code (ECC) and specialized hardware/software for memories and bus signals, aiming for most errors to be non-fatal, with retry and logging mechanisms.
• Multiprocessor Support: Designed to support high-performance symmetrical multiprocessing (up to four processors) with automatic cache coherence for shared pages.

The Mbox is built using ECL 256x4 bit memories and Macro cell array LSI logic. Performance goals include a 50-nanosecond cache access time and an improved page table hit rate compared to its predecessor (KL10). While expandable in cache size (2K-8K words), the physical address space is not. Certain functions like Universal Base Register (UBR) and Executive Base Register (EBR) handling, and the "Map" instruction, are offloaded to the Ebox microcode.