Dolphin IBOX EBOX Functional Spec May78

This interoffice memorandum from June 1978 (with a first printing in July 1976) details the functional specification and justification for a multi-processor design within the Dolphin CPU, specifically employing an Instruction Box (IBOX) and an Execution Box (EBOX).

Key Points:

• Purpose: The design aims to achieve 1.5 times the speed of the KL10 by distributing tasks between two tightly-coupled, microcoded processors (IBOX and EBOX) that together execute the complete PDP-10 instruction set.

• Task Division:

  • IBOX: Handles all instruction fetches, effective address calculations, and completes instructions that only affect the Program Counter (PC) (e.g., skips, jumps, tests). It does not write results.
  • EBOX: Performs all remaining computations and stores results.

• Rationale: This architectural split is based on:

  • Benchmarking: Approximately one-third of instructions executed do not store results, only affecting the PC, suggesting a dedicated processor could handle these.
  • Conflict Studies: Low conflict rates (less than 15%) were observed between instruction results and the effective address computation of subsequent instructions, indicating potential for parallel execution.
  • Simulation: An IBOX/EBOX configuration showed significant overlap, completing a MOVE/ADD sequence in 19 clock ticks compared to 27 on a similar KS10 data path.

• IBOX/EBOX Interface:

  • Communication is handled via "last registers" (Last IR/AC, Last E, Last PC) which pass instruction opcode, AC, calculated effective address, and PC information to the EBOX.
  • An interlock mechanism ensures the IBOX pauses until the EBOX is ready for new data.
  • Conflict logic, using comparators, manages operand fetching by checking for expected result writes by the EBOX. The IBOX can also ignore conflicts for specific instruction types it knows won't be written by the EBOX.

• Data Path Features:

  • EBOX Data Path: Features a 36-bit wide data path, a 16-word two-port register file (replacing multiple KL10 registers), combined VMA/MQ registers for efficiency, a 2901-style ALU, and a modified shift matrix. While efficient for PDP-10 instructions, fast floating-point operations are intended for a dedicated accelerator rather than the basic 36-bit machine to reduce cost.
  • IBOX Data Path: Includes a limited 36-bit ALU primarily for effective address calculations.

• Other Details: The document also mentions an 18-bit "magic number field" in microcode for improved constant/mask handling, half-word parity checking, and lists various Digital Equipment Corporation trademarks.

The document includes several attached diagrams (IBOX Data Path, EBOX Data Path, Timing, Fortran Accelerator Data Connections) which are not provided in the text.